aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
AgeCommit message (Collapse)Author
2011-09-07Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ↵James Molloy
handling to llvm-mc. Reviewed by Owen Anderson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Merge the ARM disassembler header into the implementation file, since it is ↵Owen Anderson
not externally exposed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Fix 80 columns violations.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Fix up r137380 based on post-commit review by Jim Grosbach.James Molloy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138948 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31The asm parser currently selects the wrong encoding for non-conditional ↵Owen Anderson
Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30Fix issues with disassembly of IT instructions involving condition codes ↵Owen Anderson
other the EQ/NE. Discovered by roundtrip testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138840 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26Improve encoding support for BLX with immediat eoperands, and fix a BLX ↵Owen Anderson
decoding bug this uncovered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26Spelling fail.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We ↵Owen Anderson
were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26Update for feedback from Jim.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26ARMDisassembler: Always return a size, even when disassembling fails.Benjamin Kramer
This should fix PR10772. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26Support an extension of ARM asm syntax to allow immediate operands to ADR ↵Owen Anderson
instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT ↵Owen Anderson
instructions when decoding their successors. This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25Port over additional encoding tests to decoding tests, and fix an operand ↵Owen Anderson
ordering bug this exposed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Perform more thorough checking of t2IT mask parameters, which fixes all ↵Owen Anderson
remaining crashers when disassembling the entire 16-bit instruction space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138507 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Be careful not to walk off the end of the operand info list while updating ↵Owen Anderson
VFP predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng
These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Be stricter in enforcing IT instruction predicate values, so that we don't ↵Owen Anderson
end up trying to print out an illegal predicate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23Fix decoding of Thumb2 prefetch instructions, which account for all the ↵Owen Anderson
remaining Thumb2 decoding failures found by randomized testing so far. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same ↵Owen Anderson
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22Reject invalid imod values in t2CPS instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138306 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming ↵Owen Anderson
majority of decoder crashes detected by randomized testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22Fix another batch of VLD/VST decoding crashes discovered by randomized testing.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22Correct writeback handling of duplicating VLD instructions. Discovered by ↵Owen Anderson
randomized testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add ↵Owen Anderson
more tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST ↵Owen Anderson
for the purposes of decoding all operands except the predicate. Found by randomized testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs ↵Owen Anderson
have it unset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18Remember to fill in some operands so we can print _something_ coherent even ↵Owen Anderson
when decoding the CPS instruction soft-fails. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18Improve handling of failure and unpredictable cases for CPS, STR, and SMLA ↵Owen Anderson
instructions. Fixes a large class of disassembler crashes found by randomized testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17Tidy up. 80 columns.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137881 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17ARM clean up the imm_sr operand class representation.Jim Grosbach
Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17Be more careful in the Thumb decoder hooks to avoid walking off the end of ↵Owen Anderson
the OpInfo array. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137838 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17Allow the MCDisassembler to return a "soft fail" status code, indicating an ↵Owen Anderson
instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. Patch by James Molloy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16Separate out Thumb1 instructions that need an S bit operand from those that ↵Owen Anderson
do not, for the purposes of decoding them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the ↵Owen Anderson
Thumb2 NEON decoding hooks to bring us closer to correctness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137686 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM ↵Owen Anderson
mode. Update tests to reflect this fact. Patch by James Molloy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15Fix problems decoding the to/from-lane NEON memory instructions, and add a ↵Owen Anderson
comprehensive NEON decoding testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12Fix some remaining issues with decoding ARM-mode memory instructions, and ↵Owen Anderson
add another batch of tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12Fix decoding of ARM-mode STRH.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137499 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12Fix decoding of pre-indexed stores.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12Separate decoding for STREXD and LDREXD to make each work better.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM STRT assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11Add another accidentally omitted predicate operand.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11Add missing predicate operand on SMLA and friends.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11Fix decoding support for STREXD and LDREXD.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11Continue to tighten decoding by performing more operand validation.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11ARM STRBT assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11Tighten operand decoding of addrmode2 instruction. The offset register ↵Owen Anderson
cannot be PC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-04-30 08:43:53 +0000