diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-18 22:47:44 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-18 22:47:44 +0000 |
| commit | 78affc9ea1978d707b376180ec559b62fbf9ea05 (patch) | |
| tree | 0173cdf2769e8dcd68456a75c8852ed12ad7fd00 /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 846dd95f87f62e2faa6092f99b521ecd9790121a (diff) | |
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 40a7936cfe..a57102c6e1 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -927,6 +927,8 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STC2L_OPTION: case ARM::LDCL_POST: case ARM::STCL_POST: + case ARM::LDC2L_POST: + case ARM::STC2L_POST: break; default: Inst.addOperand(MCOperand::CreateReg(0)); @@ -946,6 +948,8 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, switch (Inst.getOpcode()) { case ARM::LDCL_POST: case ARM::STCL_POST: + case ARM::LDC2L_POST: + case ARM::STC2L_POST: imm |= U << 8; case ARM::LDC_OPTION: case ARM::LDCL_OPTION: |