diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-11 20:47:56 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-11 20:47:56 +0000 |
| commit | 508e1d3db536b736063385eb1f885b446a1385ca (patch) | |
| tree | fd73f5bfa0042028762a8d0803e14f0af2ad8b9a /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | bb688cec09d08fb4c5e17d82c86bba11f0ce3168 (diff) | |
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 8cfb21793e..d2809f0c2c 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -941,6 +941,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, switch (Inst.getOpcode()) { case ARM::STR_POST_IMM: case ARM::STR_POST_REG: + case ARM::STRB_POST_IMM: + case ARM::STRB_POST_REG: case ARM::STRTr: case ARM::STRTi: case ARM::STRBT_POST_REG: @@ -957,6 +959,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, switch (Inst.getOpcode()) { case ARM::LDR_POST_IMM: case ARM::LDR_POST_REG: + case ARM::LDRB_POST_IMM: + case ARM::LDRB_POST_REG: case ARM::LDR_PRE: case ARM::LDRBT_POST_REG: case ARM::LDRBT_POST_IMM: |