diff options
author | Owen Anderson <resistor@mac.com> | 2011-08-23 17:51:38 +0000 |
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committer | Owen Anderson <resistor@mac.com> | 2011-08-23 17:51:38 +0000 |
commit | 82265a2c72b0f2d0daeab4985c9509d8405f51ef (patch) | |
tree | edc9ec5b076b3f5d588d9e5cc096018b052c017f /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
parent | 20a05be15ea5271ab6185b83200fa88263362400 (diff) |
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 5711b69796..c4b2f613cc 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2392,9 +2392,15 @@ static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = Success; - if (Inst.getOpcode() != ARM::t2PLDs) { - unsigned Rt = fieldFromInstruction32(Insn, 12, 4); - CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); + switch (Inst.getOpcode()) { + case ARM::t2PLDs: + case ARM::t2PLDWs: + case ARM::t2PLIs: + break; + default: { + unsigned Rt = fieldFromInstruction32(Insn, 12, 4); + CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); + } } unsigned Rn = fieldFromInstruction32(Insn, 16, 4); |