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| author | Jim Grosbach <grosbach@apple.com> | 2011-08-11 22:18:00 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-08-11 22:18:00 +0000 |
| commit | 342ebd5f380637d965504dcc350f9d0d79bbe599 (patch) | |
| tree | e5f9dc68a464f6a086a0285e618744082d821015 /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 41ff834e91a7f56dab18fbd7cdc03895197a923f (diff) | |
ARM STRT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 240293a2e6..201ccf8892 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -945,8 +945,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::STR_POST_REG: case ARM::STRB_POST_IMM: case ARM::STRB_POST_REG: - case ARM::STRTr: - case ARM::STRTi: + case ARM::STRT_POST_REG: + case ARM::STRT_POST_IMM: case ARM::STRBT_POST_REG: case ARM::STRBT_POST_IMM: if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; |