diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-12 20:36:11 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-12 20:36:11 +0000 |
| commit | 0d09499cf3e2d927cdc53ec79895303ac12808ac (patch) | |
| tree | 32a315f96bed5a0704fa0cf986553514ac552cd1 /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | e6e8826870bee3facb04f950f0bd725f8a88623d (diff) | |
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 29 |
1 files changed, 10 insertions, 19 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index b3db84947d..5cebabc65b 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -129,8 +129,6 @@ static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); -static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, @@ -970,6 +968,7 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::LDRB_POST_IMM: case ARM::LDRB_POST_REG: case ARM::LDR_PRE: + case ARM::LDRB_PRE: case ARM::LDRBT_POST_REG: case ARM::LDRBT_POST_IMM: case ARM::LDRT_POST_REG: @@ -1123,6 +1122,15 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST: + case ARM::LDRH: + case ARM::LDRH_PRE: + case ARM::LDRH_POST: + case ARM::LDRSH: + case ARM::LDRSH_PRE: + case ARM::LDRSH_POST: + case ARM::LDRSB: + case ARM::LDRSB_PRE: + case ARM::LDRSB_POST: case ARM::LDRHTr: case ARM::LDRSBTr: if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) @@ -2451,23 +2459,6 @@ static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, return true; } -static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { - bool isImm = fieldFromInstruction32(Val, 9, 1); - bool isAdd = fieldFromInstruction32(Val, 8, 1); - unsigned imm = fieldFromInstruction32(Val, 0, 8); - - if (!isImm) { - if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false; - Inst.addOperand(MCOperand::CreateImm(!isAdd << 8)); - } else { - Inst.addOperand(MCOperand::CreateReg(0)); - Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8))); - } - - return true; -} - static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { switch (Val) { |