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| author | Owen Anderson <resistor@mac.com> | 2011-08-26 19:39:26 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-26 19:39:26 +0000 |
| commit | 1af7f7291d0689e2d58f900c9b5ecaddec56caa1 (patch) | |
| tree | e411bf52f2f9fa81312377e17514a880cc66cda1 /lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 0f9d34c71d4f4ea83912c45f99ed286557ea189c (diff) | |
Update for feedback from Jim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138642 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 7652e8031e..b58cca32af 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2319,13 +2319,13 @@ static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); switch(Inst.getOpcode()) { + default: + return Fail; case ARM::tADR: - break; + break; // tADR does not explicitly represent the PC as an oeprand. case ARM::tADDrSPi: Inst.addOperand(MCOperand::CreateReg(ARM::SP)); break; - default: - return Fail; } Inst.addOperand(MCOperand::CreateImm(imm)); |