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AgeCommit message (Expand)Author
2012-12-24Use a std::string rather than a dynamically allocated char* buffer.Benjamin Kramer
2012-12-24CostModel: We have API for checking the costs of known shuffles. This patch addsNadav Rotem
2012-12-24Some x86 instructions can load/store one of the operands to memory. On SSE, t...Nadav Rotem
2012-12-24Change the codegen Cost Model API for shuffeles. This patch removes the API f...Nadav Rotem
2012-12-23CostModel: Change the default target-independent implementation for findingNadav Rotem
2012-12-23whitespaceNadav Rotem
2012-12-23Rename a function.Nadav Rotem
2012-12-23Loop Vectorizer: Update the cost model of scatter/gather operations and makeNadav Rotem
2012-12-22X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available.Benjamin Kramer
2012-12-22X86: Emit vector sext as shuffle + sra if vpmovsx is not available.Benjamin Kramer
2012-12-21In some cases, due to scheduling constraints we copy the EFLAGS.Nadav Rotem
2012-12-21[mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardwareAkira Hatanaka
2012-12-21[mips] Refactor SYNC and multiply/divide instructions.Akira Hatanaka
2012-12-21[mips] Refactor BAL instructions.Akira Hatanaka
2012-12-21[mips] Fix encoding of BAL instruction. Also, fix assembler test case whichAkira Hatanaka
2012-12-21[mips] Refactor jump, jump register, jump-and-link and nop instructions.Akira Hatanaka
2012-12-21[mips] Refactor load/store left/right and load-link and store-conditionalAkira Hatanaka
2012-12-21[mips] Refactor load/store instructions.Akira Hatanaka
2012-12-21[mips] Remove unnecessary isPseudo parameter.Akira Hatanaka
2012-12-21[mips] Refactor LUI instruction.Akira Hatanaka
2012-12-21[mips] Refactor count leading zero or one instructions.Akira Hatanaka
2012-12-21[mips] Refactor sign-extension-in-register instructions.Akira Hatanaka
2012-12-21[mips] Refactor instructions which copy from and to HI/LO registers.Akira Hatanaka
2012-12-21[mips] Refactor logical NOR instructions.Akira Hatanaka
2012-12-21[mips] Move instruction definitions in MipsInstrInfo.td.Akira Hatanaka
2012-12-21R600: Coding style - remove empty spaces from the beginning of functionsTom Stellard
2012-12-21R600: Fix MAX_UINT definitionTom Stellard
2012-12-21R600: Add SHADOWCUBE to TEX_SHADOW patternTom Stellard
2012-12-21Cleanup compiler warnings on discarding type qualifiers in casts. Switch to C...Benjamin Kramer
2012-12-21X86: Match pmin/pmax as a target specific dag combine. This occurs during vec...Benjamin Kramer
2012-12-21Remove duplicate includes.Roman Divacky
2012-12-21R600: Expand vec4 INT <-> FP conversionsTom Stellard
2012-12-21X86: Match the SSE/AVX min/max vector ops using a custom node instead of intr...Benjamin Kramer
2012-12-21Add a missing "virtual" keyword.Nadav Rotem
2012-12-21Add ARM cortex-r5 subtarget.Quentin Colombet
2012-12-21Improve the X86 cost model for loads and stores.Nadav Rotem
2012-12-21BB-Vectorizer: Check the cost of the store pointer typeNadav Rotem
2012-12-21Call llvm_unreachable instead of assert.Reed Kotler
2012-12-20Add an MF argument to MI::copyImplicitOps().Jakob Stoklund Olesen
2012-12-20MachineInstrBuilderize ARM.Jakob Stoklund Olesen
2012-12-20MachineInstrBuilderize NVPTX.Jakob Stoklund Olesen
2012-12-20Revert "Adding support for llvm.arm.neon.vaddl[su].* and"Bob Wilson
2012-12-20On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,Evan Cheng
2012-12-20Remove MCTargetAsmLexer and its derived classes now that edis,Roman Divacky
2012-12-20Adding support for llvm.arm.neon.vaddl[su].* andRenato Golin
2012-12-20Implement cfi_def_cfa_offset. "Make check" test case for this comming in theReed Kotler
2012-12-20There is one more patch to finish large frames. Make sure we assertReed Kotler
2012-12-20Add constant extender support to GP-relative load/store instructions.Jyotsna Verma
2012-12-20Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps.Jyotsna Verma
2012-12-20set register class properly for mips16 hereReed Kotler