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2020-03-16Flash driver for STM32G0xx and STM32G4xxAndreas Bolsch
Flash module of STM32G0/G4 family is quite similar to the one of STM32L4, so only minor changes are required, in particular adaption of flash loader to Cortex-M0. Register addresses passed to flash loader to simplify integration of L5. Added re-probe after option byte load. Added flash size override via cfg file. WRPxxR mask now based on max. number of pages instead of fixed 0xFF, as G4 devices fill up unused bits with '1'. Sizes in stm32l4_probe changed to multiples of 1kB. Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE. Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB. This handling isn't optimal as the bank size includes the size of the gap. WB not tested. Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593 Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4807 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-14tcl/target: Fix naming of RZ/A1 SoCMarek Vasut
The RZ/A1 is not part of the R-Car family, but is rather an RZ family. Fix the naming. Change-Id: I5f882b2467e87e534e0f1c827554e664a7d55664 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5445 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-12target: add examine-fail eventTomas Vanek
A configuration script may want to check the reason why examine fails e.g. device has security lock engaged. tcl/target/kx.cfg and klx.cfg is modified to use the new event for testing of the security lock of Kinetis MCU Change-Id: Id1d3a79d24e84b513f4ea35586cd2ab0437ff9b3 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4289 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12Add target config for STM8S103 chip...Anton V. Kirilchik
Change-Id: I693e5b7933fc61956010a96be57ee6eb8abd3c31 Signed-off-by: Anton V. Kirilchik <kosmonaffft@gmail.com> Reviewed-on: http://openocd.zylin.com/5422 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-09tcl/target: Unify Renesas R-Car JTAG reset configMarek Vasut
Both Gen2 and Gen3 used the same init_reset{} implementation, pull it into common file and include it from both generations. Moreover, this behavior is SoC specific, not board specific, so move the common init_reset into target/ directory. Change-Id: I5489a4bff9a786da8cb7fd7a515b0c9ce9dc16e3 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5400 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-07bluenrg-x: simplyfied the driverluca vinci
Adopted only fast algorithm for flash programming: - write_word and write_byte methods have been removed. - start and end write alignments have been defined. Moved flash controller registers offsets in a common file shared with the flash algorithm. - the flash base address is passed to the flash algorithm as a parameter. Removed unused functions Change-Id: I80aeab3994e477044bbcf02e66d9525dae0cb491 Signed-off-by: luca vinci <luca.vinci@st.com> Reviewed-on: http://openocd.zylin.com/5393 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Michele Sardo <msmttchr@gmail.com>
2020-03-07bluenrg-x: added support for BlueNRG-LP deviceluca vinci
Extended bluenrg-x flash driver with BlueNRG-LP flash controller. Changes include: - register set for the flash controller - made software structure prone to support more easily future devices - updated target config file Change-Id: I2e2dc70db32cf98c62e3a43f2e44a4600a25ac5b Signed-off-by: luca vinci <luca.vinci@st.com> Reviewed-on: http://openocd.zylin.com/5343 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-03tcl/target: Drop old Renesas Gen2 SoC configsMarek Vasut
Drop old Renesas Gen2 SoC configurations, as they were superseded by the new unified config. Change-Id: I7c2ccbdc13b01a552ce9cafdc1538f226beaa9f2 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5399 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-02tcl/target: Add unified config for Renesas R-Car Gen2 targetsMarek Vasut
Add configuration for the Renesas R-Car Generation 2 targets. These are SoCs with Cortex A15s and A7s. All cores currently supported by OpenOCD are supported here as well as two new cores, M2N and V2H, for the sake of support completeness. Change-Id: Ib6fe70a91360b4f8bd69822ee28b6dea530cfa0a Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5397 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-02tcl/target: Abort on invalid SoC selection on R-Car Gen3Marek Vasut
Instead of printing error message and continue, abort on invalid SoC selection right away. Change-Id: I9c7a7111b590c6c49a0826562380b881a162a8dc Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5439 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-02-24coding style: add newline at end of text filesAntonio Borneo
Some text file is missing newline at EOF. Add it. Change-Id: Ieebc790096f40961283c644642e56fde975e957f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5167 Tested-by: jenkins
2020-02-08tcl: Remove executable bitMarc Schink
Change-Id: Ib452435b13c3cb8d14453d983151936238b9601d Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/5419 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-02-06tcl: fix remaining scripts after rework adapter commandsAntonio Borneo
Some script have been added or modified after the patches for reworking the adapter commands were pushed in gerrit. Such scripts use the old command syntax and trigger a "deprecated" warning at runtime. Fix them with the same sed commands used for the other scripts: sed -i 's/^interface /adapter driver /' $(find tcl/ -type f) sed -i 's/adapter_khz/adapter speed/g' $(find tcl/ -type f) sed -i 's/adapter_nsrst_delay/adapter srst delay/g' $(find tcl/ -type f) sed -i 's/adapter_nsrst_assert_width/adapter srst pulse_width/g' $(find tcl/ -type f) Change-Id: I0824d6c506a9af3eb9129b74c02a92b4eb1b100d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5424 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins
2020-01-29tcl: replace the deprecated commands with "adapter ..."Antonio Borneo
Avoid annoying "deprecated" messages while running the scripts distributed with OpenOCD code. Change automatically created with commands sed -i 's/adapter_khz/adapter speed/g' $(find tcl/ -type f) sed -i 's/adapter_nsrst_delay/adapter srst delay/g' $(find tcl/ -type f) sed -i 's/adapter_nsrst_assert_width/adapter srst pulse_width/g' $(find tcl/ -type f) Minor indentation issue fixed manually in tcl/board/at91sam9g20-ek.cfg tcl/target/at91sam9260_ext_RAM_ext_flash.cfg Change-Id: I425fd56c0c88cd6b06124621306eeb89166dfe71 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5284 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-01-16flash/nor: add support of STM32WB on top STM32L4 flash driverTarek BOCHKATI
Change-Id: I9fb6700085d817d35a691f6484193f67939a4e0f Signed-off-by: Laurent LEMELE <laurent.lemele@st.com> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/4933 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-01-02tcl: update scripts after "jtag_reset" got deprecatedAntonio Borneo
Avoid annoying "deprecated" messages in the scripts distributed with OpenOCD code. Change-Id: I82d27cd420db30f0653efbd286a627ef56a8c1fd Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5287 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-01-02tcl/target: swm050: fix to allow to use with ST-LinkIcenowy Zheng
Currently the code assumes the adapter uses raw SWD, and the expected ID code of the CPU is even wrong. An adapter speed is also not specified. All these prevents the config file to be used with ST-Link. Fix the config file, to allow it to be used with ST-Link. Change-Id: I1244320fabfe8ee23da5a56a592dbeddc72cc8d5 Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-on: http://openocd.zylin.com/5297 Tested-by: jenkins Reviewed-by: Caleb Szalacinski <contact@skiboy.net> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-12-07target/stm32h7x: add support of dual core variant of STM32H7Tarek BOCHKATI
STM32H7x7 and STM32H7x5 devices contains two cores : CM7 + CM4 The second core creation is only done when * DUAL_CORE variable is set to true * non HLA interface is used A second check for the second core existence is done in cpu1 examine-end Once the second core is detected it gets examined. Furthermore, the script provides a configurable CTI usage in order to halt the cores simultaneously. Tested on Rev X and V devices. PS: the indentation was a mix of spaces and tabs, all changed to tabs. Change-Id: Iad9c30826965ddb9be5dee628bc2e63f953bbcb8 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5130 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-11-27target/stm32h7x: Use AP2 to access DBGMCU when non HLA adapter is usedChristopher Head
The STM32H7 has three access ports. The DBGMCU component is available through AP0 at 0x5C001000 and through AP2 at 0xE00E1000. Using the latter is preferable for early configuration because it works in all power states and while SRST is asserted, whereas the former does not. Change-Id: Iaf8f01d769efb6655040060a8e1e951e1f7e50ab Signed-off-by: Christopher Head <chead@zaber.com> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/4742 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-10-18tcl/target: Add Infineon TLE987xAndreas Färber
Prepare a config for Infineon TLE9879. Change-Id: Ic667ae822fd514cac365993bc3f39b4185f1a118 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/4339 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-10-18stm32l0|l1: don't corrupt RCC registersFelipe Balbi
instead of overwriting Reset settings, let's read-modify-write RCC registers. Change-Id: I21b7e26e6007d3c3d73803c681c980c6947f5910 Signed-off-by: Felipe Balbi <balbi@kernel.org> Reviewed-on: http://openocd.zylin.com/3601 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-10-15Update FTDI C232HM cfg, and add two new cfgs from cable modem researchAl Dyrius
Change-Id: Idbeffcd5ff4380b1e7c9fd5ef6ba3ca77cc22d99 Signed-off-by: Al Dyrius <aldyrius42@gmail.com> Reviewed-on: http://openocd.zylin.com/5307 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-09-08flash/nor: flash driver for Synwit SWM050 MCUsCaleb Szalacinski
SWM050 is a series of MCU product by Foshan Synwit Tech, which is available in TSSOP-8 or SSOP-16 packages. Adds flash driver for the internal 8KiB flash of the MCU. The registers are based on reverse engineering the J-Flash blob provided by the vendor. Also adds a pre-made cfg file. Change-Id: I0b29f0c0d062883542ee743e0750a4c6b6609ebd Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Caleb Szalacinski <contact@skiboy.net> Reviewed-on: http://openocd.zylin.com/4927 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-06-19tcl/target: Add initial Microchip SAML1x supportMarc Schink
There is not flash bank support at the moment. Change-Id: I833c009d9d21cdeb70b57d67eb557d50ed0fb4de Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/5205 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-06-19Configs for ARM corelink SSE-200 target and Musca A boardOmair Javaid
This patch adds configuration files for ARM CoreLink SSE-200 SoCs. Also adds configuration file for SSE-200 based Musca A board. Flash programming support for Musca A QSPI flash is still not functional. This configuration will be updated once that support lands into OpenOCD. Please refer to ARM documentation for more information about SSE-200 and Musca A. Change-Id: Id3783c34d6e2609d659ef91c0bf7252c39439874 Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/5006 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-05-23stm32f7x: Use CHIPNAME-specific name for ITCM bankChristopher Head
Change-Id: Icf67eaecd56ac3fb88bcfa2b7084b846109454e6 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/5102 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2019-05-20tcl/target: Fix V3M/V3H SoC chipnameMarek Vasut
The V3M SoC is R8A77970 while the V3H SoC is R8A77980 . Update the CHIPNAME and swap the SoCs to keep the list sorted. Change-Id: I7e1777c0c7181e5e0beac98333f2047cb443d0df Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5140 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-05-20tcl/target: Add Renesas RZ/A1H targetMarek Vasut
Add configuration for the Renesas RZ/A1H target. This is an SoC with one Cortex A9 ARMv7a core and up to 10 MiB of on-SoC SRAM. Change-Id: I20fd54b385fe1ba1cc325451c3fdfa3a835d4884 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5141 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-05-14tcl/psoc4: remove "ocd_" prefixed commandsAntonio Borneo
The commands prefixed with "ocd_" are removed. Remove them from configuration files. Change-Id: Ib44627ee17a39f3d06b479507ab5a025073bf9a8 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5090 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2019-04-24target/imx8m: Cleanup defaultsLeonard Crestez
* Add mem_ap for direct access to axi bus (without halting cpu) * Mark m4 core with -defer-examine because it's not used by default * Make a53.0 default target since it's the boot core Change-Id: Id031533c5d4af346eb08a9ac2532fa1bca602913 Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-on: http://openocd.zylin.com/5036 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-04-24target/imx6ul: Initial supportLeonard Crestez
Unlike the rest of imx6 the 6UL 6ULL 6ULZ chips are based on Cortex-A7 which is at a different address so a custom script is required. Tested on imx6ull-14x14-evk Change-Id: I72822d2241045c318389fadbc66d7aaabaaf4cb5 Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-on: http://openocd.zylin.com/5040 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-04-24target/imx6sx: Initial supportLeonard Crestez
Unlike the rest of imx6 a Cortex-M4 was added with a second CoreSight DAP so a separate script is required. Tested on imx6sx-sdb running linux Change-Id: I1561910b233015f42508f341175822c0827655ec Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-on: http://openocd.zylin.com/5041 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-04-24target/imx7ulp: Initial supportLeonard Crestez
Unlike imx7d/solo supported by imx7.cfg the M4 core is on a different AP and is always running by default so no -defer-examine is required. There is also only one Cortex-A7 Tested on imx7ulp-evk Change-Id: Ifa923d1b9a372c788e6654bc2233fd4d9073a32d Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-on: http://openocd.zylin.com/5043 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-04-10target/imx6: Update list of supported TAPIDsLeonard Crestez
Copy all SJC TAPIPs from imx6 reference manuals. Some imx6 chips are based on Cortex-A7 or have an additional Cortex-M4 and need separate scripts. Change-Id: I3b07d94058c2c5e6313cfc8bb43134a90682a62e Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-on: http://openocd.zylin.com/5034 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-04-10target/imx6: Fix indentation in DAP_TAPID handlingLeonard Crestez
OpenOCD scripts are usually indented with 4 spaces but here there are 8. Change-Id: Iaad53e3b377d246d99119bb7bb5fd75d4422f564 Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-on: http://openocd.zylin.com/5039 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-04-10target/imx6: Add -ignore-versionLeonard Crestez
Looking through imx6 manuals all of them claim that "In follow-on silicon revisions the ID value is subject to change by incrementing the first nibble". Handle this by passing -ignore-version to jtag newtap command. Change-Id: I7fc4779f9757d527ea20a5174a8c90f919580013 Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-on: http://openocd.zylin.com/5031 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-04-10target/imx7: Add ahb mem_apLeonard Crestez
This allows bus access even when CPU is off. Change-Id: I2d5c5581cd0169aecb92ac7b610810988a8dcef4 Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-on: http://openocd.zylin.com/5032 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-04-09topic: Remapped Flash over ITCM region in STM32F7x scriptRocco Marco Guglielmi
This patch remaps the Flash over ITCM region as virtual to ensure that any breakpoint placed in this area will be automatically set as an hardware breakpoint. This patch is a fix to a regression introduced with changes #4429. Change-Id: I03d46d8537ef06b33a3d4a2328274667c6481969 Signed-off-by: Rocco Marco Guglielmi <roccomarco.guglielmi@gmail.com> Reviewed-on: http://openocd.zylin.com/5097 Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Tested-by: jenkins
2019-03-27smp: replace commands smp_on/smp_off with "smp [on|off]"Antonio Borneo
Seams over-engineered having two separate commands to turn SMP on/off. Plus it is missing the possibility to dump the current status of SMP and would be weird adding an additional command for it. Moreover, such commands are replicated in few targets so it would make sense centralizing them. - Deprecate the commands "smp_on" and "smp_off". - Add a new command "smp" that accepts optional parameters "[on|off]" and prints the SMP status when run without parameters. This replaces the two commands above. - Put the deprecated and the new command handlers in smp.c - Update the documentation, except for mips_m4k, since it is not available yet. - Promote the macro foreach_smp_target to global context and use it where possible. Change-Id: Ia72841c1a3bd6edd4db4cc809046322f498617e6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4615 Tested-by: jenkins Reviewed-by: Graham Sanderson <graham.sanderson@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-03-27imx8m: add an m4 target to the imx8mAngus Ainslie
The imx8m also has a Cortex m4 so add a target for it. Change-Id: I2abf62b6232c547fe9b12507f459835b11c63a6d Signed-off-by: Angus Ainslie <angus@akkea.ca> Reviewed-on: http://openocd.zylin.com/4501 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-02-27flash: stm32f2/f4/f7: Add One-Time-Porgrammable (OTP) supportMoritz Fischer
The OTP is part of the flash memory. It has 512 (1024 for F7) bytes and is organized in 16 sectors with 32 (64 for F7) bytes each. The OTP is exposed as separate flash bank 1 and can be used with the usual flash commands. Writing the OTP can be done as follows: > stm32f2x otp 1 enable > flash write bank 1 foo.bin 0 > mdw 0x1fff7800 4 > verify_image foo.bin 0x1fff7800 > stm32f2x otp 1 disable Note: This patch is largely a rebase/cleanup of a patch from 2012 by Laurent Charpentier and he did most of the work. No new Clang-Analyzer warnings. Change-Id: I5e6371f6a7c7a9929c1d7907d6ba4724f9d20d97 Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: http://openocd.zylin.com/829 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-02-05flash/nor: flash driver and cfg for SAM E54, E53, E51 and D51Tomas Vanek
The new Microchip (former Atmel) series powered by Cortex-M4 looks very similar to older M0+ powered SAM D2x at the first sight. Unfortunately the new series differs a lot in important details. NVMCTRL has different register addresses, moved important bits and even changed binary command set. An universal driver for all SAM D/E would be very complicated. That's why a new driver was derived. Tested on Microchip SAM E54 Xplained Pro kit (board cfg included). Adjusted for the restructured dap support. Checked by valgrind and clang static analyzer. Change-Id: I26c67047a552076f4b207b9b89285a53d69b4ca4 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4272 Tested-by: jenkins Reviewed-by: Andres Vahter <andres.vahter@gmail.com>
2019-01-26tcl: Support for Analog Devices ADSP-SC58x / ADSP-SC584-EZBRDPeter Lawrence
The original script was broken by changes to the Cortex-A code. The recent introduction of the mem_ap target provided a new mechanism to allow the script to be fixed. This also adds an example board script for the ADSP-SC584-EZBRD. Change-Id: I36bc1ac6b6c036539f4175f1e65223ba10a35355 Signed-off-by: Peter Lawrence <majbthrd@gmail.com> Reviewed-on: http://openocd.zylin.com/4855 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-23Correct ZynqMP configuration to be appropriately namedJonathan McDowell
The xilinx_ultrascale.cfg target is actually the configuration for a ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad core A53. Update the filename/comments to reflect this, and include the tap IDs for all known FPGA cores for this part. Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047 Signed-off-by: Jonathan McDowell <noodles@earth.li> Reviewed-on: http://openocd.zylin.com/4850 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-01-08icepick.cfg: add cancel reset bit to TAP register writesEdward Fewell
The Agama family of devices (CC26x2/CC13x2) required an additional bit to be set when adding the core's TAP into the scan chain. The cancel reset bit 0x10000 tells the ICEPick to take the bus out of reset so that the other bits will take effect. This bit is a NOP on other devices and ICEPicks, so the change shouldn't adversely affect other devices. Change-Id: I9245eef0936ea7eea28ae84ab5e8ce05fa63af40 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4789 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2019-01-02NOR: lpc2000 Add support for LPC84x devicesRod Boyce
These devices differ from LPC8xx devices in that they have a different IAP entry point, but everything else is the same. Using Tcl to pass different IAP entry point. no new Clang analyser warnings and no new build sanitizers issues. Change-Id: I2d654dd250f416e74262c0228cad8713a283402f Signed-off-by: Rod Boyce <developer@teamboyce.co.uk> Reviewed-on: http://openocd.zylin.com/4684 Reviewed-by: Jean-Christian de Rivaz <jcamdr70@gmail.com> Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-12-23Add LPC8Nxx and NHS3xx support.Jean-Christian de Rivaz
Change-Id: I0bdbca8dd9b234aca355230af7269463c9f70bd1 Signed-off-by: Jean-Christian de Rivaz <jcamdr70@gmail.com> Reviewed-on: http://openocd.zylin.com/4515 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-12-11flash/nor: update CC26xx/CC13xx supportEdward Fewell
Added fixes found in additional code reviews. Remove inappropriate use of bank_number field and updated documentation to reflect the change. Restored functionality to cc2538.cfg file because previous change removed the cc26xx.cfg file because the flash support changes made it obsolete. Rolled the previous cc26xx.cfg file into cc2538.cfg and updated it to work with other recent changes. Tested using a SmartRF06 Evaluation board with embedded XDS100v3 and external XDs110. Change-Id: Ia19d00cf8055c5c0f1acc53aa23fd06a80fd2ebc Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4787 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-11-26tcl/target, board: remove useless gdb-attach event definitionsTomas Vanek
Since commit bae76053dc515252dc5c8235b9a848e461080c66 gdb-attach event is defined as halt by default. Remove useless and in case of bcm281xx wrong definitions of the event. Change-Id: I8e69780a93722eb9392673303f54d502e71eceb6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4763 Tested-by: jenkins Reviewed-by: Steven Stallion <sstallion@gmail.com>
2018-11-20tcl/target: ti_tms570.cfg restructure dap supportTomas Vanek
ti_tms570 was probably omitted in commit 2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f Change-Id: Idd4828fd5ea3641bda6c73c7f07a598c1e512ef6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4762 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-16 14:26:59 +0000