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2020-03-16flash/startup.tcl: add STM32G0 and G4 aliasesHEADmasterTarek BOCHKATI
STM32G0 and G4 uses the same flash driver as the stm32l4x Change-Id: Ic1c4be70aaee809536912e0390f07893efb9a082 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5482 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-16Flash driver for STM32G0xx and STM32G4xxAndreas Bolsch
Flash module of STM32G0/G4 family is quite similar to the one of STM32L4, so only minor changes are required, in particular adaption of flash loader to Cortex-M0. Register addresses passed to flash loader to simplify integration of L5. Added re-probe after option byte load. Added flash size override via cfg file. WRPxxR mask now based on max. number of pages instead of fixed 0xFF, as G4 devices fill up unused bits with '1'. Sizes in stm32l4_probe changed to multiples of 1kB. Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE. Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB. This handling isn't optimal as the bank size includes the size of the gap. WB not tested. Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593 Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4807 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-14tcl/target: Fix naming of RZ/A1 SoCMarek Vasut
The RZ/A1 is not part of the R-Car family, but is rather an RZ family. Fix the naming. Change-Id: I5f882b2467e87e534e0f1c827554e664a7d55664 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5445 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-14drivers: xds110: Fix errors in routine that togglesEdward Fewell
TCK during nSRST assert/deassert code. To support LPRF targets (CC13xx/CC26xx), TCK must be toggled for 50 ms while nSRST is asserted and right after it is released. This allows the core to halt in boot ROM before code is run that might interfere with debug access. The current routine has two issues. It shouldn't be run at all if the target is using SWD. And the delay needs to be a real-time 50 ms, so the number of TCK periods should be calculated off the set speed. Change-Id: If993031b84cf2a505ea67a6633602c4b01cd8e1e Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/5497 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-12target/cortex_a: add hypervisor modeAntonio Borneo
Hypervisor mode is present only if the optional virtualization extensions are available. Moreover, virtualization extensions require that also security extensions are implemented. Add the required infrastructure for the shadowed registers in hypervisor mode. Make monitor shadowed registers visible in hypervisor mode too. Make hypervisor shadowed registers visible in hypervisor mode only. Check during cortex_a examine if virtualization extensions are present and then conditionally enable the visibility of both hypervisor and monitor modes shadowed registers. Change-Id: I81dbb1ee8baf4c9f1a2226b77c10c8a2a7b34871 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5261 Tested-by: jenkins
2020-03-12armv7a: access monitor registers only with security extensionsAntonio Borneo
Accordingly to ARM DDI 0406C at B1.5, the security extensions for armv7a are optional extensions and can be detected by reading ID_PFR1. The monitor mode is part of the security extensions and the shadow registers "sp_mon", "lr_mon" and "spsr_mon" are only present with the security extensions. Read the register ID_PFR1 during cortex_a examine, determine if security extension is present and then conditionally enable the visibility of the monitor mode shadow registers. Change-Id: Ib4834698659046566f6dc5cd35b44de122dc02e5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5259 Tested-by: jenkins
2020-03-12target/armv4_5: remove unused macroAntonio Borneo
The macro ARMV4_5_CORE_REG_MODENUM() is unused. Remove it! Change-Id: I183df57bd86c9428710ea3583e43fba88fd26e0a Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5260 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
2020-03-12arm: Use different enum for core_type and core_modeAntonio Borneo
The fields core_type and core_mode use the same enum arm_mode but encode different information, making the code less immediate to read. Use a different enum arm_core_type for the field core_type. The code behavior is not changed. Change-Id: I60f2095ea6801dfe22f6da81ec295ca71ef90466 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5258 Tested-by: jenkins
2020-03-12arm: fix reg num for Monitor modeAntonio Borneo
Commit 2efb1f14f611 ("Add GDB remote target description support for ARM4") inserts two additional registers "sp" and "lr" in the table arm_core_regs[], thus shifting by two the position of the last three registers already present "sp_mon" moved from index 37 to 39 "lr_mon" moved from index 38 to 40 "spsr_mon" moved from index 39 to 41 Part of the code is updated (e.g. enum defining ARM_SPSR_MON and array arm_mon_indices[]), but it's missing the update of mapping in armv4_5_core_reg_map[]. Fix armv4_5_core_reg_map[]. Change-Id: I0bdf766183392eb738206b876cd9559aacc29fa0 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Fixes: 2efb1f14f611 ("Add GDB remote target description support for ARM4") Reviewed-on: http://openocd.zylin.com/5257 Tested-by: jenkins
2020-03-12ftdi: flush mpsse queue after a level change on reset pinsAntonio Borneo
The function ftdi_set_signal() does not propagate the pin change until next call to mpsse_flush(). Current code does not toggles immediately the reset pins if polling is turned off. Call mpsse_flush() at the end of ftdi_reset(). While there, remove the duplicated LOG message. Change-Id: I79eacfe4fc32b5cdf2dc1b78f3660d96988466bc Fixes: 8850eb8f2c51 ("swd: get rid of jtag queue to assert/deassert srst") Reported-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5431 Tested-by: jenkins Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-12jimtcl: update to tag 0.79Antonio Borneo
OpenOCD is stuck at jimtcl tag 0.77 that is 3 years old. The latest tag 0.79 (2019-11-20) is already used by debian build, which packs jim library separately, as shown in [1]. Today only the build for architecture powerpcspe is still not updated to latest package version. I have been using jim 0.79 since the day of the release, without any issue. Switch jimtcl to latest tag 0.79 [1] https://packages.debian.org/sid/openocd Change-Id: I3426e68c32f88ecde74d4278303925423db451e0 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5403 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-12target: fix crash with jimtcl 0.78Antonio Borneo
The jimtcl commit 41c5ff1809f5 ("jim.c: Fix Object leak in zlib support") https://repo.or.cz/jimtcl.git/commit/41c5ff1809f5 makes Jim_SetResultFormatted() freeing the parameters that have zero refcount. OpenOCD commit 559d08c19ed8 ("jim tests: use installed") adds the only code instance in OpenOCD that first passes a zero refcount object to Jim_SetResultFormatted() and then frees it. By switching jimtcl version to 0.78 or newer this causes a crash of OpenOCD. To trigger the crash in a telnet session, check that the current target is running and type: [target current] arp_waitstate halted 1 Remove the call to Jim_FreeNewObj() after the call to Jim_SetResultFormatted(). Change-Id: I5f5a8bca96a0e8466ff7b789fe578ea9785fa550 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5453 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-12jtag: report API reset as synchronousAntonio Borneo
The jtag API reset() is synchronous, but this was not highlighted in the description. Change-Id: I76ffb7eec97c8608cfbef0b9268ee18a5f50b221 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Fixes: 8850eb8f2c51 ("swd: get rid of jtag queue to assert/deassert srst") Reviewed-on: http://openocd.zylin.com/5471 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2020-03-12semihosting: add semihosting handlers to AArch64Tarek BOCHKATI
note: this works only when the PE is in AArch64 state Change-Id: Id6a336ca7d201df72bd1aaaeccce4185473fc1bd Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5474 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12cortex_a: warn on broken debug_base settingMatthias Welwarsky
A common problem with target configurations appears to be broken debug base address configuration. ARM DDI0406C.d specifies in App. D, 1.4.1, that bit 31 of the debug base address serves as identification of an external debugger, as opposed to an internal access to memory mapped debug registers by the CPU. External accesses are treated as privileged and require no debug authentification via the lock access register. Sometimes the base address of a debug component is wrong even in the targets' ROM table. In this case, the correct base address must be specified using the -dbgbase argument when creating the target. This patch adds a warning when bit 31 of the debug base address is not set, as a hint to the user. Change-Id: I9c41d85a138123c657ef655e3436a2aa39249dcc Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/5105 Tested-by: jenkins Reviewed-by: Tommy Vestermark <tov@vestermark.dk> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12target/armv8_opcodes: use T32 instructions when the PE is in AArch32 stateTarek BOCHKATI
As stated in ARM v8-A Architecture Reference Manual (ARM DDI 0487E.a) in Chapter H4.3 DCC and ITR access modes: Writes to EDITR trigger the instruction to be executed if the PE is in Debug state: - If the PE is in AArch64 state, this is an A64 instruction. - If the PE is in AArch32 state, this is a T32 instruction But in armv8_opcodes specifically in t32_opcodes we were using some A32 instructions for HLT, LDRx and STRx opcodes. Using the correct LDRx and STRx opcodes, fixes 16 and 8 bits memory access when the PE is in AArch32 state. Change-Id: Ib1acbdd4966297e7b069569bcb8deea3c3993615 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5346 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12target/aarch64: fix soft breakpoint when PE is in AArch32 stateTarek BOCHKATI
Before this patch aarch64_set_breakpoint was using either A64, or A32 HLT opcode by relying on armv8_opcode helper. This behaviors ignores the fact that in AArch32 state the core could execute Thumb-2 instructions, and gdb could request to insert a soft bkpt in a Thumb-2 code chunk. In this change, we check the core_state and bkpt length to know the correct opcode to use. Note: based on https://sourceware.org/gdb/current/onlinedocs/gdb/ARM-Breakpoint-Kinds.html if bkpt length/kind == 3, we should replace a 32-bit Thumb-2 opcode, then we use twice the 16 bits Thumb-2 bkpt opcode and we fix-up the length to 4 bytes, in order to set correctly the bpkt. Change-Id: I8f3551124412c61d155eae87761767e9937f917d Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5355 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12target/aarch64: fix minor stepping issue with gdbTarek BOCHKATI
when using step command from gdb the step happens without any issue, but aarch64_step call explicitly aarch64_poll which consumes the status change to HALTED, so it does not inform gdb that the step has finished. by removing this call, all is back to normal and openocd could inform gdb that the step has finished. Change-Id: I9366aecd20f7d52259b050b8653189b67d9299d0 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5354 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12target: add examine-fail eventTomas Vanek
A configuration script may want to check the reason why examine fails e.g. device has security lock engaged. tcl/target/kx.cfg and klx.cfg is modified to use the new event for testing of the security lock of Kinetis MCU Change-Id: Id1d3a79d24e84b513f4ea35586cd2ab0437ff9b3 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4289 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-12Add target config for STM8S103 chip...Anton V. Kirilchik
Change-Id: I693e5b7933fc61956010a96be57ee6eb8abd3c31 Signed-off-by: Anton V. Kirilchik <kosmonaffft@gmail.com> Reviewed-on: http://openocd.zylin.com/5422 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-03-10semihosting: reorganize semihosting commandsTarek BOCHKATI
the same semihosting handlers chain is declared twice: 1. in src/target/armv4_5.c 2. in src/target/riscv/riscv.c to make it simpler we moved the declaration into 'src/target/semihosting_common.c' under semihosting_common_handlers[]. then we used this into both of armv4_5.c and riscv.c Change-Id: If813b3fd5eb2476658f1308f741c4e805141f617 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5473 Tested-by: jenkins Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org> Reviewed-by: Tim Newsome <tim@sifive.com> Reviewed-by: Liviu Ionescu <ilg@livius.net>
2020-03-10flash/stm32h7x: fix bank sizes for devices with trimmed flashTarek BOCHKATI
STM32H7yxxI: dual independent 1 MByte banks STM32H7yxxG: dual independent 512 Kbyte banks STM32H7yxxB: single 128 Kbyte bank where y = [4/5] or [A/B] references: (documents are available in www.st.com) - STM32H7[4/5]x[G/I] : DS12110 Rev 7 >> 3.3.1 Embedded Flash memory - STM32H750xB : RM0433 Rev 6 >> Table 11. Flash memory organization on STM32H750xB devices - STM32H7[A/B]x[B/G/I] : RM0455 Rev 3 >> 4.3.4 Flash memory architecture and usage Change-Id: Ic9346964ef2554abf47f5832e25adfdc77bd323e Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5442 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com>
2020-03-09tcl/target: Unify Renesas R-Car JTAG reset configMarek Vasut
Both Gen2 and Gen3 used the same init_reset{} implementation, pull it into common file and include it from both generations. Moreover, this behavior is SoC specific, not board specific, so move the common init_reset into target/ directory. Change-Id: I5489a4bff9a786da8cb7fd7a515b0c9ce9dc16e3 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5400 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-07flash/nor: update support for TI MSP432 devicesEdward Fewell
Added fixes for issues found in additional code reviews. Fixed host Endianness issues with using buffer reads and writes instead of the *_u32 variants. Changed code that tried to ID banks by hardcode bank_number values to use instead the bank base address. This fixes problems using configurations with multiple devices. Note that this replaces Change 4786 which has been abandoned because of extensive changes to the code to stop IDing banks by name. And I think I really messed up a rebase/merge on the document file. Tested on MSP432P401R, MSP432P4111, and MSP432E401Y Launchpads. Change-Id: Id05798b3aa78ae5cbe725ee762a164d673ee5767 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/5481 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-07bluenrg-x: simplyfied the driverluca vinci
Adopted only fast algorithm for flash programming: - write_word and write_byte methods have been removed. - start and end write alignments have been defined. Moved flash controller registers offsets in a common file shared with the flash algorithm. - the flash base address is passed to the flash algorithm as a parameter. Removed unused functions Change-Id: I80aeab3994e477044bbcf02e66d9525dae0cb491 Signed-off-by: luca vinci <luca.vinci@st.com> Reviewed-on: http://openocd.zylin.com/5393 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Michele Sardo <msmttchr@gmail.com>
2020-03-07bluenrg-x: added support for BlueNRG-LP deviceluca vinci
Extended bluenrg-x flash driver with BlueNRG-LP flash controller. Changes include: - register set for the flash controller - made software structure prone to support more easily future devices - updated target config file Change-Id: I2e2dc70db32cf98c62e3a43f2e44a4600a25ac5b Signed-off-by: luca vinci <luca.vinci@st.com> Reviewed-on: http://openocd.zylin.com/5343 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-07helper/binarybuffer: fix clang static analyzer warningsTomas Vanek
Writing bits to an uninitialized buffer generated false warnings. Zero buffers before setting them by buf_set_u32|64() (do it only if bit-by-bit copy loop is used, zeroed buffer is not necessary if a fast path write is used) Change-Id: I2f7f8ddb45b0cbd08d3e249534fc51f4b5cc6694 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5383 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2020-03-07target/arm920t: fix clang static analyzer warningTomas Vanek
Change-Id: I570dfb8b20a3f187f1fe660343cf0b75691e2c30 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5375 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-07rtos/linux: fix use of memory after it is freedTomas Vanek
Discovered by clang static analyzer Change-Id: I9f64a67f281b95562d8fd6e2ebb0ae3f79ae8039 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5371 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-07jtag/drivers/openjtag: fix clang static analyzer warningsTomas Vanek
Change-Id: I900ce8157b3e220a4647871080bb9abc772446d1 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5369 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-07jtag/aice: fix clang static analyzer warningsTomas Vanek
Change-Id: I6c801c2406cd117f2bcf930a5b329c441ab5f1ff Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5368 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-07flash/nor/numicro: use flash infrastructure to align writeTomas Vanek
The aligning code generated a clang static analyzer warning and imposed huge memory leak. This part of code was removed and flash infrastructure to alignment is used instead. Not tested on hw! Change-Id: I7c71da87547e71d595a7e7071ae5adcc1cecc827 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5367 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-07flash/nor/fm4,tms470: fix clang static analyzer warningsTomas Vanek
Change-Id: I18c1501918d40453fea6aeeb6f035e46d41fc524 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5366 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-07src/flash/nor/at91sam3|4l|7: fix clang static analyzer warningsTomas Vanek
Change-Id: I5cd2b2ebb2bd1980bdd1632b5c35bda9718a1089 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5365 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-07flash/nor/stm32f1x: Group and cleanup device listMarc Schink
Group device list based on the device family and add clear device family names. Change-Id: I7a2dab1d1c0c8d141df02656c1964cb2c3fcbcd1 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/5423 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-03drivers: Rename 'libusb1_common' to 'libusb_helper'Marc Schink
The name 'common' does not make sense anymore. While at it, remove some unnecessary #includes. Change-Id: If9798a5cce179438d89428a598d8ca05c8e5f20c Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/5434 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-03drivers: libusb1_common code cleanupMarc Schink
Remove unncessary wrapper functions and 'jtag_' prefixes. Change-Id: I0fd866ff1e1cf7386c4d58a808dfda2c1c0a1518 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/5433 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-03tcl/target: Drop old Renesas Gen2 SoC configsMarek Vasut
Drop old Renesas Gen2 SoC configurations, as they were superseded by the new unified config. Change-Id: I7c2ccbdc13b01a552ce9cafdc1538f226beaa9f2 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5399 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-03remove libusb0_common supportOleksij Rempel
Supporting two libusb versions provides additional development challenges without additional advantage. In most cases we need to patch libusb0_common and libusb1_common without real ability to test libusb0_common. Change-Id: Icbb19c6809b14533fe2acf7a877377b3be4cbd61 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/5432 Tested-by: jenkins
2020-03-02tcl/target: Switch Renesas R-Car Gen2 boards to new configMarek Vasut
Switch Renesas R-Car Gen2 boards which are currently supported from the old ad-hoc SoC configuration to the new unified configuration. Change-Id: I8a67bceb3ae92d840ae4dbac20868c75e83f7d58 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5398 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-02tcl/target: Add unified config for Renesas R-Car Gen2 targetsMarek Vasut
Add configuration for the Renesas R-Car Generation 2 targets. These are SoCs with Cortex A15s and A7s. All cores currently supported by OpenOCD are supported here as well as two new cores, M2N and V2H, for the sake of support completeness. Change-Id: Ib6fe70a91360b4f8bd69822ee28b6dea530cfa0a Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5397 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-02tcl/target: Abort on invalid SoC selection on R-Car Gen3Marek Vasut
Instead of printing error message and continue, abort on invalid SoC selection right away. Change-Id: I9c7a7111b590c6c49a0826562380b881a162a8dc Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/5439 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-03-02flash/stm32h7x: add support of STM32H7Ax/H7Bx devicesTarek BOCHKATI
this new device has the following features: - single core cortex-M7 - 2MB flash - dual bank - page size 8k - write protection grouped by 4 sectors - write block size 128 bits (16 bytes) the bit definition of FLASH_CR is different than STM32H74x, that's why we introduced a helper to compute the FLASH_CR value Change-Id: I4da10cde8dd215b1b0f2645f0efdba9d198038d1 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5441 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-03-02Add support for SAMD21E17D deviceMichael Stoll
Change-Id: Id0a533f8899b20cc87e3a9143383ddf279c86301 Signed-off-by: Michael Stoll <michael.stoll@meadow-robotics.com> Reviewed-on: http://openocd.zylin.com/5458 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-02-29target/arc: fix clang static analyzer warningsEvgeniy Didin
Fixes: * Removed typo in *bitfields initializations. * Removed potentional memory leak allocating reg_data_type_struct_field/reg_data_type_flags_field objects. * Initialize buffers with "0" before usage in buf_set_u32(). * Removed memory leak in jim_arc_add_reg(). Change-Id: Iefde57cd4a48c4f3350c376475df8642607f52ff Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5480 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-02-27Introduce ARCv2 architecture related codeEvgeniy Didin
This patch is an initial bump of ARC-specific code which implements the ARCv2 target(EMSK board) initializing routine and some basic remote connection/load/continue functionality. Changes: 03.12.2019: -Add return value checks. -Using static code analizer next fixes were made: Mem leak in functions: arc_jtag_read_memory,arc_jtag_read_memory, arc_jtag_write_registers, arc_jtag_read_registers, jim_arc_add_reg_type_flags, jim_arc_add_reg_type_struct, arc_build_reg_cache, arc_mem_read. Dead code in "arc_mem_read"; In arc_save_context, arc_restore_context correct arguments in"memset" calls. In "build_bcr_reg_cache", "arc_build_reg_cache" check if list is not empty. 29.12.2019 -Moved code from arc_v2.c to arc.c -Added checks of the result of calloc/malloc calls -Reworked arc_cmd.c: replaced spagetty code with functions -Moved to one style in if statements - to "if(!bla)" -Changed Licence headers 22.01.2020 -Removed unused variables in arc_common -Renamed register operation functions -Introduced arc_deinit_target function -Fixed interrupt handling in halt/resume: * add irq_state field in arc_common * fix irq enable/disable calls ( now STATUS32 register is used) -Switched from buf_set(get)_us32() usage to target_buffer_set(get)_u32() -Made some cleanup 30.01.2020 -Removed redundant arc_register struct, moved target link to arc_reg_desc -Introduced link to BCR reg cache in arc_common for freeing memory. -Now arc_deinit_target frees all arc-related allocated memory. Valgrind shows no memory leaks. -Inroduced arch description in arc.c 01.02.2020 -Remove small memory allocations in arc_init_reg. Instead created reg_value and feature fields in arc_reg_desc. -Add return value for arc_init_reg() func. -Replaced some integer constants(61,62,63) with defines. -Removed redundant conversions in arc_reg_get_field(). -Moved iccm/dccm configuration code from arc_configure() to separate functions. 19.02.2020 -Change sizeof(struct) to sizeof(*ptr) in allocations -Changed if/while(ptr != NULL) to if/while(ptr) -Removed unused variables from struct arc_jtag -Add additional structs to arc_reg_data_type to reduce amount of memory allocations calls and simplifying memory freeing. -Add helper arc_reg_bitfield_t struct which includes reg_data_type_bitfield object and char[] name. Reduces memory allocations calls. -Add limit for reg_type/reg_type_field names(20 symbols). -Add in jim_arc_add_reg_type*() functions additional argnument checks(amount of field/name size). -In jim_arc_add_reg_type*() reduced amount of memory allocations. -Cleanup of jim_arc_add_reg_type*() functions. -For commands update ".usage" fields according docopt. -Cleanup in arc_jtag.c -Renamed functions which require jtag_exeutre_queue() to arc_jtag_enque_*() -Add arc_jtag_enque_register_rw() function, which r/w to jtag ir/dr regs during regiter r/w. 24.02: -Change include guards in arc* files according coding style -Remove _t suffix in struct arc_reg_bitfield_t -Some cleanup Change-Id: I6ab0e82b12e6ddb683c9d13dfb7dd6f49a30cb9f Signed-off-by: Evgeniy Didin <didin@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5332 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-02-24coding style: doc: remove empty lines at end of text filesAntonio Borneo
Empty lines at end of text files are useless. Remove them. Change-Id: I30e4d3d03c4ce846aa7bcefa7366f88732275557 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5170 Tested-by: jenkins
2020-02-24coding style: testing: remove empty lines at end of text filesAntonio Borneo
Empty lines at end of text files are useless. Remove them. Change-Id: Id05a7bd944edccaa03ed9eb48599b2e262664cf0 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5169 Tested-by: jenkins
2020-02-24coding style: tools: remove empty lines at end of text filesAntonio Borneo
Empty lines at end of text files are useless. Remove them. Change-Id: Iea4c8425e137d6252fb2e5b62e0b124c73a01cb6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5168 Tested-by: jenkins
2020-02-24coding style: add newline at end of text filesAntonio Borneo
Some text file is missing newline at EOF. Add it. Change-Id: Ieebc790096f40961283c644642e56fde975e957f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5167 Tested-by: jenkins
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-11-23 10:07:56 +0000