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2020-02-15coding style: remove unnecessary parenthesesAntonio Borneo
Identified by checkpatch script from Linux kernel v5.1 using the command find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types UNNECESSARY_PARENTHESES -f {} \; then fixed manually. Change-Id: Ia2d9a0953d9b89fc87dc1195aa05c7f63c068c48 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5196 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-20cortex_m: set C_DEBUGEN in soft_reset_haltAntonio Borneo
The command "soft_reset_halt" is deprecated since mid 2013 with the commit 146dfe32956d ("cortex_m: deprecate soft_reset_halt"). Nevertheless it is still extremely useful with multicore chips where it allows to reset only one of the cores, option not available through asserting the chip-wide srst. Without a better replacement of the command, it's worth fixing it. Accordingly to ARM DDI 0403E.d, chapter C1.4.1 "Entering Debug state on leaving reset state", to halt the core at reset both bits DHCSR.C_DEBUGEN and DEMCR.VC_CORERESET must be set. Current code only sets the latter bit, relying on having C_DEBUGEN already set through other commands, e.g. "halt". This prevents the command "soft_reset_halt" to work if issued as very first command. Set the bit C_DEBUGEN in command "soft_reset_halt". Change-Id: I66bfd6a0da1fca5049dea037b4d258cf6f842966 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4987 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-19target/cortex_m: Add support for AHB5-APMarc Schink
The AHB5-AP is implemented in Cortex-M23/33 based devices. Change-Id: I505954a2e2c6462ce0aa96eba1d55b016c5028b9 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/5232 Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins
2019-06-19target/arm_adiv5: Add type for AHB5-APMarc Schink
This access port type comes with the AMBA 5 protocol specification, see 'C1.3 AP' in ARM IHI 0031D. Change-Id: I3c4f0a69230daaf4f5f979de6213fe3c025a089a Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/5231 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Muhammad Omair Javaid <omair.javaid@linaro.org>
2019-06-19Support for debugging on ARMv8-M CPUsOmair Javaid
This patch adds ARMv8-M CPUs detection logic in ARMv7m target specific code. Also adds a slightly different watchpoint manipulation logic for ARMv8-M. This is based on ARMv8-M architecture reference manual. Tested on ARM Musca A board. Change-Id: I0652560954ef02c378a7067fab586edf39d3e9cc Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4997 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-06-06target/cortex_m: remove dependency from jtag queueAntonio Borneo
Since the first commit 09883194f867 that introduced cortex_m, the code has a delay of 50ms after srst has been asserted. The specific delay is implemented through the JTAG_SLEEP command sent in the jtag queue. To remove the dependency from the jtag queue, replace the delay with a transport independent function. In case of jtag transport, this change keeps the same behaviour only if the jtag queue has been flushed before the delay. This does not happen if the call to dap_dp_init(), few lines above, fails while calling a dap_queue_dp_{read,write}(); in this case the jtag queue will be flushed later, after the delay, while in the original code the delay would follow the flushing of the commands already queued. Anyway, this different behavior would only happen in case of DAP already not responsive so anticipating the delay in such error condition is not supposed to add further problems. Change-Id: If15978246764e4266b10e707d86c03e5ed907de7 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4912 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-05-23cortex_m: set the debug reason to DBGRQ when NVIC_DFSR indicates EXTERNALTarek BOCHKATI
By definition the EXTERNAL bit in Debug Fault Status Register indicates that an external debug request (EDBGRQ) signal was asserted. Usage example: this could be done by CTI in multicore devices in order to halt all the cores together. Change-Id: I7830455ce5da6702b7d08c8fa7bfe80e4d8a5055 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5157 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-05-14helper/command: change prototype of command_print/command_print_samelineAntonio Borneo
To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-05-14target/cortex_m: change prototype of cortex_m_verify_pointer()Paul Fertser
To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should be ready to switch to CMD as first parameter. Change prototype of cortex_m_verify_pointer() to pass CMD instead of CMD_CTX. This change was part of http://openocd.zylin.com/1815 from Paul Fertser and has been extracted and rebased to simplify the review. Change-Id: Icf6d1e5f8b4a3ce115c4253e49769df19a5211ae Signed-off-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5061 Tested-by: jenkins
2019-04-10target/cortex_m: Implement maskisr steponly optionChristopher Head
`maskisr steponly` disables interrupts during single-stepping but enables them during normal execution. This can be used as a partial workaround for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with FPU (AT611) Software Developer Errata Notice" from ARM for further details. Change-Id: I797a14e4d43f6dcb3706528ee4ab452846ebf133 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4673 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2019-04-03target/cortex_m: remove target halted check when removing a breakpointTomas Vanek
Remove the target halted check from cortex_m_remove_breakpoint() as there is no such check in cortex_m_set_breakpoint() and bp can be safely removed from the running target. While on it return the error code from cortex_m_unset_breakpoint() to higher level. Change-Id: I2b358c3661feed84297913e9f589bdf1e4de7e64 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4887 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Jānis Skujenieks <janis.skujenieks@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com>
2019-04-01target/cortex_m: remove fp_code_available countingTomas Vanek
fp_code_available looses sync with the real number of free comparators as soon as cortex_m_set_breakpoint() returns an error. Remove the counter and always go through the fp_comparator_list to find a free one. Change-Id: I9f6e06c36d8a57ad11df5155e8a1a3aff6d833a5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4870 Tested-by: jenkins Reviewed-by: Jānis Skujenieks <janis.skujenieks@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-04-01target/cortex_m: simplify cortex_m_unset_breakpoint()Tomas Vanek
Cortex-M uses only 2 byte breakpoint instruction. cortex_m_unset_breakpoint() does not need to check breakpoint->length, use the length as the size argument in target_write_memory() Change-Id: I20bb869f6abce2fc61f0469e34a638bc4dc6f7ce Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4889 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Jānis Skujenieks <janis.skujenieks@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com>
2019-03-06target/cortex_m: Use 'bool' instead of 'int'Marc Schink
Change-Id: I273d24997e2c844015e144a15981f8f0af522261 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4950 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-01Use enum for target_register_timer_callback()Marc Schink
Change-Id: I268e8c5d783914aa97cbde301448b2c5bc3cb9e6 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4921 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-02-07target/cortex_m: fix clang static analyzer warningTomas Vanek
Fix "Potential leak of memory pointed to by 'cortex_m'" and test for NULL return from calloc in cortex_m_target_create() Change-Id: I4d2bb5bccc57f0ed60696f3d588297a858b8ea60 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4881 Tested-by: jenkins Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-02-04cortex_m: fix stepping on FPB rev 1Tomas Vanek
Stepping in the maskisr auto mode sets breakpoint to step over interrupt service tasks. If the device has FPB rev 1, setting hard breakpoint is impossible on address over 0x1fffffff. Use soft type breakpoint for adresses over 0x1fffffff if FPB is rev 1. This may eventually fail if the code memory is not writeable, but there is nothing to do in such case. Change-Id: Ibdeeb506903a35d550b64f82c24c37a668de62b3 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4857 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-01-27target/cortex_m: inform if an external reset occursTomas Vanek
Change-Id: I873e73012c44aac7af3b21b633bd096d8e299d07 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4840 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-01-16cortex_m: fix bug in poll() machine state (external resume awareness)Tarek BOCHKATI
This patch covers the fact that cortex_m could be resumed externally by Cross Trigger Interface or by direct write to DHSCR ... To reproduce: - halt the target - then run the core through DHCSR (mww 0xe000edf0 0xa05f0001) => this resumes the core, but target state in OpenOCD remains HALTED. Change-Id: Ifa1ae18645bfeb863acc78a039bbf04873fd78fe Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/4817 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-01-08target/arm: add support for multi-architecture gdbAntonio Borneo
GDB can be built for multi-architecture through the command ./configure --enable-targets=all && make Such multi-architecture GDB requires the target's architecture to be selected either manually by the user through the GDB command "set architecture" or automatically by the target description sent by the remote target (i.e. OpenOCD). Commit e65acd889c61a424c7bd72fdee5d6a3aee1d8504 ("gdb_server: add support for architecture element") already provides the required infrastructure to support multi-architecture gdb. arm-none-eabi-gdb 8.2 uses "arm" as default architecture, but also supports the following values: "arm_any", "armv2", "armv2a", "armv3", "armv3m", "armv4", "armv4t", "armv5", "armv5t", "armv5te", "armv5tej", "armv6", "armv6k", "armv6kz", "armv6-m", "armv6s-m", "armv6t2", "armv7", "armv7e-m", "armv8-a", "armv8-m.base", "armv8-m.main", "armv8-r", "ep9312", "iwmmxt", "iwmmxt2", "xscale". These values can be displayed on arm gdb prompt by typing "set architecture " followed by a TAB for autocompletion. Set the gdb architecture value for all arm targets to "arm". Change-Id: I176cb89878606e1febd546ce26543b3e7849500a Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4754 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2018-12-19target/cortex_m: fix cortex_m reset_config help and check for syntax errorTomas Vanek
Remove option 'srst' which is not recognized from on-line help and texi. Check parameter and return syntax error if wrong option is entered. Change-Id: I87daa423a9f53193a0b015080594820b933628f5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4795 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2018-12-19target/cortex_m: do not use VECTRESET on Cortex-M0, M0+ and M1Tomas Vanek
Cortex-M0, M0+ and M1 do not support VECTRESET bit in AIRCR. Without this change the 'reset' command silently fails if VECTRESET is requested. Detect these cores, show warning if VECTRESET is about to use and use SYSRESETREQ instead. Change-Id: Ief174373e3ef0e6b287c57911c0aca4dfa8209f2 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4794 Tested-by: jenkins Reviewed-by: Jean-Christian de Rivaz <jcamdr70@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2018-09-25target/cortex_m: fix typoChristopher Head
The subunit of the debug unit is called the Flash Patch and Breakpoint unit, abbreviated (by ARM no less) as FPB, not FBP. Change-Id: Ia2f08470da705f0f1518feeca878f0f500507308 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4675 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2018-09-07adi_v5: enforce check on AP number valueAntonio Borneo
The AP number value is restricted in 8 bits unsigned by ADI-v5 specification. Nevertheless, an "invalid" value is used by target cortex-m to force an automatic detection of the AP. Replace magic numbers by using new macros for AP max number and for the value of AP invalid. Check the value passed through -ap-num flag during configuration. Change-Id: Ic19a367db0ab11c0ebd070750eca0647d25279a5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4668 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-08-14target/cortex_m: restore C_MASKINTS after resetChristopher Head
The cortex_m maskisr user-facing setting is not changed across a target reset. However, the in-core C_MASKINTS bit was always cleared as part of reset processing, meaning that a cortex_m maskisr on setting would not be respected after a reset. Set C_MASKINTS based on the user-facing setting value rather than always clearing it after reset. Change-Id: I5aa5b9dfde04a0fb9c6816fa55b5ef1faf39f8de Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4605 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-08-01target/cortex_m: fix incorrect commentChristopher Head
The code sets C_MASKINTS if that bit is not already set (correctly). Fix the comment to agree. Change-Id: If4543e2660a9fa2cdabb2d2698427a6c8d9a274c Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4620 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-07-25target/cortex_m: make a variable localChristopher Head
The vec_ids variable is not referenced anywhere other than the vector catch command handler. Make it local to that function. Change-Id: Ie5865e8f78698c19a09f0b9d58269ced1c9db440 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4606 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-07-19target/armv7m_trace: Use prefix for enumsMarc Schink
Change-Id: I3f199e6053146a1094d96b98ea174b41bb021599 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3905 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-07-03target/cortex_m: return error if breakpoint address is out of rangeAntonio Borneo
If the "Flash Patch and Breakpoint" unit is rev.1 then it can only accept breakpoint addresses below 0x1FFFFFFF. Detailed info in "ARM v7-M Architecture Reference Manual", DDI0403E at chapter "C1.11 Flash Patch and Breakpoint unit". Print a message and return error if the address of hardware breakpoint cannot be handled by the breakpoint unit. Change-Id: I95c92b1f058f0dfc568bf03015f99e439b27c59b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4535 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Christopher Head <chead@zaber.com>
2018-06-05target/cortex_m: constify some variablesChristopher Head
Change-Id: I1f3fddd89597333fc1bb9535c0cd76ca3e008324 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4503 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-12target/cortex_m: allow setting the type of a breakpointTomas Vanek
Cortex-M target used 'auto_bp_type' mode. The requested type of breakpoint was ignored and hard (FPB) breakpoints were set in 'code memory area' 0x00000000-0x1fffffff, soft breakpoints were set above 0x20000000. The code memory area of Cortex-M does not mean the memory is flash and vice versa. External flash (parallel or QSPI) is usually mapped above code memory area. Cortex-M7 ITCM RAM is mapped at 0. Kinetis has a RAM block under 0x20000000 boundary. Remove 'auto_bp_type' mode, set breakpoints to requested type. Change 'cortex_m maskisr auto' handling to use a hard temporary breakpoint everywhere: it can also workaround not working soft breakpoints on Cortex-M7 with ICache enabled. Change-Id: I7a9f9464c5e10bfd7f17cba1037ed07a064fa2e8 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4429 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-04target/cortex_m: avoid dwt comparator overflowCody P Schafer
Avoid ever overflowing the DWT_COMPARATOR array by allocating space for 16 comparators (the field is masked by 0xf). On a stm32f767zi chip (on a nucleo-767zi board) I've been seeing crashes with address sanitizer enabled due to its (apparent) 10 present comparators. This appears to be due to https://sourceforge.net/p/openocd/tickets/178/. In non-address sanitizer builds, this would likely cause some random memory to be written to in some cases. (see above bug for observations). Change-Id: I2b7d599eb326236dbc93f74b350c442c9a502c4b Signed-off-by: Cody P Schafer <openocd@codyps.com> Reviewed-on: http://openocd.zylin.com/4458 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-03-30target: restructure dap supportMatthias Welwarsky
- add 'dap create' command to create dap instances - move all dap subcmmand into the dap instance commands - keep 'dap info' for convenience - change all armv7 and armv8 targets to take a dap instance instead of a jtag chain position - restructure tap/dap/target relations, jtag tap no longer references the dap, daps are now independently created and initialized. - clean up swd connect - re-initialize DAP also on JTAG errors (e.g. after reset, power cycle) - update documentation - update target files Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4468 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-25Use timeval helpersChristopher Head
Some of these changes actually fix broken comparisons which could occasionally fail. Others just clean up the code and make it more clear. Change-Id: I6c398bdc45fa0d2716f48a74822457d1351f81a5 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4380 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-13hla_target: allow non-intrusive profiling on cortex-mKarl Palsson
Leverages the existing work that added profiling via DWT_PCSR. hla_target doesn't have direct access to the mem_ap for doing a bulk repeated read, but simply reading the DWT_PCSR register repeatedly is still ~2 order of magnitude faster than halt/resume. Change-Id: Ibe451aa95143694398370fdad6939cfb6191d56f Signed-off-by: Karl Palsson <karlp@tweak.net.au> Reviewed-on: http://openocd.zylin.com/4220 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-01-13cortex_m: add profiling functionSimon Schubert
Use DWT_PCSR if present (reads nonzero); otherwise do halt-and-sample pc. Signed-off-by: Simon Schubert <2@0x2c.org> Change-Id: Id2dc4665e5008cc497a2e6e6493522d038d5af42 Reviewed-on: http://openocd.zylin.com/4211 Tested-by: jenkins Reviewed-by: Karl Palsson <karlp@tweak.net.au> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-10-27Cortex-M: Delete an unnecessary local variableChristopher Head
The dhcsr_save variable was used to save the value of cortex_m->dcb_dhcsr so it could be restored later. However, all writes in between the save and the restore use mem_ap_write_atomic_u32, not cortex_m_write_debug_halt_mask, which means cortex_m->dcb_dhcsr isn’t changed anyway. Delete the unnecessary local. Change-Id: I064a3134e21398e1ecfc9f1fa7efd7b020b52341 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4240 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-10-27Cortex-M: fix stale DHCSR cache valuesChristopher Head
In cortex_m_assert_reset, in two locations, DHCSR is written directly using mem_ap_write_u32. This means that the cached version, target_to_cm(target)->dcb_dhcsr, is not updated when these writes are performed, so subsequent writes to DHCSR that use cortex_m_write_debug_halt_mask will change those bits back to their old values which, unless modified in that particular invocation, come from the cache. This causes an actual, observable bug on an STM32F7 in which running “reset run” immediately after “program” can in some cases result in execution proceeding with C_MASKINTS set (it is cleared on line 1021 but is then set immediately afterward in cortex_m_clear_halt), causing failure of the application. Replace these mem_ap_write_u32 calls with cortex_m_write_debug_halt_mask calls to do the same jobs. Change-Id: Id35ca7f6057c2df2ba9cd67c53a73b50816d0b71 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4239 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-02-10target: Add 64-bit target address supportDongxue Zhang
Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2016-12-08cortex_m: allow setting debug ap during createMatthias Welwarsky
This patch adds a Cortex-M private configuration option that allows setting the acess point during target creation. This circumvents situations in hybrid systems when the correct access point can not be automatically detected. Change-Id: If313a5250e6e66509bb9080f3498feab7781dced Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3639 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-12-08semihosting: support fileio operationSteven Stallion
This patch adds support for bridging semihosting to GDB's File-I/O remote protocol extension. For the most part operations match up 1:1, however some require a working area to complete successfully, namely operations that devolve to read, stat, and gettimeofday. A new command was added to enable support for fileio named `arm semihosting_fileio`, which ensures that the default behavior remains intact for those that prefer it. Finally, redundant logging was removed from the target_arch_state function; this permits ARM targets to quiesce log output when polling for a fileio reply. This prevents filling the logs with halt/resume messages when using semihosting fileio. Change-Id: Ifbb864fc2373336a501cc0332675b887b552e1ee Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/3566 Tested-by: jenkins Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-11-04cortex_a/r/m: fix handling of un-examined coresMatthias Welwarsky
On multi-core systems, with some cores in power-down state, examination will fail for these cores. Make sure assert- and deassert_reset functions don't crash due to uninitialized variables. Change-Id: I472f8d19af2cd3c770c05f3e57a31b35a863b687 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3552 Tested-by: jenkins Reviewed-by: Jiri Kastner <cz172638@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-10-04cortex_m: fix autoincrement range of Cortex-M7Tomas Vanek
Cortex-M7 has autoincrement range only 1024 bytes, surprisingly smaller than M3, M4. Change-Id: I35ff1f0e093aac4af79f98eb3b8058d4295942d1 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3737 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2016-08-10Cortex-M7 handling.Andreas Bolsch
- FPU detection and FPU register support added for Cortex-M7. There is no apparent difference between FPv4 and FPv5_SP but ... - Autoincrement range for MEM-AP added for Cortex-M7 This patch together with #3526 replaces #3123 except for stm32f7x.cfg. Change-Id: I5ed5392e3835674160563ff37d67622a7bf2c877 Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/3531 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-24Remove FSF address from GPL noticesMarc Schink
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-20Fix spelling of ARM CortexAndreas Färber
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn or CortexXn. Further it's Cortex-M0+, not M0plus. Cf. http://www.arm.com/products/processors/index.php Consistently write it the official way, so that it stops propagating. Originally spotted in the documentation, it mainly affects code comments but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output. Found via: git grep -i "Cortex " git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu" git grep -i "CortexM" Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3483 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-06Cortex-M7: Give user a hint about single stepping problem up to r0p1.Uwe Bonnes
http://www.keil.com/support/docs/3778.htm Change-Id: I452f76726f3bb269fa14cc785f329bfba5189489 Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/3467 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2016-05-05target: improve robustness of reset commandTomas Vanek
Before this change jim_target_reset() checked examined state of a target and failed without calling .assert_reset in particular target layer (and without comprehensible warning to user). Cortex-M target (which refuses access to DP under active SRST): If connection is lost then reset process fails before asserting SRST and connection with MCU is not restored. This resulted in: 1) A lot of Cortex-M MCUs required use of reset button or cycling power after firmware blocked SWD access somehow (sleep, misconfigured clock etc). If firmware blocks SWD access early during initialization, a MCU could become completely inaccessible by SWD. 2) If OpenOCD is (re)started and a MCU is in a broken state unresponsive to SWD, reset command does not work even if it could help to restore communication. Hopefully this scenario is not possible under full JTAG. jim_target_reset() in target.c now does not check examined state and delegates this task to a particular target. All targets have been checked and xx_assert_reset() (or xx_deassert_reset()) procedures were changed to check examined state if needed. Targets except arm11, cortex_a and cortex_m just fail if target is not examined although it may be possible to use at least hw reset. Left as TODO for developers familiar with these targets. cortex_m_assert_reset(): memory access errors are stored instead of immediate returning them to a higher level. Errors from less important reads/writes are ignored. Requested reset always leads to a configured action. arm11_assert_reset() just asserts hw reset in case of not examined target. cortex_a_assert_reset() works as usual in case of not examined target. Change-Id: I84fa869f4f58e2fa83b6ea75de84440d9dc3d929 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2606 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-12-30target: cortex_m: fix segfault with HLAPaul Fertser
The HLA target shares an examine handler with cortex_m but since it lacks direct access to DAP, some operations need to be omitted. Change-Id: Ifdd9d3da4a3a3c2e1c9721284b21d041b3ccaa7a Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3183 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29cortex: Set default memaccess_tck only during examineAndreas Fritiofson
It's currently set during target creation but the AP that will be used for the target is not even known. Change-Id: I4502e7eb1fa8d90f746445b8cf8a4c21cb7d519e Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3155 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
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