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AgeCommit message (Expand)Author
2011-08-11Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.Owen Anderson
2011-08-11Making SEL decodings auto-generate-able.Owen Anderson
2011-08-11Tidy up comment.Jim Grosbach
2011-08-11Fix decoding support for STREXD and LDREXD.Owen Anderson
2011-08-11ARM STRH assembly parsing and encoding.Jim Grosbach
2011-08-11Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.Owen Anderson
2011-08-11Tidy up. Remove unused template parameter.Jim Grosbach
2011-08-11Improve operand validation for Thumb2 addressing modes.Owen Anderson
2011-08-11ARM STRD assembly parsing and encoding.Jim Grosbach
2011-08-11Continue to tighten decoding by performing more operand validation.Owen Anderson
2011-08-11Tidy up.Jim Grosbach
2011-08-11ARM STRBT assembly parsing and encoding.Jim Grosbach
2011-08-11ARM STR(immediate) assembly parsing and encoding.Jim Grosbach
2011-08-11Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.Owen Anderson
2011-08-11Tighten operand decoding of addrmode2 instruction. The offset register canno...Owen Anderson
2011-08-11Correct immediate range for shifter operands. Patch by James Molloy, with ad...Owen Anderson
2011-08-11Improve error checking in the new ARM disassembler. Patch by James Molloy.Owen Anderson
2011-08-11ARM push of a single register encodes as pre-indexed STR.Jim Grosbach
2011-08-11ARM pop of a single register encodes as post-indexed LDR.Jim Grosbach
2011-08-10ARM LDRT assembly parsing and encoding.Jim Grosbach
2011-08-10Tidy up. 80 columns.Jim Grosbach
2011-08-10ARM LDRH(immediate) assembly parsing and encoding support.Jim Grosbach
2011-08-10ARM LDRD(register) assembly parsing and encoding.Jim Grosbach
2011-08-10Fix typo. Not quite sure how that slipped in there.Jim Grosbach
2011-08-10ARM LDRD(immediate) assembly parsing and encoding support.Jim Grosbach
2011-08-10Add initial support for decoding NEON instructions in Thumb2 mode.Owen Anderson
2011-08-10Tabs --> spaces.Owen Anderson
2011-08-10Cleanups based on Nick Lewycky's feedback.Owen Anderson
2011-08-10Rewrite some ARM InstrInfo functions to be most accepting of arbitrary regist...Owen Anderson
2011-08-10Add support for the R and Q constraints.Rafael Espindola
2011-08-10Push GPRnopc through a large number of instruction definitions to tighten ope...Owen Anderson
2011-08-09Promote VMOVS to VMOVD when possible.Jakob Stoklund Olesen
2011-08-09Tighten operand checking of register-shifted-register operands.Owen Anderson
2011-08-09Tighten operand checking on memory barrier instructions.Owen Anderson
2011-08-09Tighten operand checking on CPS instructions.Owen Anderson
2011-08-09Create a new register class for the set of all GPRs except the PC. Use it to...Owen Anderson
2011-08-09ARM Disassembler: sign extend branch immediates.Benjamin Kramer
2011-08-09Silence an false-positive warning.Owen Anderson
2011-08-09Don't generate the old-style disassembler in CMake builds either.Owen Anderson
2011-08-09The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction...Benjamin Kramer
2011-08-09Don't continue generating the old-style decoder file.Owen Anderson
2011-08-09ARM fix typo in pre-indexed store lowering.Jim Grosbach
2011-08-09Attempt to fix CMake build.Owen Anderson
2011-08-09Tighten Thumb1 branch predicate decoding.Owen Anderson
2011-08-09Replace the existing ARM disassembler with a new one based on the FixedLenDec...Owen Anderson
2011-08-09Emitting ARM build attributes and values as ULEB, rather than char.Renato Golin
2011-08-08ARM parsing and encoding for LDRBT instruction.Jim Grosbach
2011-08-08Thumb1 BL instructions encoding 22 bits of displacement, not 21.Owen Anderson
2011-08-08Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.Jakob Stoklund Olesen
2011-08-08ARM load/store label parsing.Jim Grosbach