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2014-03-26optimize x < 0 and generalize it to non-i64 values tooAlon Zakai
2014-03-15Handle conflicting lifetime markers conservatively.Dan Gohman
Avoid infinite looping in AllocaManager::computeInterBlockLiveness, without using new temporary variables. This also makes it clear that the algorithm is conservative in the face of conflicting liveness intrinsics.
2014-03-15Add triple and datalayout strings to testcases.Dan Gohman
This allows them to be run without specifying any command-line options, which is convenient.
2014-03-10update float ffi rulesAlon Zakai
2014-03-09add aliases testAlon Zakai
2014-03-05Disable the ResolveAliases and GlobalCleanup passes.Dan Gohman
Also add a test for handling of global aliases.
2014-03-05Disable the LowerExpectIntrinsic pass.Dan Gohman
2014-03-05Don't emit redirects for llvm.memcpy.p0i8.p0i8.i32 and friends.Dan Gohman
We never reference these intrinsics by name, so we don't need redirects for them.
2014-03-05Don't emit JS declarations for LLVM intrinsics expanded inline.Dan Gohman
2014-03-05Tidy up the output for memset and memcpy, and add a test.Dan Gohman
2014-03-05Don't run a pass to strip dead prototypes; just ignore them.Dan Gohman
Also, fix the code for supressing declarations for no-op intrinsics.
2014-03-05Clean up the handling of inline asm.Dan Gohman
Make inline asm a report_fatal_error instead of an assertion failure so that it's a little friendlier, and add a test to make sure llc -march=js rejects inline asm. Also disable the PNaCl inline asm("":::"memory") lowering pass. If people are using this, it's best that we diagnose it as it likely isn't portable. There are usually better alternatives.
2014-03-05Teach phi translation to also look through bitcasts.Dan Gohman
This fixes a regression introduced in d95cd364f0c049d6c1b8d78746d44c00ed2f69f2; when regular expression translation looks through bitcasts but phi translation doesn't, phi translation may fail to properly detect dependencies.
2014-03-04Introduce AllocaManager, a class for managing allocas.Dan Gohman
The AllocaManager performs stack layout for alloca objects. It is capable of analyzing alloca liveness and sharing space between multiple allocas.
2014-03-04Update to the new datalayout string.Dan Gohman
2014-02-28Update tests for recent changes which result in more parens being used in ↵Dan Gohman
some places.
2014-02-28Move ExpandI64 into lib/Target/JSBackend.Dan Gohman
2014-02-28Implement llvm.flt.rounds and disable the createRewriteLLVMIntrinsicsPass pass.Dan Gohman
2014-02-12Create a test directory for basic JS CodegenDan Gohman
2013-10-11Cherry-pick LLVM 187787 to prevent tail calls on x86-32 when not appropriate.Jan Voung
See: http://llvm.org/viewvc/llvm-project?view=revision&revision=187787 The newer version of newlib tickles this x86-32 bug when building the exception handling tests, which don't strip the "tail" attribute. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3702 Waiting on trybots, but it seems to have fixed the minimal reproducer I have: http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_64/builds/922 http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-linux-pnacl-x86_32/builds/870 http://chromegw.corp.google.com/i/tryserver.nacl/builders/nacl-toolchain-mac-pnacl-x86_32/builds/875 R=jfb@chromium.org Review URL: https://codereview.chromium.org/26538008
2013-10-11Apply upstream: [mips] Fix a bug in MipsLongBranch::replaceBranchPetar Jovanovic
Cherry-pick r191978 from upstream. Original commit message: Author: Akira Hatanaka <ahatanaka@mips.com> Date: Fri Oct 4 20:51:40 2013 +0000 [mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing instructions in delay slots along with the original branch instructions This has to be cherrypicked, as it is a bug in backend. It was exposed in a long function inside of llc, which caused llc.nexe to work incorrectly. TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= bug in MIPS backend Review URL: https://codereview.chromium.org/26933005
2013-10-11Apply upstream: [mips] Implement llvm.trap intrinsic.Petar Jovanovic
Cherry-pick r187244 from upstream. Original commit message: Author: Akira Hatanaka <ahatanaka@mips.com> Date: Fri Jul 26 20:58:55 2013 +0000 [mips] Implement llvm.trap intrinsic. Patch by Sasa Stankovic. This has to be cherrypicked, as two tests fail due to missing llvm.trap intrinsic. The tests are: - run_sysbrk_test - run_abi_types_test TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= sysbrk and abi_types tests fail for MIPS Review URL: https://codereview.chromium.org/26953003
2013-10-11Apply upstream: Add missing ATOMIC_CMP_SWAP case.Petar Jovanovic
Cherry-pick r185186 from upstream. Original commit message: Author: Lang Hames <lhames@gmail.com> Date: Fri Jun 28 18:36:42 2013 +0000 Add missing case to switch statement - DAGTypeLegalizer::ExpandIntegerResult should expand ATOMIC_CMP_SWAP nodes the same way that it does for ATOMIC_SWAP. Since ATOMIC_LOADs on some targets (e.g. older ARM variants) get legalized to ATOMIC_CMP_SWAPs, the missing case had been causing i64 atomic loads to crash during isel. This has to be cherry-picked, as we have experienced the same bug described in the original message. Missing case caused MIPS 64 atomics to crash. TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= crash for MIPS atomics Review URL: https://codereview.chromium.org/26958002
2013-10-11Apply upstream: [mips] Trap on integer division by zero.Petar Jovanovic
Cherry-pick r182306 from upstream. Original commit message: Author: Akira Hatanaka <ahatanaka@mips.com> Date: Mon May 20 18:07:43 2013 +0000 [mips] Trap on integer division by zero. By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. TBR= mseaborn@chromium.org, dschuff@chromium.org BUG= missing trap for MIPS Review URL: https://codereview.chromium.org/26846007
2013-09-16Work around a gcc 4.6.3 / 4.7 bug.Jim Stichnoth
GCC bug http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58416 causes the bf64-1.c test to fail in the GCC torture test suite. This provides an upstreamable workaround. Inspection of the LLVM code base showed no other instances of the pattern that triggers the gcc bug. This can also be upstreamed as soon as I can get a working x86-32 upstream build working to verify/test against. In the meantime, we can make one pnacl-fyi bot go green again. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3685 R=jfb@chromium.org, jfb@google.com Review URL: https://codereview.chromium.org/23437037
2013-07-25Clean some PNaCl-specific tests.Jim Stichnoth
BUG= https://code.google.com/p/nativeclient/issues/detail?id=3588 R=jvoung@chromium.org Review URL: https://codereview.chromium.org/19606003
2013-07-24Hide the x86-64 sandbox base address.Jim Stichnoth
Prevent sandbox addresses from being written to the stack. This covers the following cases: 1. Function calls manually push a masked return address and jump to the target, rather than using the call instruction. 2. When the function prolog chooses to use a frame pointer (rbp), it saves a masked version of the old rbp. 3. Indirect branches (jumps, calls, and returns) uniformly use r11 to construct the 64-bit target address. 4. Register r11 is marked as reserved (similar to r15) so that the register allocator won't inadvertently spill a code address to the stack. These transformations can be disabled for performance testing with the flag "-sfi-hide-sandbox-base=false". BUG= https://code.google.com/p/nativeclient/issues/detail?id=1235 R=eliben@chromium.org, mseaborn@chromium.org Review URL: https://codereview.chromium.org/19505003
2013-07-23Cherrypick test from r186226 - Fix ARM paired GPR COPY loweringJF Bastien
BUG= test the fix that was already cherrypicked TEST= self R=eliben@chromium.org Review URL: https://codereview.chromium.org/19704008
2013-07-22Cherrypick upstream ARM FastISel ext patchesJF Bastien
Specifically: r186489 - Fix ARMFastISel::ARMEmitIntExt shift emission r183794 - ARM FastISel fix sext/zext fold r183601 - Fix unused variable warning from my previous patch r183551 - ARM FastISel integer sext/zext improvements These should fix some failures that I had run into back then, as well as make ARM FastISel faster because it doesn't go to SelectionDAG. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3501 R=jvoung@chromium.org TEST= make check-all Review URL: https://codereview.chromium.org/19992002
2013-07-18Merge remote-tracking branch 'origin/master'Eli Bendersky
2013-07-17Disallow a global address in the x86-64 displacement field.Jim Stichnoth
This applies only to %r15 sandboxed memory references. The problem is that if the index register is negative, the sandboxing operation will cause the index to become a large positive 32-bit value, which combined with the displacement, will overflow and try to reference memory outside the sandbox. This situation may legitimately occur if the compiler happens to construct a (constant) interior pointer to the middle of the global struct/array, and then dereferences it with a variable offset. After this fix, pnacl/scripts/testsuite_known_failures_pnacl.txt can be updated to remove the "aha x86-64" known failure. BUG= https://code.google.com/p/nativeclient/issues/detail?id=3517 R=eliben@chromium.org Review URL: https://codereview.chromium.org/17987002
2013-07-15Merge commit '7dfcb84fc16b3bf6b2379713b53090757f0a45f9'Eli Bendersky
Conflicts: docs/LangRef.rst include/llvm/CodeGen/CallingConvLower.h include/llvm/IRReader/IRReader.h include/llvm/Target/TargetMachine.h lib/CodeGen/CallingConvLower.cpp lib/IRReader/IRReader.cpp lib/IRReader/LLVMBuild.txt lib/IRReader/Makefile lib/LLVMBuild.txt lib/Makefile lib/Support/MemoryBuffer.cpp lib/Support/Unix/PathV2.inc lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMTargetMachine.cpp lib/Target/Mips/CMakeLists.txt lib/Target/Mips/MipsDelaySlotFiller.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrControl.td lib/Target/X86/X86InstrFormats.td lib/Transforms/IPO/ExtractGV.cpp lib/Transforms/InstCombine/InstCombineCompares.cpp lib/Transforms/Utils/SimplifyLibCalls.cpp test/CodeGen/X86/fast-isel-divrem.ll test/MC/ARM/data-in-code.ll tools/Makefile tools/llvm-extract/llvm-extract.cpp tools/llvm-link/CMakeLists.txt tools/opt/CMakeLists.txt tools/opt/LLVMBuild.txt tools/opt/Makefile tools/opt/opt.cpp
2013-07-08R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst regTom Stellard
Patch by: Vincent Lejeune https://bugs.freedesktop.org/show_bug.cgi?id=64877 NOTE: This is a candidate for the 3.3 branch. Merged from r182600 Author: Tom Stellard <thomas.stellard@amd.com> Date: Thu May 23 18:26:42 2013 +0000 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@185868 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25Revert "Apply upstream r183551, r183601, r183624 and r183794"Jan Voung
Revert this until we fix i1 sext. Currently, it uses LSL and ASR, which are pseudo-instructions and get dropped on the floor when generating .o files. We'll fix that, but for now revert to green the bots. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3501 R=jfb@chromium.org Review URL: https://codereview.chromium.org/17715002
2013-06-24Merge r179774: Allow misaligned stores in x86 fast-isel.Mark Seaborn
This change will fix the regression in -O0 translation time caused by putting "align 1" on integer loads and stores, which was causing FastISel to fall back to SelectionDAG more often. > In X86FastISel::X86SelectStore(), improperly aligned stores are > rejected and handled by the DAG-based ISel. However, > X86FastISel::X86SelectLoad() makes no such requirement. There > doesn't appear to be an x86 architectural correctness issue with > allowing potentially unaligned store instructions. This patch > removes this restriction. > > Patch by Jim Stichnot. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3445 TEST=PNaCl toolchain trybots Review URL: https://codereview.chromium.org/17575003
2013-06-13Fix PrologEpilogInserter to save and restore all callee saved registersDerek Schuff
if the function calls _builtin_unwind_init() Also fix the list of callee-saved registers returned by X86RegisterInfo::getCalleeSavedRegisters BUG= https://code.google.com/p/nativeclient/issues/detail?id=3486 R=mseaborn@chromium.org Review URL: https://codereview.chromium.org/16987002
2013-06-11Apply upstream r183551, r183601, r183624 and r183794JF Bastien
Rename countTrailingZeros to the older CountTrailingZeros_32, mark as localmod. These patches fix correctness issues with ARM FastISel, and should make it faster while generating better code. BUG= none TEST= self R=jvoung@chromium.org Review URL: https://codereview.chromium.org/16712002
2013-05-31Apply LLVM upstream: r182877 - Enable FastISel on ARM for Linux and NaClJF Bastien
This also pulls in a TargetMachine.h change from r176986 and changes NaCl's intrinsics-bitmanip.ll test to account for register spills at O0. FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. R=dschuff@chromium.org, jvoung@chromium.org BUG= https://code.google.com/p/nativeclient/issues/detail?id=3120 Review URL: https://codereview.chromium.org/15671004
2013-05-29Apply LLVM upstream: r181801 - Fix ARM FastISel tests, as a first step to ↵JF Bastien
enabling ARM FastISel ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. R=dschuff@chromium.org Review URL: https://codereview.chromium.org/15737029
2013-05-29Apply LLVM upstream: r182175 - Support unaligned load/store on more ARM targetsJF Bastien
This patch matches GCC behavior: the code used to only allow unaligned load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for v6+ Darwin as well as for v7+ on Linux and NaCl. The distinction is made because v6 doesn't guarantee support (but LLVM assumes that Apple controls hardware+kernel and therefore have conformant v6 CPUs), whereas v7 does provide this guarantee (and Linux/NaCl behave sanely). The patch keeps the -arm-strict-align command line option, and adds -arm-no-strict-align. They behave similarly to GCC's -mstrict-align and -mnostrict-align. I originally encountered this discrepancy in FastIsel tests which expect unaligned load/store generation. Overall this should slightly improve performance in most cases because of reduced I$ pressure. R=dschuff@chromium.org Review URL: https://codereview.chromium.org/15677005
2013-05-29Merging r182394:Bill Wendling
------------------------------------------------------------------------ r182394 | jholewinski | 2013-05-21 09:51:30 -0700 (Tue, 21 May 2013) | 1 line [NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29Merging r182298:Bill Wendling
------------------------------------------------------------------------ r182298 | jholewinski | 2013-05-20 09:42:18 -0700 (Mon, 20 May 2013) | 1 line [NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a symbol name error in the output PTX. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29Merging r182254:Bill Wendling
------------------------------------------------------------------------ r182254 | jholewinski | 2013-05-20 05:13:32 -0700 (Mon, 20 May 2013) | 12 lines [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs This converter currently only handles global variables in address space 0. For these variables, they are promoted to address space 1 (global memory), and all uses are updated to point to the result of a cvta.global instruction on the new variable. The motivation for this is address space 0 global variables are illegal since we cannot declare variables in the generic address space. Instead, we place the variables in address space 1 and explicitly convert the pointer to address space 0. This is primarily intended to help new users who expect to be able to place global variables in the default address space. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182826 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-29Merging r182253:Bill Wendling
------------------------------------------------------------------------ r182253 | jholewinski | 2013-05-20 05:13:28 -0700 (Mon, 20 May 2013) | 1 line [NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need to use .u8 for i1 parameters for kernels. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182825 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-22Merging r182486:Bill Wendling
------------------------------------------------------------------------ r182486 | d0k | 2013-05-22 10:01:12 -0700 (Wed, 22 May 2013) | 3 lines X86: When expanding PCMPGTQ to PCMPGTD we always want to compare the lower halves as unsigned. Take #2 on fixing PR15977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182489 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21Merging r182387:Bill Wendling
------------------------------------------------------------------------ r182387 | jholewinski | 2013-05-21 07:37:16 -0700 (Tue, 21 May 2013) | 7 lines Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen. The intrinsic calls are dropped, but the annotated value is propagated. Fixes PR 15253 Original patch by Zeng Bin! ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-21Merging r182364:Bill Wendling
------------------------------------------------------------------------ r182364 | d0k | 2013-05-21 02:58:54 -0700 (Tue, 21 May 2013) | 4 lines X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type. Otherwise we'll get a mix of signed and unsigned compares. Fixes PR15977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Merging r182113:Bill Wendling
------------------------------------------------------------------------ r182113 | tstellar | 2013-05-17 08:23:21 -0700 (Fri, 17 May 2013) | 9 lines R600: Fix encoding for R600 family GPUs Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64193 https://bugs.freedesktop.org/show_bug.cgi?id=64257 https://bugs.freedesktop.org/show_bug.cgi?id=64320 NOTE: This is a candidate for the 3.3 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@182174 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17Re-allow an x86-32 fast-isel optimization for NaCl / use shorter insts.Jan Voung
There was an old fix for r+r based memory references on x86-64 that checked for isTargetNaCl() instead of isTargetNaCl64(). This disabled some r+r for 32-bit. However, fast isel only sets up r+r with geps, and we don't have geps in the stable ABI. We could potentially add some similar pattern matching in the future... The problem we *do* see with the current bitcode, is that this change also made it preferred to use an index register instead of a base register. This made the memory references on x86-32 look like: cmpl ..., (,%eax,1) instead of cmpl ..., (%eax) So we had longer instructions. Total zipped nexe sizes: 5.73MB (old) vs 5.59 MB (new) (2.5%) Total not zipped: 17.28MB vs 16.28 MB (6%) runtime diffs (min of 5 runs) * eon 4.94 (old) vs 4.72 (new) (~4%) * mesa 21.64 vs 21.08 * mcf 5.76 vs 5.60 * vortex 4.21 vs 4.05 * perlbmk 27.62 vs 26.55 (the rest were under 2% better) BUG=https://code.google.com/p/nativeclient/issues/detail?id=3359 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/15047013
2013-05-17Cherry-pick r181922: Fix miscompile due to StackColoring incorrectly merging ↵Mark Seaborn
stack slots (PR15707) IR optimisation passes can result in a basic block that contains: llvm.lifetime.start(%buf) ... llvm.lifetime.end(%buf) ... llvm.lifetime.start(%buf) Before this change, calculateLiveIntervals() was ignoring the second lifetime.start() and was regarding %buf as being dead from the lifetime.end() through to the end of the basic block. This can cause StackColoring to incorrectly merge %buf with another stack slot. Fix by removing the incorrect Starts[pos].isValid() and Finishes[pos].isValid() checks. Just doing: Starts[pos] = Indexes->getMBBStartIdx(MBB); Finishes[pos] = Indexes->getMBBEndIdx(MBB); unconditionally would be enough to fix the bug, but it causes some test failures due to stack slots not being merged when they were before. So, in order to keep the existing tests passing, treat LiveIn and LiveOut separately rather than approximating the live ranges by merging LiveIn and LiveOut. This fixes PR15707. Patch by Mark Seaborn. BUG=https://code.google.com/p/nativeclient/issues/detail?id=3374 Review URL: https://codereview.chromium.org/15302009
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