diff options
| author | Mark Seaborn <mseaborn@chromium.org> | 2013-06-24 09:18:55 -0700 |
|---|---|---|
| committer | Mark Seaborn <mseaborn@chromium.org> | 2013-06-24 09:18:55 -0700 |
| commit | 41dd5ede22556305aed7ea2184a2905f187db78c (patch) | |
| tree | f554bb44a06adfb2cfc8428814d75183e69c399d /test/CodeGen | |
| parent | ae9f7fcc65aed800db82aaa55e5e72322f20af02 (diff) | |
Merge r179774: Allow misaligned stores in x86 fast-isel.
This change will fix the regression in -O0 translation time caused by
putting "align 1" on integer loads and stores, which was causing
FastISel to fall back to SelectionDAG more often.
> In X86FastISel::X86SelectStore(), improperly aligned stores are
> rejected and handled by the DAG-based ISel. However,
> X86FastISel::X86SelectLoad() makes no such requirement. There
> doesn't appear to be an x86 architectural correctness issue with
> allowing potentially unaligned store instructions. This patch
> removes this restriction.
>
> Patch by Jim Stichnot.
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3445
TEST=PNaCl toolchain trybots
Review URL: https://codereview.chromium.org/17575003
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/X86/fast-isel-unaligned-store.ll | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/test/CodeGen/X86/fast-isel-unaligned-store.ll b/test/CodeGen/X86/fast-isel-unaligned-store.ll new file mode 100644 index 0000000000..7ce7f676ad --- /dev/null +++ b/test/CodeGen/X86/fast-isel-unaligned-store.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s +; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s + +define i32 @test_store_32(i32* nocapture %addr, i32 %value) { +entry: + store i32 %value, i32* %addr, align 1 + ret i32 %value +} + +; CHECK: ret + +define i16 @test_store_16(i16* nocapture %addr, i16 %value) { +entry: + store i16 %value, i16* %addr, align 1 + ret i16 %value +} + +; CHECK: ret |