Re-allow an x86-32 fast-isel optimization for NaCl / use shorter insts.

There was an old fix for r+r based memory references on
x86-64 that checked for isTargetNaCl() instead of
isTargetNaCl64(). This disabled some r+r for 32-bit.
However, fast isel only sets up r+r with geps, and we don't
have geps in the stable ABI.  We could potentially add
some similar pattern matching in the future...

The problem we *do* see with the current bitcode, is that
this change also made it preferred to use an index register
instead of a base register. This made the memory references
on x86-32 look like:

  cmpl ..., (,%eax,1)

instead of

  cmpl ..., (%eax)

So we had longer instructions.
Total zipped nexe sizes: 5.73MB (old) vs 5.59 MB (new) (2.5%)
Total not zipped: 17.28MB vs 16.28 MB (6%)

runtime diffs (min of 5 runs)
* eon 4.94 (old) vs 4.72 (new) (~4%)
* mesa 21.64 vs 21.08
* mcf 5.76 vs 5.60
* vortex 4.21 vs 4.05
* perlbmk 27.62 vs 26.55
(the rest were under 2% better)

BUG=https://code.google.com/p/nativeclient/issues/detail?id=3359
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/15047013

1 files changed, 16 insertions, 0 deletions

diff --git a/test/CodeGen/X86/fast-isel-gep.ll b/test/CodeGen/X86/fast-isel-gep.ll
index f0375f8602..7cc5903202 100644
--- a/test/CodeGen/X86/fast-isel-gep.ll
+++ b/test/CodeGen/X86/fast-isel-gep.ll
@@ -1,6 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-linux -O0 | FileCheck %s --check-prefix=X64
 ; RUN: llc < %s -mtriple=x86_64-win32 -O0 | FileCheck %s --check-prefix=X64
 ; RUN: llc < %s -march=x86 -O0 | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=i686-nacl -march=x86 -O0 | FileCheck %s --check-prefix=NACL32
 
 ; GEP indices are interpreted as signed integers, so they
 ; should be sign-extended to 64 bits on 64-bit targets.
@@ -18,6 +19,11 @@ define i32 @test1(i32 %t3, i32* %t1) nounwind {
 ; X64:  	movl	(%r[[A1:si|dx]],%rax,4), %eax
 ; X64:  	ret
 
+; NACL32: test1:
+; NACL32:   movl (%e{{.*}},%e{{.*}},4), %eax
+; NACL32:   popl %ecx
+; NACL32:   nacljmp %ecx
+
 }
 define i32 @test2(i64 %t3, i32* %t1) nounwind {
        %t9 = getelementptr i32* %t1, i64 %t3           ; <i32*> [#uses=1]
@@ -30,6 +36,10 @@ define i32 @test2(i64 %t3, i32* %t1) nounwind {
 ; X64: test2:
 ; X64:  	movl	(%r[[A1]],%r[[A0]],4), %eax
 ; X64:  	ret
+
+; NACL32: test2:
+; NACL32:   movl (%e{{.*}},%e{{.*}},4), %e
+
 }
 
 
@@ -51,6 +61,10 @@ entry:
 ; X64:  	movb	-2(%r[[A0]]), %al
 ; X64:  	ret
 
+; NACL32: test3:
+; NACL32:   movl 4(%esp), %[[REG:e..]]
+; NACL32:   movb -2(%{{.*}}[[REG]]), %al
+
 }
 
 define double @test4(i64 %x, double* %p) nounwind {
@@ -70,6 +84,8 @@ entry:
 ; X32: 128(%e{{.*}},%e{{.*}},8)
 ; X64: test4:
 ; X64: 128(%r{{.*}},%r{{.*}},8)
+; NACL32: test4:
+; NACL32: 128(%e{{.*}},%e{{.*}},8)
 }
 
 ; PR8961 - Make sure the sext for the GEP addressing comes before the load that