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path: root/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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2011-10-27Add some NEON stores to the VLD decoding hook that were accidentally omitted ↵Owen Anderson
previously. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143162 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-25ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach
Four entry register lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach
Three entry register list variation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24ARM refactor am6offset usage for VLD1.Jim Grosbach
Split am6offset into fixed and register offset variants so the instruction encodings are explicit rather than relying an a magic reg0 marker. Needed to being able to parse these. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24Fix a NEON disassembly case that was broken in the recent refactorings. As ↵Owen Anderson
more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142817 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-22Move various generated tables into read-only memory, fixing up const ↵Benjamin Kramer
correctness along the way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21Assembly parsing for 4-register sequential variant of VLD2.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21Assembly parsing for 4-register variant of VLD1.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21Assembly parsing for 3-register variant of VLD1.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21ARM VLD parsing and encoding.Jim Grosbach
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20Tidy up. Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17Removed set, but unused variables.Chad Rosier
Patch by Joe Abbey <jabbey@arxan.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142223 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14Fix a non-firing assert. Change:Richard Trieu
assert("bad SymbolicOp.VariantKind"); To: assert(0 && "bad SymbolicOp.VariantKind"); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13Fix undefined shift. Patch by Ahmed Charles.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141914 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13SETEND is not allowed in an IT block.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12ARM addrmode5 represents the 'U' bit of the encoding backwards.Jim Grosbach
The disassembler needs to use the AM5 factory methods instead of just building up the immediate directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12addrmode2 is gone from these, so no need for the reg0 operand.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06Fix the check for nested IT instructions in the disassembler. We need to ↵Owen Anderson
perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04Adding back support for printing operands symbolically to ARM's new disassemblerKevin Enderby
using llvm's public 'C' disassembler API now including annotations. Hooked this up to Darwin's otool(1) so it can again print things like branch targets for example this: blx _puts instead of this: blx #-36 and includes support for annotations for branches to symbol stubs like: bl 0x40 @ symbol stub for: _puts and annotations for pc relative loads like this: ldr r3, #8 @ literal pool for: Hello, world! Also again can print the expression encoded in the Mach-O relocation entries for things like this: movt r0, :upper16:((_foo-_bar)+1234) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach
Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid ↵Owen Anderson
testcases updated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23Revert r140412. This affects more instructions than intended.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23Thumb2 register-shifted-register loads cannot target the PC or the SP.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19tMOVSr is not allowed in an IT block either.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19CPS instructions are UNPREDICTABLE inside IT blocks.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, ↵Owen Anderson
not in the middle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140079 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19Handle STRT (and friends) like LDRT (and friends) for decoding purposes. ↵Owen Anderson
Port over additional encoding tests to decoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Bitfield mask instructions are unpredictable if the encoded LSB is higher ↵Owen Anderson
than the encoded MSB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139972 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Fix bitfield decoding based on Eli's feedback.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139965 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Fix disassembly of Thumb2 LDRSH with a #-0 offset.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15Don't attach annotations to MCInst's. Instead, have the disassembler ↵Owen Anderson
return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139736 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Port more encoding tests to decoding tests, and correct an improper Thumb2 ↵Owen Anderson
pre-indexed load decoding this uncovered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09LDM writeback is not allowed if Rn is in the target register list.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson
have a predicate operand, unlike conditional branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139329 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Thumb2 assembly parsing and encoding for LDRD(immediate).Jim Grosbach
Refactor operand handling for STRD as well. Tests for that forthcoming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Remove the "common" set of instructions shared between ARM and Thumb2 modes. ↵Owen Anderson
This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Create Thumb2 versions of STC/LDC, and reenable the relevant tests.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds ↵James Molloy
predicate checking to the Disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Port more assembler tests over to disassembler tests, and fix a minor logic ↵Owen Anderson
error that exposed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
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