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authorOwen Anderson <resistor@mac.com>2011-09-19 18:07:10 +0000
committerOwen Anderson <resistor@mac.com>2011-09-19 18:07:10 +0000
commitecd1c557904815e568258fc5420de479589b0a93 (patch)
tree6196095d8744bcd816f02812c1a074041d3851d4 /lib/Target/ARM/Disassembler/ARMDisassembler.cpp
parent8a8d28b0392a27ff8e0c60c04561671023a08dc2 (diff)
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassembler.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index d76fb93d15..6cbe863d0e 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2761,6 +2761,9 @@ static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
case ARM::t2LDRHT:
case ARM::t2LDRSBT:
case ARM::t2LDRSHT:
+ case ARM::t2STRT:
+ case ARM::t2STRBT:
+ case ARM::t2STRHT:
imm |= 0x100;
break;
default: