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path: root/include/llvm/Target/TargetInstrDesc.h
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2011-06-28- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng
sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Remove RCBarriers from TargetInstrDesc.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15- Add "Bitcast" target instruction property for instructions which performEvan Cheng
nothing more than a bitcast. - Teach tablegen to automatically infer "Bitcast" property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29Merge System into Support.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120298 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng
and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23Revert r114703 and r114702, removing the isConditionalMove flag from ↵Owen Anderson
instructions. After further reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23Add an TargetInstrDesc bit to indicate that a given instruction is a ↵Owen Anderson
conditional move. Not intended functionality change, as nothing uses this yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114702 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Implement register class inflation.Jakob Stoklund Olesen
When splitting a live range, the new registers have fewer uses and the permissible register class may be less constrained. Recompute the register class constraint from the uses of new registers created for a split. This may let them be allocated from a larger set, possibly avoiding a spill. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-08Add back in r109901, which adds a Compare flag to the target instructions. It'sBill Wendling
useful after all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn'tBill Wendling
need the Compare flag after all. --- Reverse-merging r109901 into '.': U include/llvm/Target/TargetInstrDesc.h U include/llvm/Target/Target.td U utils/TableGen/InstrInfoEmitter.cpp U utils/TableGen/CodeGenInstruction.cpp U utils/TableGen/CodeGenInstruction.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110424 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30Add a "Compare" flag to the target instruction descriptor. This will be usedBill Wendling
later to identify and possibly remove superfluous compare instructions -- those that are testing for and setting a status flag that should already be set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman
MachineRegisterInfo doesn't have to confusingly allocate an extra entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes
immediates to avoid breaking the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner
In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-05Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes
yet, only assembly encoding support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24add a convenient TargetInstrDesc::getNumImplicitUses/Defs method.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99446 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16Add @earlyclobber TableGen constraintJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91554 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-29Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman
bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. WhenEvan Cheng
set, these flags indicate the instructions source / def operands have special register allocation requirement that are not captured in their register classes. Post-allocation passes (e.g. post-alloc scheduler) should not change their allocations. e.g. ARM::LDRD require the two definitions to be allocated even / odd register pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83196 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-291. Introduce a new TargetOperandInfo::getRegClass() helper methodChris Lattner
and convert code to using it, instead of having lots of things poke the isLookupPtrRegClass() method directly. 2. Make PointerLikeRegClass contain a 'kind' int, and store it in the existing regclass field of TargetOperandInfo when the isLookupPtrRegClass() predicate is set. Make getRegClass pass this into TargetRegisterInfo::getPointerRegClass(), allowing targets to have multiple ptr_rc things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77504 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-12Add new TargetInstrDesc::hasImplicitUseOfPhysReg andChris Lattner
hasImplicitDefOfPhysReg methods. Use them to remove a look in X86 fast isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68886 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09Fix pr3954. The register scavenger asserts for inline assembly withBob Wilson
register destinations that are tied to source operands. The TargetInstrDescr::findTiedToSrcOperand method silently fails for inline assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very close to doing what is needed, so this revision makes a few changes to that method and also renames it to isRegTiedToUseOperand (for consistency with the very similar isRegTiedToDefOperand and because it handles both two-address instructions and inline assembly with tied registers). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05Clarify comments.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63851 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-05Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-22Clarify a comment.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61338 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03Mark x86's V_SET0 and V_SETALLONES with isSimpleLoad, and teach X86'sDan Gohman
foldMemoryOperand how to "fold" them, by converting them into constant-pool loads. When they aren't folded, they use xorps/cmpeqd, but for example when register pressure is high, they may now be folded as memory operands, which reduces register pressure. Also, mark V_SET0 isAsCheapAsAMove so that two-address-elimination will remat it instead of copying zeros around (V_SETALLONES was already marked). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60461 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17Add RCBarriers to TargetInstrDesc. It's a list of register classes the given ↵Evan Cheng
instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers. TableGen has been taught to generate the lists from instruction definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57722 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-28Add a flag to indicate that an instruction is as cheap (or cheaper) than a moveBill Wendling
instruction to execute. This can be used for transformations (like two-address conversion) to remat an instruction instead of generating a "move" instruction. The idea is to decrease the live ranges and register pressure and all that jazz. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51660 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-09Fix some minor errors in comments.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49445 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-15Remove isImplicitDef TargetInstrDesc flag.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-22Remove an invalid assertion now that there are implicit virtual register ↵Evan Cheng
operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47493 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10Simplify the side effect stuff a bit more and make licm/sinkingChris Lattner
both work right according to the new flags. This removes the TII::isReallySideEffectFree predicate, and adds TII::isInvariantLoad. It removes NeverHasSideEffects+MayHaveSideEffects and adds UnmodeledSideEffects as machine instr flags. Now the clients can decide everything they need. I think isRematerializable can be implemented in terms of the flags we have now, though I will let others tackle that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45843 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-08add a mayLoad property for machine instructions, a correlary to mayStore.Chris Lattner
This is currently not set by anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07split TargetInstrDesc out into its own header file.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45696 91177308-0d34-0410-b5e6-96231b3b80d8
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