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path: root/include/llvm/CodeGen/MachineInstr.h
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2011-12-06First chunk of MachineInstr bundle support.Evan Cheng
1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Add MachineInstr::getRegClassConstraint().Jakob Stoklund Olesen
Most instructions have some requirements for their register operands. Usually, this is expressed as register class constraints in the MCInstrDesc, but for inline assembly the constraints are encoded in the flag words. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141835 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12Extract a method for finding the inline asm flag operand.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141834 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-29Remove NumImplicitOps which is now unused.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02Include a source location when complaining about bad inline assembly.Jakob Stoklund Olesen
Add a MI->emitError() method that the backend can use to report errors related to inline assembly. Call it from X86FloatingPoint.cpp when the constraints are wrong. This enables proper clang diagnostics from the backend: $ clang -c pr30848.c pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack __asm__ ("" : "=u" (d)); /* { dg-error "output regs" } */ ^ 1 error generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134307 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Create a isFullCopy predicate.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng
sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-12Re-commit 131172 with fix. MachineInstr identity checks should check deadEvan Cheng
markers. In some cases a register def is dead on one path, but not on another. This is passing Clang self-hosting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131214 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-1180 columns.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127493 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Add FrameSetup MI flagsAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Shorten AsmPrinterFlags filed to accomodate for future Flags fieldAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127097 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng
Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-21add some helper methods for asmprinter flags, from PR8417Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119932 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12add operand iterator apis to MachineInstr, patch by ether zhhb.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22Transfer implicit ops when forming load multiple and return instructions.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117151 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling
thus is a much more meaningful name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-03Detect and handle COPY in many places.Jakob Stoklund Olesen
This code is transitional, it will soon be possible to eliminate isExtractSubreg, isInsertSubreg, and isMoveInstr in most places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107547 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02Add a new target independent COPY instruction and code to lower it.Jakob Stoklund Olesen
The COPY instruction is intended to replace the target specific copy instructions for virtual registers as well as the EXTRACT_SUBREG and INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection DAG. COPY is lowered to native register copies by LowerSubregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Teach regular and fast isel to set dead flags on unused implicit defsDan Gohman
on calls and similar instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen
instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defsEvan Cheng
that are aliases of the specified register. - Rename modifiesRegister to definesRegister since it's looking a def of the specific register or one of its super-registers. It's not looking for def of a sub-register or alias that could change the specified register. - Added modifiesRegister to look for defs of aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21Add MachineInstr::readsWritesVirtualRegister() to determine if an instructionJakob Stoklund Olesen
reads or writes a register. This takes partial redefines and undef uses into account. Don't actually use it yet. That caused miscompiles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a ↵Jakob Stoklund Olesen
register is read." This reverts r104322. I think it was causing miscompilations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.Jakob Stoklund Olesen
This correctly handles partial redefines and undef uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21If the first definition of a virtual register is a partial redef, add anJakob Stoklund Olesen
<imp-def> operand for the full register. This ensures that the full physical register is marked live after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19Add MachineInstr::readsVirtualRegister() in preparation for proper handling ofJakob Stoklund Olesen
partial redefines. We are going to treat a partial redefine of a virtual register as a read-modify-write: %reg1024:6 = OP Unless the register is fully clobbered: %reg1024:6 = OP, %reg1024<imp-def> MachineInstr::readsVirtualRegister() knows the difference. The first case is a read, the second isn't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13Teach MachineLICM and MachineSink how to clear kill flags conservativelyDan Gohman
when they move instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103737 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05Move REG_SEQUENCE removal to 2addr pass.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103109 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09Fix up header comments to match the comment fixups I made in r100849.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08Coalescer should not delete copy instructions whose defs are partially dead. ↵Evan Cheng
e.g. %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02rename NewDebugLoc -> DebugLoc, prune #includes in DebugLoc.h.Chris Lattner
This keeps around temporary typedef for clang/llvm-gcc so the build won't break when I commit this :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03Move MachineInstrExpressionTrait::getHashValue() out of line so it can skip ↵Evan Cheng
over only virtual register defs. This matches what isEqual() is doing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97680 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03Re-apply r97667 but with a little bit of thought put into the patch. This ↵Evan Cheng
implements a special DenseMapInfo trait for DenseMap<MachineInstr*> that compare the value of the MachineInstr rather than the pointer value. Since the hashing and equality test functions ignore defs it's useful for doing CSE kind optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97678 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03Revert 97667. It broke a bunch of tests.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97673 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03Move DenseMapInfo for MachineInstr* to MachineInstr.hEvan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03- Change MachineInstr::isIdenticalTo to take a new option that determines ↵Evan Cheng
whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. - Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02Swap parameters of isSafeToMove and isSafeToReMat for consistency.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97578 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-10Fix "the the" and similar typos.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-10fix a layering violation: VirtRegRewriter.cpp shouldn't use AsmPrinter.h.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95748 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-10Stop MachineInstr.h from #including AsmPrinter.hChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09move target-independent opcodes out of TargetInstrInfoChris Lattner
into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-06Add <imp-def> and <imp-kill> operands when replacing virtual sub-register ↵Jakob Stoklund Olesen
defs and kills. An instruction like this: %reg1097:1<def> = VMOVSR %R3<kill>, 14, %reg0 Must be replaced with this when substituting physical registers: %S0<def> = VMOVSR %R3<kill>, 14, %reg0, %D0<imp-def> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-03Fill out codegen SSA updater. It's not yet tested.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90395 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12Add AsmPrinter comment flags to machine instructions so that AsmPrinterDavid Greene
can emit extra information in comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87018 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman
is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07Replace TargetInstrInfo::isInvariantLoad and its target-specificDan Gohman
implementations with a new MachineInstr::isInvariantLoad, which uses MachineMemOperands and is target-independent. This brings MachineLICM and other functionality to targets which previously lacked an isInvariantLoad implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83475 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25Improve MachineMemOperand handling.Dan Gohman
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-17grammarJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82149 91177308-0d34-0410-b5e6-96231b3b80d8
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