diff options
author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-07-08 16:40:22 +0000 |
---|---|---|
committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-07-08 16:40:22 +0000 |
commit | 0bc25f40402f48ba42fc45403f635b20d90fabb3 (patch) | |
tree | da54f1273d8837a03ebf46bee701c2c19a05a573 /include/llvm/CodeGen/MachineInstr.h | |
parent | 5c00e077952d14899c3fc26709c7b2dfd36d0209 (diff) |
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.
Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/MachineInstr.h')
-rw-r--r-- | include/llvm/CodeGen/MachineInstr.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 08ada4cc91..e67b2dda11 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -215,9 +215,6 @@ public: bool isKill() const { return getOpcode() == TargetOpcode::KILL; } bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; } - bool isExtractSubreg() const { - return getOpcode() == TargetOpcode::EXTRACT_SUBREG; - } bool isInsertSubreg() const { return getOpcode() == TargetOpcode::INSERT_SUBREG; } @@ -234,7 +231,13 @@ public: /// isCopyLike - Return true if the instruction behaves like a copy. /// This does not include native copy instructions. bool isCopyLike() const { - return isCopy() || isSubregToReg() || isExtractSubreg() || isInsertSubreg(); + return isCopy() || isSubregToReg(); + } + + /// isIdentityCopy - Return true is the instruction is an identity copy. + bool isIdentityCopy() const { + return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() && + getOperand(0).getSubReg() == getOperand(1).getSubReg(); } /// readsRegister - Return true if the MachineInstr reads the specified |