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authorRobert Jordens <jordens@gmail.com>2017-10-05 15:44:58 +0200
committerTomas Vanek <vanekt@fbl.cz>2018-03-07 23:42:01 +0000
commitfd6986168a5e9f33b8dba628b9d9e42196c02923 (patch)
tree47d9f8a63f2fd4a2662a0d48847c5a2c46476d59 /tcl/interface/ftdi
parent06e13d6ff56175317ae39ee0e86efbf55d2b27fd (diff)
pipistrello: decrease jtag speed to 10 MHz
30 MHz is not working reliably here Change-Id: I38f5f8c7153fc64e313ee911b1629fb5f1114c39 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4242 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'tcl/interface/ftdi')
-rw-r--r--tcl/interface/ftdi/pipistrello.cfg2
1 files changed, 1 insertions, 1 deletions
diff --git a/tcl/interface/ftdi/pipistrello.cfg b/tcl/interface/ftdi/pipistrello.cfg
index b51405a2..5ee5be5b 100644
--- a/tcl/interface/ftdi/pipistrello.cfg
+++ b/tcl/interface/ftdi/pipistrello.cfg
@@ -10,4 +10,4 @@ ftdi_layout_init 0x0008 0x000b
reset_config none
# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
-adapter_khz 30000
+adapter_khz 10000