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2013-05-13The purpose of the patch is to fix the syntax of ARM mrc and mrc2 ↵Mihai Popa
instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30s tightens up the encoding description for ARM post-indexed ldr ↵Mihai Popa
instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet
"hint" space for Thumb actually overlaps the encoding space of the CPS instruction. In actuality, hints can be defined as CPS instructions where imod and M bits are all nil. Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe, sev) in DecodeT2CPSInstruction. This commit adds a proper diagnostic message for Imm0_4 and updates all tests. Patch by Mihail Popa <Mihail.Popa@arm.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover
Patch from Mihail Popa git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12ARM: Correct printing of pre-indexed operands.Quentin Colombet
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179398 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover
These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when ↵Gordon Keiser
the upper bit is set. They should always be zero-extended, not sign extended. Added test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178275 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Patch by Gordon Keiser!Joe Abbey
If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178017 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-22Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵Kristof Beyls
instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls
The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Added a option to the disassembler to print immediates as hex.Kevin Enderby
This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169393 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby
which would then cause an assert when printed. rdar://11437956 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30ARM: Better disassembly for pc-relative LDR.Jim Grosbach
When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby
is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22Add support for annotated disassembly output for X86 and arm.Kevin Enderby
Per the October 12, 2012 Proposal for annotated disassembly output sent out by Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc tool now has a -mdis option to produced the marked up disassembly and a couple of small example test cases have been added. rdar://11764962 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166445 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover
Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover
instructions. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06Use correct part of complex operand to encode VST1 alignment.Tim Northover
Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-13ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines.Jim Grosbach
These tests weren't actually being run before (missing ':' after CHECK). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu
index issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton
single-precision resiters) (and do it properly this time! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Fix the remaining TCL-style quotes found in the testsuite. This isChandler Carruth
another mechanical change accomplished though the power of terrible Perl scripts. I have manually switched some "s to 's to make escaping simpler. While I started this to fix tests that aren't run in all configurations, the massive number of tests is due to a really frustrating fragility of our testing infrastructure: things like 'grep -v', 'not grep', and 'expected failures' can mask broken tests all too easily. Essentially, I'm deeply disturbed that I can change the testsuite so radically without causing any change in results for most platforms. =/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159547 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Convert the uses of '|&' to use '2>&1 |' instead, which works on oldChandler Carruth
versions of Bash. In addition, I can back out the change to the lit built-in shell test runner to support this. This should fix the majority of fallout on Darwin, but I suspect there will be a few straggling issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159544 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Convert all tests using TCL-style quoting to use shell-style quoting.Chandler Carruth
This was done through the aid of a terrible Perl creation. I will not paste any of the horrors here. Suffice to say, it require multiple staged rounds of replacements, state carried between, and a few nested-construct-parsing hacks that I'm not proud of. It happens, by luck, to be able to deal with all the TCL-quoting patterns in evidence in the LLVM test suite. If anyone is maintaining large out-of-tree test trees, feel free to poke me and I'll send you the steps I used to convert things, as well as answer any painful questions etc. IRC works best for this type of thing I find. Once converted, switch the LLVM lit config to use ShTests the same as Clang. In addition to being able to delete large amounts of Python code from 'lit', this will also simplify the entire test suite and some of lit's architecture. Finally, the test suite runs 33% faster on Linux now. ;] For my 16-hardware-thread (2x 4-core xeon e5520): 36s -> 24s git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Correct decoder for T1 conditional B encodingRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Added the missing bit definition for the 4th bit of the STR (post reg) ↵Silviu Baranga
instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby
for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26Specify cpu to unbreak tests.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155453 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)Kevin Enderby
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155444 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Added support for disassembling unpredictable swp/swpb ARM instructions.Silviu Baranga
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Fix the bahavior of the disassembler when decoding unpredictable mrs ↵Silviu Baranga
instructions on ARM. Now the diasassembler emmits warnings instead of errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ↵Silviu Baranga
disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Fixed decoding for the ARM cdp2 instruction. The restriction on the ↵Silviu Baranga
coprocessor number was removed for this instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM ↵Silviu Baranga
instructions in the disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)Kevin Enderby
instructions with writebacks. And add test a case for all opcodes handed by DecodeVLD2DupInstruction() in ARMDisassembler.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11Fixed a case of ARM disassembly getting an assert on a bad encodingKevin Enderby
of a VST instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11Fix ARM disassembly of VLD instructions with writebacks.  And add test a caseKevin Enderby
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng
1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05Added support for unpredictable ADC/SBC instructions on ARM, and also fixed ↵Silviu Baranga
some corner cases involving the PC register as an operand for these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05Added support for handling unpredictable arithmetic instructions on ARM.Silviu Baranga
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154100 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-02Added fix in TableGen instruction decoder generation. The decoder now breaks ↵Silviu Baranga
for every leaf node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153874 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-25Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnuEli Bendersky
* Removed test/lib/llvm.exp - it is no longer needed * Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files left in the test suite so this code is no longer required. test/lit.cfg is now much shorter and clearer * Removed a lot of duplicate code in lit.local.cfg files that need access to the root configuration, by adding a "root" attribute to the TestingConfig object. This attribute is dynamically computed to provide the same information as was previously provided by the custom getRoot functions. * Documented the config.root attribute in docs/CommandGuide/lit.pod git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22Added soft fail checks for the disassembler when decoding some corner cases ↵Silviu Baranga
of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or ↵Silviu Baranga
LDRSHT instruction on ARM git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
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