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2013-05-13The purpose of the patch is to fix the syntax of ARM mrc and mrc2 ↵Mihai Popa
instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05[XCore] Add LDAPB instructions.Richard Osborne
With the change the disassembler now supports the XCore ISA in its entirety. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05[XCore] Add BLRB instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30s tightens up the encoding description for ARM post-indexed ldr ↵Mihai Popa
instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet
"hint" space for Thumb actually overlaps the encoding space of the CPS instruction. In actuality, hints can be defined as CPS instructions where imod and M bits are all nil. Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe, sev) in DecodeT2CPSInstruction. This commit adds a proper diagnostic message for Imm0_4 and updates all tests. Patch by Mihail Popa <Mihail.Popa@arm.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover
Patch from Mihail Popa git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18[mips] DSP-ASE move from HI/LO register instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Use object file specific section type for initial text sectionNico Rieck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12ARM: Correct printing of pre-indexed operands.Quentin Colombet
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179398 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Add CLAC/STAC instruction encoding/decoding supportMichael Liao
As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test casesKay Tiong Khoo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179223 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover
These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04[XCore] Add bru instruction.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04[XCore] The RRegs register class is a superset of GRRegs.Richard Osborne
At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03[XCore] Check disassembly of the st8 instruction.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178689 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03[XCore] Update disassembler test to improve coverage of the instructions.Richard Osborne
Previously some instructions were unintentionally covered twice and others were not covered at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178688 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03AArch64: implement ETMv4 trace system registers.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when ↵Gordon Keiser
the upper bit is set. They should always be zero-extended, not sign extended. Added test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178275 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28AArch64: implement GICv3 system registersTim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178236 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Patch by Gordon Keiser!Joe Abbey
If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178017 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-25x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki
This fixes Apple bug: 13493622 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177887 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-11Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby
rdar://13318048 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-28AArch64: remove post-encoder method from FCMP (immediate) instructions.Tim Northover
The work done by the post-encoder (setting architecturally unused bits to 0 as required) can be done by the existing operand that covers the "#0.0". This removes at least one use of the discouraged PostEncoderMethod uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176261 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-22Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵Kristof Beyls
instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17[XCore] Add missing 2r instructions.Richard Osborne
These instructions are not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17[XCore] Add TSETR instruction.Richard Osborne
This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17[XCore] Add missing u10 / lu10 instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17[XCore] Add missing u6 / lu6 instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14death to extra whitespaceKay Tiong Khoo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175200 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14added basic support for Intel ADX instructionsKay Tiong Khoo
-feature flag, instructions definitions, test cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls
The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12added test cases for r174920 (prefetch disassembly)Kay Tiong Khoo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174979 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11*fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo
*added file for test cases for i386 intel syntax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174900 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Add AArch64 CRC32 instructionsTim Northover
These instructions are a late addition to the architecture, and may yet end up behind an optional attribute, but for now they're available at all times. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174496 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06Add icache prefetch operations to AArch64Tim Northover
This adds hints to the various "prfm" instructions so that they can affect the instruction cache as well as the data cache. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174495 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31Add AArch64 as an experimental target.Tim Northover
This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing l2rus instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing l2r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing 1r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27[XCore] Add missing 0r instructions.Richard Osborne
These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add instruction encodings / disassembly support for l4r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25Add instruction encodings / disassembly support for l5r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23Add instruction encodings / disassembly support for l6r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22Add instruction encodings / disassembly support for u10 / lu10 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Add instruction encodings / disassembly support for u6 / lu6 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21Add instruction encoding / disassembly support for ru6 / lru6 instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembly support for l2rus instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembly support for l3r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20Add instruction encodings / disassembler support for 2rus instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
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