aboutsummaryrefslogtreecommitdiff
path: root/test/CodeGen/X86
AgeCommit message (Expand)Author
2011-12-30Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size,...Craig Topper
2011-12-28Fix type-checking for load transformation which is not legal on floating-poin...Eli Friedman
2011-12-28PR11662.Nadav Rotem
2011-12-28Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR.Elena Demikhovsky
2011-12-26Make sure DAGCombiner doesn't introduce multiple loads from the same memory l...Eli Friedman
2011-12-24Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when theChandler Carruth
2011-12-24Add systematic testing for cttz as well, and fix the bug I spotted byChandler Carruth
2011-12-24Add i8 and i64 testing for ctlz on x86. Also simplify the i16 test.Chandler Carruth
2011-12-24Tidy up this rather crufty test. Put the declarations at the top to makeChandler Carruth
2011-12-24Expand more when we have a nice 'tzcnt' instruction, to avoid generatingChandler Carruth
2011-12-24Tidy up some of these tests.Chandler Carruth
2011-12-24Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to theChandler Carruth
2011-12-24Cleanup this test a bit, sorting things and grouping them more clearly.Chandler Carruth
2011-12-20This is the second fix related to VZEXT_MOVL node.Elena Demikhovsky
2011-12-20Begin teaching the X86 target how to efficiently codegen patterns thatChandler Carruth
2011-12-17Make sure that the lower bits on the VSELECT condition are properly set.Lang Hames
2011-12-16Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is su...Craig Topper
2011-12-15Add missing zmovl AVX patterns which were causing crashes.Chad Rosier
2011-12-15Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.Chad Rosier
2011-12-15Set specific target cpu for testcase.Lang Hames
2011-12-15Added test case for r146671.Lang Hames
2011-12-15Don't try to form FGETSIGN after legalization; it is possible in some cases, ...Eli Friedman
2011-12-15Add support for lowering fneg when AVX is enabled.Chad Rosier
2011-12-12Manually upgrade the test suite to specify the flag to cttz and ctlz.Chandler Carruth
2011-12-09Update test to something more sensible.Evan Cheng
2011-12-09X86: Add patterns for the various rounding ops for SSE4.1 and AVX.Benjamin Kramer
2011-12-09Forgot setting -march.Evan Cheng
2011-12-08Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417Evan Cheng
2011-12-08Add various missing AVX patterns which was causing crashes. Sadly, the generatedEvan Cheng
2011-12-08Add test for r146163.Evan Cheng
2011-12-08test/CodeGen/X86/vec_compare-2.ll: Add explicit -mtriple=i686-linux.NAKAMURA Takumi
2011-12-08Fix a bug in the integer-promotion of bitcast operations on vector types.Nadav Rotem
2011-12-07Support vector bitcasts in the AsmPrinter. PR11495.Eli Friedman
2011-12-07Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves c...Eli Friedman
2011-12-06Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other inte...Craig Topper
2011-12-06Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do bo...Craig Topper
2011-12-05test/CodeGen/X86/pointer-vector.ll: Add explicit -mtriple=i686-linux.NAKAMURA Takumi
2011-12-05Add support for vectors of pointers.Nadav Rotem
2011-12-03Check for stack space more intelligently.Sanjoy Das
2011-12-03Fix a bug in the x86-32 code generated for segmented stacks.Sanjoy Das
2011-12-02Add instruction selection support for horizontal add/sub of 256-bit floating ...Craig Topper
2011-12-01For 64-bit the rest of the general regs are ok for the q constraint. MakeEric Christopher
2011-12-01Pass AVX vectors which are arguments to varargs functions on the stack. <rdar...Eli Friedman
2011-11-30Support for encoding all FMA4 instructions and tablegen patterns for allJan Sjödin
2011-11-30Add test arch to make it pass on non x86 targetsNadav Rotem
2011-11-30Add a tripple to the testNadav Rotem
2011-11-30X86: PerformOrCombine introduced a vselect node with a wrong order of operand...Nadav Rotem
2011-11-29Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was...Evan Cheng
2011-11-29Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.Jakob Stoklund Olesen
2011-11-29Fixed vsqrt.ss intrinsic usage - order of input operands was wrong.Elena Demikhovsky