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AgeCommit message (Expand)Author
2011-12-05Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR in...Craig Topper
2011-12-05Clean up and optimizations to the X86 shuffle lowering code. No functional ch...Craig Topper
2011-12-04Fix 80-column issues.Bob Wilson
2011-12-03Emit the ctors in the proper order on ARM/EABI.Anton Korobeynikov
2011-12-03Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() sinceVenkatraman Govindaraju
2011-12-03Check for stack space more intelligently.Sanjoy Das
2011-12-03Fix a bug in the x86-32 code generated for segmented stacks.Sanjoy Das
2011-12-03Creating multiple JITs on X86 in multiple threads causes multiple writes (ofNick Lewycky
2011-12-03[arm-fast-isel] Unaligned stores of floats require special care.Chad Rosier
2011-12-02ARM NEON VEXT aliases for data type suffices.Jim Grosbach
2011-12-02ARM VEXT tighten up operand classes a bit.Jim Grosbach
2011-12-02ARM VST1 single lane assembly parsing.Jim Grosbach
2011-12-02Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky
2011-12-02ARM VLD1 single lane assembly parsing.Jim Grosbach
2011-12-02ARM encoder method needs the physical register number, not the enum.Jim Grosbach
2011-12-02[arm-fast-isel] After promoting a function parameter be sure to update theChad Rosier
2011-12-02Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.Jim Grosbach
2011-12-02Add XOP feature flag.Jan Sjödin
2011-12-02Reduce duplicate code in isHorizontalBinOp and add some asserts to protect as...Craig Topper
2011-12-02Add instruction selection support for horizontal add/sub of 256-bit floating ...Craig Topper
2011-12-02remove unneeded FIXME commentHal Finkel
2011-12-02update PPC 940 hazard rec. to function in postRA modeHal Finkel
2011-12-02ARM start parsing VLD1 single lane instructions.Jim Grosbach
2011-12-01Dummy commit to check commit access.Sanjoy Das
2011-12-01Add missing functions.Chad Rosier
2011-12-01Add a few more functions to TargetLibraryInfo. More of rdar://10500969.Chad Rosier
2011-12-01For 64-bit the rest of the general regs are ok for the q constraint. MakeEric Christopher
2011-12-01Pass AVX vectors which are arguments to varargs functions on the stack. <rdar...Eli Friedman
2011-12-01Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostyle...Eli Friedman
2011-11-30Support for encoding all FMA4 instructions and tablegen patterns for allJan Sjödin
2011-11-30Remove unused variableMatt Beaumont-Gay
2011-11-30ARM parsing for VLD1 all lanes, with writeback.Jim Grosbach
2011-11-30Add a few functions to TargetLibraryInfo.Chad Rosier
2011-11-30ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach
2011-11-30X86: Turns out bulldozer also supports sse42 and lzcnt.Benjamin Kramer
2011-11-30X86: Add subtargets for AMD's bulldozer.Benjamin Kramer
2011-11-30X86: PerformOrCombine introduced a vselect node with a wrong order of operand...Nadav Rotem
2011-11-30Add instruction selection support for AVX2 horizontal add/sub instructions.Craig Topper
2011-11-30Merge VPERM2F128/VPERM2I128 ISD node types.Craig Topper
2011-11-30Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node ty...Craig Topper
2011-11-30Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functionalChad Rosier
2011-11-30ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach
2011-11-29Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable Chad Rosier
2011-11-29Tidy up a bit.Jim Grosbach
2011-11-29Add comment.Jim Grosbach
2011-11-29ARM parsing aliases for data-size suffices on VST1.Jim Grosbach
2011-11-29Change names for MIPS "generic" processors defined in Mips.td to match what GNUAkira Hatanaka
2011-11-29ARM assembly parsing and encoding for four-register VST1.Jim Grosbach
2011-11-29Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was...Evan Cheng
2011-11-29ARM assembly parsing and encoding for three-register VST1.Jim Grosbach
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