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AgeCommit message (Expand)Author
2012-05-01Move MipsDisassembler classes into an anonymous namespace.Benjamin Kramer
2012-05-01Value-initialize global to avoid global construction.Benjamin Kramer
2012-05-01Change the PassManager from a reference to a pointer.Bill Wendling
2012-05-01Allow BMI, AES, F16C, POPCNT, FMA3, and CLMUL to be detected on AMD processors.Craig Topper
2012-05-01Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify B...Craig Topper
2012-05-01Attempt to handle MRMInitReg in emitVEXOpcodePrefix. Hopefully fixes PR12711.Craig Topper
2012-05-01Make XOP imply AVX as its needed to legalize the registers types.Craig Topper
2012-05-01Remove HasSSE2 from AES and CLMUL predicates. It's now implied by the HasAES ...Craig Topper
2012-05-01Make CLMUL and AES imply SSE2 since its needed to legalize the type.Craig Topper
2012-05-01Enable AVX and FMA4 for AMD Bulldozer processors.Craig Topper
2012-04-30X86: optimization for -(x != 0)Manman Ren
2012-04-30ARM: Diagnostics for out of range fixups.Jim Grosbach
2012-04-30Fix address calculation error from r155744.Jakob Stoklund Olesen
2012-04-30Tidy up. No functional change intended.Chad Rosier
2012-04-30Fix fastcc structure return with fast-isel on x86-32Derek Schuff
2012-04-30Don't introduce illegal types when creating vmull operations. <rdar://11324364>Bob Wilson
2012-04-30No need to normalize index before calling Extract128BitVectorCraig Topper
2012-04-30Copied all the VEX prefix encoding code from X86MCCodeEmitter to the x86 JIT ...Pete Cooper
2012-04-29Remove unneeded casts. No functionality change.Jakub Staszak
2012-04-29Simplify code a bit. No functional change intended.Craig Topper
2012-04-29Update the documentation of CellSPU, in case it gets removed in 3.1.Kalle Raiskila
2012-04-28Fix a problem with blocks that need to be split twice.Jakob Stoklund Olesen
2012-04-27ARM: Thumb add(sp plus register) asm constraints.Jim Grosbach
2012-04-27ARM: Tweak tADDrSP definition for consistent operand order.Jim Grosbach
2012-04-27Revert r155745Derek Schuff
2012-04-27Fix fastcc structure return with fast-isel on x86-32Derek Schuff
2012-04-27Track worst case alignment padding more accurately.Jakob Stoklund Olesen
2012-04-27Use 'unsigned' instead of 'int' in several places when retrieving number of v...Craig Topper
2012-04-27Add x86-specific DAG combine to simplify:Chad Rosier
2012-04-27Tidy up spacing.Craig Topper
2012-04-27Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,Lang Hames
2012-04-27Fix ARM assembly parsing for upper case condition codes on IT instructions.Richard Barton
2012-04-27X86: Don't emit conditional floating point moves on when targeting pre-pentiu...Benjamin Kramer
2012-04-27Refactor IT handling not to store the bottom bit of the condition code in the...Richard Barton
2012-04-27Implement a bastardized ABI.Evan Cheng
2012-04-27- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng
2012-04-26ARM: Thumb ldr(literal) base address alignment is 32-bits.Jim Grosbach
2012-04-26Trivial change to set UseLeaForSP flag in addition to togglingPreston Gurd
2012-04-26Use VLD1 in NEON extenting-load patterns instead of VLDR.Tim Northover
2012-04-26Test commit.Tim Northover
2012-04-26Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei...Craig Topper
2012-04-26If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assumeEvan Cheng
2012-04-25Unify internal representation of ARM instructions with a register right-shift...Richard Barton
2012-04-25Add ifdef around getSubtargetFeatureName in tablegen output file so that only...Craig Topper
2012-04-25Use vector_shuffles instead of target specific unpack nodes for AVX ZERO_EXTE...Craig Topper
2012-04-25Do not use $gp as a dedicated global register if the target ABI is not O32. Akira Hatanaka
2012-04-24ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach
2012-04-24ARM: Nuke remnant bogus code.Jim Grosbach
2012-04-24AVX: Add additional vbroadcast replacement sequences for integers.Nadav Rotem
2012-04-24AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8Nadav Rotem
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