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AgeCommit message (Expand)Author
2013-04-26R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTETom Stellard
2013-04-26ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet
2013-04-26PowerPC: Use RegisterOperand instead of RegisterClass operandsUlrich Weigand
2013-04-26PowerPC: Fix encoding of vsubcuw and vsum4sbs instructionsUlrich Weigand
2013-04-26PowerPC: Fix encoding of stfsu and stfdu instructionsUlrich Weigand
2013-04-26PowerPC: Fix encoding of rldimi and rldcl instructionsUlrich Weigand
2013-04-26PowerPC: Support PC-relative fixup_ppc_brcond14.Ulrich Weigand
2013-04-26ARM/NEON: Pattern match vector integer abs to vabs.Benjamin Kramer
2013-04-26X86: Now that we have a canonical form for vector integer abs, match it into ...Benjamin Kramer
2013-04-25Mips assembler: .set reorder supportJack Carter
2013-04-25Make function documentation conform to llvm standards.Preston Gurd
2013-04-25ARM cost model: Integer div and rem is lowered to a function callArnold Schwaighofer
2013-04-25This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd
2013-04-25Fix section relocation for SECTIONREL32 with immediate offset.Rafael Espindola
2013-04-25[mips] Add definitions of micromips load and store instructions.Akira Hatanaka
2013-04-25[mips] Add definitions of micromips shift instructions.Akira Hatanaka
2013-04-24R600: Initialize BooleanVectorContentsTom Stellard
2013-04-24R600: Use SHT_PROGBITS for the .AMDGPU.config sectionTom Stellard
2013-04-23Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.Jyotsna Verma
2013-04-23Hexagon: Define relations for GP-relative instructions.Jyotsna Verma
2013-04-23Add more tests for r179925 to verify correct handling of signext/zeroext; str...Stephen Lin
2013-04-23Lowercase "is" boolean variable prefix for consistency within function, no fu...Stephen Lin
2013-04-23Hexagon: Remove assembler mapped instruction definitions.Jyotsna Verma
2013-04-23Change commentary for PowerPC Boolean vector contents.Bill Schmidt
2013-04-23[mips] Compare splat value with element size instead of calling isUIntN.Akira Hatanaka
2013-04-23DAGCombine should not aggressively fold SEXT(VSETCC(...)) into a wider VSETCC...Owen Anderson
2013-04-23R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune
2013-04-23R600: Add CF_ENDVincent Lejeune
2013-04-23Hexagon: Remove duplicate instructions to handle global/immediate valuesJyotsna Verma
2013-04-23AArch64: remove unnecessary check that RS is validTim Northover
2013-04-22Remove unused DwarfSectionOffsetDirective stringMatt Arsenault
2013-04-22Move C++ code out of the C headers and into either C++ headersEric Christopher
2013-04-22[ms-inline asm] Removed this unnecessary check. In the current implementation,Chad Rosier
2013-04-22[ms-inline asm] Add the OpDecl to the InlineAsmIdentifierInfo struct and in turnChad Rosier
2013-04-22Fix unused variable warning.Chad Rosier
2013-04-2280 columns.Akira Hatanaka
2013-04-22[mips] In performDSPShiftCombine, check that all elements in the vector areAkira Hatanaka
2013-04-22[ms-inline asm] Remove the identifier parsing logic from the AsmParser. This isChad Rosier
2013-04-22[ms-inline asm] Refactor/clean up the SemaLookup interface. No functionalChad Rosier
2013-04-22No really, don't store anything to this since it's unconditionallyEric Christopher
2013-04-22Remove variable store that is never read.Eric Christopher
2013-04-22Fix for 5.5 Parameter Passing --> Stage C:Stepan Dyatkovskiy
2013-04-21Legalize vector truncates by parts rather than just splitting.Jim Grosbach
2013-04-21Passing arguments to varags functions under the SPARC v9 ABI.Jakob Stoklund Olesen
2013-04-21Fix the SETHIimm pattern for 64-bit code.Jakob Stoklund Olesen
2013-04-21ARM: Use ldrd/strd to spill 64-bit pairs when available.Tim Northover
2013-04-20Compile varargs functions for SPARCv9.Jakob Stoklund Olesen
2013-04-20ARM: don't add FrameIndex offset for LDMIA (has no immediate)Tim Northover
2013-04-20AArch64: remove useless commentTim Northover
2013-04-20Remove unused ShouldFoldAtomicFences flag.Tim Northover