llvm - http://llvm.org

Age	Commit message (Collapse)	Author
2013-05-05	[XCore] Remove '-' from back branch asm syntax.	Richard Osborne
	Instead operands are treated as negative immediates where the sign bit is implicit in the instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181151 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04	[XCore] Make use of the target independent global address offset folding.	Richard Osborne
	This let us to remove some custom code that matched constant offsets from globals at instruction selection time as a special addressing mode. No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04	[XCore] The RRegs register class is a superset of GRRegs.	Richard Osborne
	At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17	[XCore] Add missing 2r instructions.	Richard Osborne
	These instructions are not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17	[XCore] Add TSETR instruction.	Richard Osborne
	This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-27	[XCore] Add missing l2rus instructions.	Richard Osborne
	These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25	Add instruction encodings / disassembly support for l4r instructions.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25	Use the correct format in the STW / SETPSC instruction names.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25	Add instruction encodings / disassembly support for l5r instructions.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-23	Add instruction encodings / disassembly support for l6r instructions.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-21	Add instruction encoding / disassembly support for ru6 / lru6 instructions.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20	Add instruction encodings / disassembly support for l2rus instructions.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20	Add instruction encodings / disassembly support for l3r instructions.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20	Add instruction encodings / disassembler support for 2rus instructions.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20	Add instruction encodings / disassembly support 3r instructions.	Richard Osborne
	It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17	Add instruction encodings / disassembly support for l2r instructions.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17	Fix parameter name in prototypes in XCoreDisassembler.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170332 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17	Add instruction encodings / disassembly support for rus instructions.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17	Add instruction encodings / disassembly support for 2r instructions.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17	Update comments to match recommended doxygen style.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170320 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16	Add instruction encodings and disassembly for 1r instructions.	Richard Osborne
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16	Add XCore disassembler.	Richard Osborne
	Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8