diff options
| author | Richard Osborne <richard@xmos.com> | 2013-01-21 20:42:16 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-21 20:42:16 +0000 |
| commit | 9b709f8b3f3fa6e9bfb5007b70e096f6192f3ef8 (patch) | |
| tree | 9ef864c103916ee8ad7fc1e09bc1a770af644a56 /lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | |
| parent | a3458380b97bd732baf84f1bf0d21f215bf99727 (diff) | |
Add instruction encoding / disassembly support for ru6 / lru6 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp')
| -rw-r--r-- | lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index d24d9476cd..e6861bf0f3 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -92,6 +92,9 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); + static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -192,6 +195,13 @@ static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, return MCDisassembler::Success; } +static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + Inst.addOperand(MCOperand::CreateImm(Val)); + Inst.addOperand(MCOperand::CreateImm(0)); + return MCDisassembler::Success; +} + static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { unsigned Combined = fieldFromInstruction(Insn, 6, 5); |