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path: root/lib/Target/X86/X86InstrInfo.cpp
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2007-08-10Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via ↵Christopher Lamb
subregisters when 16-bit LEA is disabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41007 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26Don't pollute the meaning of isUnpredicatedTerminator.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40537 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06isUnpredicatedTerminator should treat conditional branches as unpredicated ↵Evan Cheng
terminator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37960 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-04Refactor X87 instructions. As a side effect, allDale Johannesen
their names are changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37876 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-03Fix for PR 1505 (and 1489). Rewrite X87 registerDale Johannesen
model to include f32 variants. Some factoring improvments forthcoming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37847 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-26Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman
instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman
with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-14Do not treat FP_REG_KILL as terminator in branch analysis (X86).Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37578 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-14Add a target hook to allow loads from constant pools to be rematerialized, ↵Dan Gohman
and an implementation for x86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37576 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-13Handle blocks with 2 unconditional branches in AnalyzeBranch.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-08Add a utility routine to check for unpredicated terminator instruction.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-21BlockHasNoFallThrough() now returns true if block ends with a return ↵Evan Cheng
instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37266 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-18RemoveBranch() and InsertBranch() now returns number of instructions deleted ↵Evan Cheng
/ inserted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37193 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25Relex assertions to account for additional implicit def / use operands.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-24Remove some invalid instructions from this check.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36404 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03Adding more MMX instructions.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35638 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35616 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28Compile CodeGen/X86/lea-3.ll:test2 to:Chris Lattner
_test3: leaq (,%rdi,4), %rax orq %rdi, %rax ret instead of: _test2: movq %rdi, %rax shlq $2, %rax orq %rdi, %rax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35434 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-28Fix a problem building llvm-gcc on amd64-unknown-freebsd6.2, due to theChris Lattner
system assembler not groking legal instructions like "leal (,%esi,8), %ecx". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35393 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-20Two changes:Chris Lattner
1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35204 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-08Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so thatBill Wendling
moves, loads, etc. are recognized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35031 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-26Make LABEL a builtin opcode.Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-01convertToThreeAddress() is now responsible for updating live info as well as ↵Evan Cheng
inserting the new MI's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32097 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-27Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng
of opcode and number of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-16Fix a potential bug: MOVPDI2DI, etc. are not copy instructions.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31794 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-15Properly transfer kill / dead info.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31765 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-13Matches MachineInstr changes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-30fix wonky indentationChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31298 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-28add another target hook for branch folding.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31262 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-21Implement support for branch condition reversal.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31099 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-21Simplify code, no functionality changeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31097 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-21allow insertion of a conditional branch with fall-throughChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31095 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-21update assert messageChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31093 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-20bugfixChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31074 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-20Implement branch analysis/xform hooks required by the branch folding pass.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31065 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-17expose DWARF_LABEL opcode# so the branch folder can update debug info properly.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31024 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-13remove some dead codeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30938 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-28update commentsChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30663 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-08Committing X86-64 support.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-05Fix a long-standing wart in the code generator: two-address instruction loweringChris Lattner
actually *removes* one of the operands, instead of just assigning both operands the same register. This make reasoning about instructions unnecessarily complex, because you need to know if you are before or after register allocation to match up operand #'s with the target description file. Changing this also gets rid of a bunch of hacky code in various places. This patch also includes changes to fold loads into cmp/test instructions in the X86 backend, along with a significant simplification to the X86 spill folding code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30108 91177308-0d34-0410-b5e6-96231b3b80d8
2006-07-25Can't commute shufps. The high / low parts elements come from different vectors.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29275 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-30Commute shufps / shufpd.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28577 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-30Somehow I lost a condition when I was shuffling some code around. Anyway,Evan Cheng
only transform a shufps to pshufd when the first two operands are the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28575 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-30Fix a build breaker.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28574 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-30Oops. PSHUFD is only available with SSE2.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28573 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-30Allow shufps x, x, mask to be converted to pshufd x, mask to save a move.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28565 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-19These can be transformed into lea as well. Not that we use this featureEvan Cheng
currently... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28393 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-11Add MOV16_rm / MOV32_rm and MOV16_mr / MOV32_mr to isLoadFromStackSlot and ↵Evan Cheng
isStoreToStackSlot git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28223 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-08Fixing truncate. Previously we were emitting truncate from r16 to r8 asEvan Cheng
movw. That is we promote the destination operand to r16. So %CH = TRUNC_R16_R8 %BP is emitted as movw %bp, %cx. This is incorrect. If %cl is live, it would be clobbered. Ideally we want to do the opposite, that is emitted it as movb ??, %ch But this is not possible since %bp does not have a r8 sub-register. We are now defining a new register class R16_ which is a subclass of R16 containing only those 16-bit registers that have r8 sub-registers (i.e. AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the value to the R16_ class, followed by a TRUNC_R16_R8. Due to bug 770, the register colaescer is not going to coalesce between R16 and R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it can only be eliminated if we are lucky that source and destination registers are the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28164 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-18Teach the codegen about instructions used for SSE spill code, allowing itChris Lattner
to optimize cases where it has to spill a lot git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27801 91177308-0d34-0410-b5e6-96231b3b80d8
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