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authorEvan Cheng <evan.cheng@apple.com>2007-04-25 07:12:14 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-04-25 07:12:14 +0000
commit1e341729dd003ca33ecea4abf13134f20062c5f8 (patch)
tree4bc71a3892c29b85687c6c6d46531aced64c4e01 /lib/Target/X86/X86InstrInfo.cpp
parent79b3bd395dc3303cde65e18e0524ed2f70268c99 (diff)
Relex assertions to account for additional implicit def / use operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.cpp')
-rw-r--r--lib/Target/X86/X86InstrInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 7a3dfe06da..bd46cda376 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -39,7 +39,7 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
- assert(MI.getNumOperands() == 2 &&
+ assert(MI.getNumOperands() >= 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"invalid register-register move instruction");