diff options
| author | Dan Gohman <gohman@apple.com> | 2007-06-19 01:48:05 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2007-06-19 01:48:05 +0000 |
| commit | 82a87a01723c095176c6940bcc63d3a7c8007b4b (patch) | |
| tree | cb6bdf78002b48d594f2803783ba8c3d361d8a01 /lib/Target/X86/X86InstrInfo.cpp | |
| parent | eaa91b0a1fc68984aae51f3c4b0cf29b38f89dac (diff) | |
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.cpp')
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index c8621ad1b7..0e02ef0be8 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -112,9 +112,20 @@ unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI, } -bool X86InstrInfo::isOtherReMaterializableLoad(MachineInstr *MI) const { +bool X86InstrInfo::isTriviallyReMaterializable(MachineInstr *MI) const { switch (MI->getOpcode()) { default: break; + case X86::FpLD0: + case X86::FpLD1: + case X86::MOV8ri: + case X86::MOV16ri: + case X86::MOV32ri: + case X86::MMX_V_SET0: + case X86::MMX_V_SETALLONES: + case X86::V_SET0: + case X86::V_SETALLONES: + // These instructions are always trivially rematerializable. + return true; case X86::MOV8rm: case X86::MOV16rm: case X86::MOV16_rm: @@ -128,6 +139,7 @@ bool X86InstrInfo::isOtherReMaterializableLoad(MachineInstr *MI) const { case X86::MOVAPDrm: case X86::MMX_MOVD64rm: case X86::MMX_MOVQ64rm: + // Loads from constant pools are trivially rematerializable. return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() && MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() && MI->getOperand(1).getReg() == 0 && |