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path: root/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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2011-10-03ARM assembly parsing and encoding for VMOV immediate.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03ARM parsing/encoding for VCMP/VCMPE.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03ARM assembly parsing and encoding for VMRS/FMSTAT.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy
forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset ↵Owen Anderson
of #-0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19ARM asm parsing should handle pre-indexed writeback w/o immediate.Jim Grosbach
For example, 'ldrb r9, [sp]!' is odd, but valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140035 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Thumb2 assembly parsing and encoding for SUB(immediate).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Thumb2 assembly parsing and encoding for STR.Jim Grosbach
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH and STR(register). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Thumb2 assembly parsing and encoding for STMIA.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Thumb2 assembly parsing and encoding for SMMULL.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Kill some dead code.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139904 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Tidy up a bit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139903 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16Thumb2 assembly parsing and encoding for SMLAL.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14Thumb2 assembly parsing and encoding for MUL.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14Thumb2 assembly parsing and encoding for MSR/MRS.Jim Grosbach
Fix a bug in handling default flags for both ARM and Thumb encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14Thumb2 assembly parsing for MOV in IT block.Jim Grosbach
Select the right 16 vs. 32 bit encoding in an IT block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14ARM fix assembly parser handling of ranges in register lists.Jim Grosbach
Clean up register list handling in general a bit to explicitly check things like all the registers being from the same register class. rdar://8883573 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139707 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13Remove unnecessary scope resolution operator.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139656 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13There's only 16 regs legal in a register list.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139637 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-13Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it ↵Owen Anderson
is always executed unconditionally. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139610 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12Tidy up a bit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-10Thumb2 parsing and encoding for MOV(immediate).Jim Grosbach
Some aliases for MOV(register) also to keep existing T1 tests happy when run in thumbv7 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson
have a predicate operand, unlike conditional branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb2 assembly parsing and encoding for MLA and MLS.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Thumb2 assembly parsing and encoding for LDRD(immediate).Jim Grosbach
Refactor operand handling for STRD as well. Tests for that forthcoming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.Jim Grosbach
Adjust encoding of writeback load/store instructions to better reflect the way the operand types are represented. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Thumb2 assembly parsing and encoding for LDRBT.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Thumb2 assembly parsing and encoding for LDR(register).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Thumb2 parsing and encoding for LDR(immediate).Jim Grosbach
The immediate offset of the non-writeback i8 form (encoding T4) allows negative offsets only. The positive offset form of the encoding is the LDRT instruction. Immediate offsets in the range [0,255] use encoding T3 instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Thumb2 parsing and encoding for LDMIA.Jim Grosbach
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing as match classes are insufficient to handle the context-sensitiveness of the writeback operand's legality for the 16-bit encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07Better diagnostic location information for mnemonic suffices.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139232 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Thumb2 parsing and encoding for CLREX.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06ARM .code directive should always go to the streamer.Jim Grosbach
Even if there's no mode switch performed, the .code directive should still be sent to the output streamer. Otherwise, for example, an output asm stream is not equivalent to the input stream which generated it (a dependency on the input target triple arm vs. thumb is introduced which was not originally there). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Thumb2 parsing and encoding of B instruction.Jim Grosbach
Tweak handling of IT blocks a bit to enable this. The differentiation between B and Bcc needs special sauce. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138952 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01t2Bcc is allowed to have a predicate without a preceding IT instruction.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01Thumb2 assembly parsing and encoding for ADD(immediate).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Thumb2 t2Bcc should encode as t2B when condition is 'always'.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138898 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Remove FIXME. Thumb2 MOV instruction will use separate custom tricks.Jim Grosbach
When we want encoding T3 (the wide encoding), we can explicitly check for that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly handle encodings T1 and T2 when in Thumb2 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138879 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31Tweak Thumb1 ADD encoding selection a bit.Jim Grosbach
When the destination register of an add immediate instruction is explicitly specified, encoding T1 is preferred, else encoding T2 is preferred. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29Thumb2 parsing and encoding for IT blocks.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138773 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29Improve handling of #-0 offsets for many more pre-indexed addressing modes.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
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