diff options
| author | Jim Grosbach <grosbach@apple.com> | 2011-08-31 17:07:33 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-08-31 17:07:33 +0000 |
| commit | 0f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77 (patch) | |
| tree | 4f390cc6b292ef6fad5e5a78d78385b4c4d5b2fb /lib/Target/ARM/AsmParser/ARMAsmParser.cpp | |
| parent | 61545829832ba0375249c42c84843d0b62c8f55f (diff) | |
Tweak Thumb1 ADD encoding selection a bit.
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138862 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index ab0ff87eae..67176ad5a3 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -3473,8 +3473,11 @@ processInstruction(MCInst &Inst, } break; case ARM::tADDi8: - // If the immediate is in the range 0-7, we really wanted tADDi3. - if (Inst.getOperand(3).getImm() < 8) + // If the immediate is in the range 0-7, we want tADDi3 iff Rd was + // explicitly specified. From the ARM ARM: "Encoding T1 is preferred + // to encoding T2 if <Rd> is specified and encoding T2 is preferred + // to encoding T1 if <Rd> is omitted." + if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) Inst.setOpcode(ARM::tADDi3); break; case ARM::tBcc: |