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path: root/lib/Target/ARM/ARMMCCodeEmitter.cpp
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2010-12-09Fix Thumb2 fixups for ldr.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09The BLX instruction is encoded differently than the BL, because why not? InBill Wendling
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0' always. Going through the BL fixup encoding was trashing the "bit 0 is '0'" invariant. Attempt to get the encoding at slightly more correct with this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121336 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09Fix Thumb2 BCC encoding and fixups.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121329 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08Support the "target" encodings for the CB[N]Z instructions.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121308 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08Add support for loading from a constant pool.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08VLDR fixups need special handling under Thumb. While the encoding is the same,Owen Anderson
the order of the bytes in the data stream is flipped around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07Fix a warning about a variable which is only used in an assertion.Matt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07Binary encoding for ARM tLDRspi and tSTRspi.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson
gazillion places that need to know about it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03Encode the 32-bit wide Thumb (and Thumb2) instructions with the high orderJim Grosbach
halfword being emitted to the stream first. rdar://8728174 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03The tLDR instruction wasn't encoded properly:Bill Wendling
<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>> Notice that the "reg" here is 0, which is an invalid register. Put a check in the code for this to prevent crashing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120766 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-02Add support for binary encoding of ARM 'adr' instructions referencing constantJim Grosbach
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01Add a post encoder method to the VFP instructions to convert them to the Thumb2Bill Wendling
encoding if we're in that mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01Use the correct fixup type for ARM VLDR*Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120604 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADRJim Grosbach
instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01Add correct encodings for STRD and LDRD, including fixup support. ↵Owen Anderson
Additionally, update these to unified syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-0110 bits, not 12.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120584 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30Fix typo.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120499 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30Thanks to JimG for catching this!Jason W Kim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same asBill Wendling
t_addrmode_s4, but with a different scaling factor. * Encode the Thumb1 load and store instructions. This involved a bit of refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and were removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120482 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. ↵Owen Anderson
This allows the Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free. It also allows us to fold away at least one codegen-only pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30Fix handling of ARM negative pc-relative fixups for loads and stores.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30Add encoding support for Thumb2 PLD and PLI instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120449 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almostBill Wendling
certainly be made more generic. But it does allow us to parse something like: ldr r3, [r2, r4] correctly in Thumb mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30Correct Thumb2 encodings for a much wider range of loads and stores.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30Fix the encoding of VLD4-dup alignment.Bob Wilson
The only reasonable way I could find to do this is to provide an alternate version of the addrmode6 operand with a different encoding function. Use it for all the VLD-dup instructions for the sake of consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29Provide Thumb2 encodings for basic loads and stores.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-22Fix a compiler warning about Kind being used uninitializedDuncan Sands
when assertions are disabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119962 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19Minor cleanups to a few llvm_unreachable() calls.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19An 'unreachable' shouldn't have a '0 &&' prefix.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ↵Jason W Kim
.o path now works for ARM. Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired. Existing tests cover this update. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Add binary emission stuff for VLDM/VSTM. This reuses theBill Wendling
"getRegisterListOpValue" logic. If the registers are double or single precision, the value returned is suitable for VLDM/VSTM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119180 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner
Switch the ARM backend to use 'let' instead of 'set' with this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12First stab at providing correct Thumb2 encodings, start with adc.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11Start of support for binary emit of 16-it Thumb instructions.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11Fill out support for Thumb2 encodings of NEON instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11Add support for Thumb2 encodings of NEON data processing instructions, using ↵Owen Anderson
the new PostEncoderMethod infrastructure. More tests to come. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11Encoding of destination fixup for ARM branch and conditional branchJim Grosbach
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11Encoding for ARM LDRSH_POST.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11ARM STRH encoding information.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10ARM LDM encoding for the mode (ia, ib, da, db) operand.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09For ARM load/store instructions, encode [reg+reg] with no shifter immediate asJim Grosbach
a left shift by zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Add encoder method for ARM load/store shifted register offset operands.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Add support for a few simple fixups to the ARM Darwin asm backend. This allowsJim Grosbach
constant pool references and global variable refernces to resolve properly for object file generation. For example, int x; void foo(unsigned a, unsigned *p) { p[a] = x; } can now be successfully compiled directly to an (ARM mode) object file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Revert r118457 and r118458. These won't hold for GPRs.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Get the register and count from the register list operands.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04Add ARM fixup info for load/store label references. Probably will need a bit ofJim Grosbach
tweaking when we start using it for object file emission or JIT, but it's a start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118221 91177308-0d34-0410-b5e6-96231b3b80d8
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