diff options
| author | Bill Wendling <isanbard@gmail.com> | 2010-11-30 07:44:32 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-11-30 07:44:32 +0000 |
| commit | ef4a68badbde372faac9ca47efb9001def57a43d (patch) | |
| tree | 2365abf528a38f22d1d78168fd89899a6034ae6a /lib/Target/ARM/ARMMCCodeEmitter.cpp | |
| parent | 3f8e61789100ee411d0bfe00fb90df60eaed65f5 (diff) | |
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMMCCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMMCCodeEmitter.cpp | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index a9f8133af0..a2829c9f28 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -136,6 +136,10 @@ public: uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const; + /// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands. + uint32_t getAddrModeS4OpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl<MCFixup> &Fixups) const; + /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const; @@ -540,6 +544,26 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); } +/// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands. +uint32_t ARMMCCodeEmitter:: +getAddrModeS4OpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl<MCFixup> &Fixups) const { + // [Rn, Rm] + // {5-3} = Rm + // {2-0} = Rn + // + // [Rn, #imm] + // {7-3} = imm5 + // {2-0} = Rn + const MCOperand &MO = MI.getOperand(OpIdx); + const MCOperand &MO1 = MI.getOperand(OpIdx + 1); + const MCOperand &MO2 = MI.getOperand(OpIdx + 2); + unsigned Rn = getARMRegisterNumbering(MO.getReg()); + unsigned Imm5 = MO1.getImm(); + unsigned Rm = getARMRegisterNumbering(MO2.getReg()); + return (Rm << 3) | (Imm5 << 3) | Rn; +} + /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand. uint32_t ARMMCCodeEmitter:: getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, |