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path: root/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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2009-06-15Typo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73422 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15Do not form ldrd / strd if the two dests / srcs are the same. Code clean up.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73413 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15Silence a warning.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73406 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15Part 1.Evan Cheng
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-13Add a ARM specific pre-allocation pass that re-schedule loads / stores fromEvan Cheng
consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order ↵Evan Cheng
change no longer make sense after the coalescing changes we have made since then. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05When merging multiple load / store instructions. Use the DebugLoc of the ↵Evan Cheng
first one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72952 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05Code clean up: return vector by reference rather than by value. No ↵Evan Cheng
functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72950 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04Re-apply 72756 with fixes. One of those was introduced by we changed ↵Evan Cheng
MachineInstrBuilder::addReg() interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72826 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03Temporarily revert 72756 for now.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72757 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03Fold preceding / trailing base inc / dec into the single load / store as well.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-13Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling
booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13Remove refs to non-DebugLoc versions of BuildMI from ARM.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64429 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-03Switch the MachineOperand accessors back to the short names likeDan Gohman
isReg, etc., from isRegister, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04Tidy up several unbeseeming casts from pointer to intptr_t.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55779 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-11rename MachineInstr::setInstrDescriptor -> setDescChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45871 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner
Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner
that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-30Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner
Likewise setImmedValue -> setImm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29Remove attribution from file headers, per discussion on llvmdev.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-19Avoid referencing deleted instruction.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42153 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-10Remove clobbersPred. Add an OptionalDefOperand to instructions which have ↵Evan Cheng
the 's' bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38501 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05Reflects the chanegs made to PredicateOperand.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37898 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-29Add missing const qualifiers.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37342 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-15Add PredicateOperand to all ARM instructions that have the condition field.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03Drop 'const'Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36662 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-02Use 'static const char' instead of 'static const int'.Devang Patel
Due to darwin gcc bug, one version of darwin linker coalesces static const int, which defauts PassID based pass identification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01Do not use typeinfo to identify pass in pass manager.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36632 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-26Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36483 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-26findRegisterUseOperand() changed.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35366 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-08Bug fix. Not advancing the register scavenger iterator correctly.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35020 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-07Only safe to use a call-clobbered or spilled callee-saved register as ↵Evan Cheng
scratch register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35010 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-07Fix some brittle code. Watch out for cases where register scavenger is ↵Evan Cheng
pointing to deleted instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34998 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-06Make load / store optimizer use register scavenger.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34986 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-06Code clean up. Prepare to use register scavenger.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34976 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-19ARM backend contribution from Apple.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
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