Add PredicateOperand to all ARM instructions that have the condition field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 60 insertions, 36 deletions

diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 5d45568f4d..7977555b0e 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -66,8 +66,8 @@ namespace {
 
     SmallVector<MachineBasicBlock::iterator, 4>
     MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
-                 int Opcode, unsigned Size, unsigned Scratch,
-                 MemOpQueue &MemOps);
+                 int Opcode, unsigned Size, ARMCC::CondCodes Pred,
+                 unsigned Scratch, MemOpQueue &MemOps);
 
     void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
     bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
@@ -112,7 +112,7 @@ static int getLoadStoreMultipleOpcode(int Opcode) {
 /// It returns true if the transformation is done. 
 static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                      int Offset, unsigned Base, bool BaseKill, int Opcode,
-                     unsigned Scratch,
+                     ARMCC::CondCodes Pred, unsigned Scratch,
                      SmallVector<std::pair<unsigned, bool>, 8> &Regs,
                      const TargetInstrInfo *TII) {
   // Only a single register to load / store. Don't bother.
@@ -156,7 +156,7 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
       return false;  // Probably not worth it then.
 
     BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase)
-      .addReg(Base, false, false, BaseKill).addImm(ImmedOffset);
+      .addReg(Base, false, false, BaseKill).addImm(ImmedOffset).addImm(Pred);
     Base = NewBase;
     BaseKill = true;  // New base is always killed right its use.
   }
@@ -166,9 +166,10 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
   Opcode = getLoadStoreMultipleOpcode(Opcode);
   MachineInstrBuilder MIB = (isAM4)
     ? BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
-        .addImm(ARM_AM::getAM4ModeImm(Mode))
+        .addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred)
     : BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
-        .addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs));
+        .addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
+        .addImm(Pred);
   for (unsigned i = 0; i != NumRegs; ++i)
     MIB = MIB.addReg(Regs[i].first, isDef, false, Regs[i].second);
 
@@ -180,9 +181,9 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
 SmallVector<MachineBasicBlock::iterator, 4>
 ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
                               unsigned Base, int Opcode, unsigned Size,
-                              unsigned Scratch, MemOpQueue &MemOps) {
+                              ARMCC::CondCodes Pred, unsigned Scratch,
+                              MemOpQueue &MemOps) {
   SmallVector<MachineBasicBlock::iterator, 4> Merges;
-  SmallVector<std::pair<unsigned,bool>, 8> Regs;
   bool isAM4 = Opcode == ARM::LDR || Opcode == ARM::STR;
   int Offset = MemOps[SIndex].Offset;
   int SOffset = Offset;
@@ -191,6 +192,8 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
   unsigned PReg = MemOps[SIndex].MBBI->getOperand(0).getReg();
   unsigned PRegNum = ARMRegisterInfo::getRegisterNumbering(PReg);
   bool isKill = MemOps[SIndex].MBBI->getOperand(0).isKill();
+
+  SmallVector<std::pair<unsigned,bool>, 8> Regs;
   Regs.push_back(std::make_pair(PReg, isKill));
   for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) {
     int NewOffset = MemOps[i].Offset;
@@ -206,7 +209,8 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
       PRegNum = RegNum;
     } else {
       // Can't merge this in. Try merge the earlier ones first.
-      if (mergeOps(MBB, ++Loc, SOffset, Base, false, Opcode,Scratch,Regs,TII)) {
+      if (mergeOps(MBB, ++Loc, SOffset, Base, false, Opcode, Pred, Scratch,
+                   Regs, TII)) {
         Merges.push_back(prior(Loc));
         for (unsigned j = SIndex; j < i; ++j) {
           MBB.erase(MemOps[j].MBBI);
@@ -214,7 +218,7 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
         }
       }
       SmallVector<MachineBasicBlock::iterator, 4> Merges2 =
-        MergeLDR_STR(MBB, i, Base, Opcode, Size, Scratch, MemOps);
+        MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, Scratch, MemOps);
       Merges.append(Merges2.begin(), Merges2.end());
       return Merges;
     }
@@ -226,7 +230,8 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
   }
 
   bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1;
-  if (mergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode,Scratch,Regs, TII)) {
+  if (mergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Pred, Scratch,
+               Regs, TII)) {
     Merges.push_back(prior(Loc));
     for (unsigned i = SIndex, e = MemOps.size(); i != e; ++i) {
       MBB.erase(MemOps[i].MBBI);
@@ -237,20 +242,29 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
   return Merges;
 }
 
+/// getInstrPredicate - If instruction is predicated, returns its predicate
+/// condition, otherwise returns AL.
+static ARMCC::CondCodes getInstrPredicate(MachineInstr *MI) {
+  MachineOperand *PredMO = MI->findFirstPredOperand();
+  return PredMO ? (ARMCC::CondCodes)PredMO->getImmedValue() : ARMCC::AL;
+}
+
 static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
-                                       unsigned Bytes) {
+                                       unsigned Bytes, ARMCC::CondCodes Pred) {
   return (MI && MI->getOpcode() == ARM::SUBri &&
           MI->getOperand(0).getReg() == Base &&
           MI->getOperand(1).getReg() == Base &&
-          ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes);
+          ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes &&
+          getInstrPredicate(MI) == Pred);
 }
 
 static inline bool isMatchingIncrement(MachineInstr *MI, unsigned Base,
-                                       unsigned Bytes) {
+                                       unsigned Bytes, ARMCC::CondCodes Pred) {
   return (MI && MI->getOpcode() == ARM::ADDri &&
           MI->getOperand(0).getReg() == Base &&
           MI->getOperand(1).getReg() == Base &&
-          ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes);
+          ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes &&
+          getInstrPredicate(MI) == Pred);
 }
 
 static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
@@ -266,7 +280,7 @@ static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
     return 8;
   case ARM::LDM:
   case ARM::STM:
-    return (MI->getNumOperands() - 2) * 4;
+    return (MI->getNumOperands() - 3) * 4;
   case ARM::FLDMS:
   case ARM::FSTMS:
   case ARM::FLDMD:
@@ -292,6 +306,7 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
   MachineInstr *MI = MBBI;
   unsigned Base = MI->getOperand(0).getReg();
   unsigned Bytes = getLSMultipleTransferSize(MI);
+  ARMCC::CondCodes Pred = getInstrPredicate(MI);
   int Opcode = MI->getOpcode();
   bool isAM4 = Opcode == ARM::LDM || Opcode == ARM::STM;
 
@@ -301,7 +316,7 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
 
     // Can't use the updating AM4 sub-mode if the base register is also a dest
     // register. e.g. ldmdb r0!, {r0, r1, r2}. The behavior is undefined.
-    for (unsigned i = 2, e = MI->getNumOperands(); i != e; ++i) {
+    for (unsigned i = 3, e = MI->getNumOperands(); i != e; ++i) {
       if (MI->getOperand(i).getReg() == Base)
         return false;
     }
@@ -310,12 +325,12 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
     if (MBBI != MBB.begin()) {
       MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
       if (Mode == ARM_AM::ia &&
-          isMatchingDecrement(PrevMBBI, Base, Bytes)) {
+          isMatchingDecrement(PrevMBBI, Base, Bytes, Pred)) {
         MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::db, true));
         MBB.erase(PrevMBBI);
         return true;
       } else if (Mode == ARM_AM::ib &&
-                 isMatchingDecrement(PrevMBBI, Base, Bytes)) {
+                 isMatchingDecrement(PrevMBBI, Base, Bytes, Pred)) {
         MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::da, true));
         MBB.erase(PrevMBBI);
         return true;
@@ -325,12 +340,12 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
     if (MBBI != MBB.end()) {
       MachineBasicBlock::iterator NextMBBI = next(MBBI);
       if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
-          isMatchingIncrement(NextMBBI, Base, Bytes)) {
+          isMatchingIncrement(NextMBBI, Base, Bytes, Pred)) {
         MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
         MBB.erase(NextMBBI);
         return true;
       } else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
-                 isMatchingDecrement(NextMBBI, Base, Bytes)) {
+                 isMatchingDecrement(NextMBBI, Base, Bytes, Pred)) {
         MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
         MBB.erase(NextMBBI);
         return true;
@@ -346,7 +361,7 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
     if (MBBI != MBB.begin()) {
       MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
       if (Mode == ARM_AM::ia &&
-          isMatchingDecrement(PrevMBBI, Base, Bytes)) {
+          isMatchingDecrement(PrevMBBI, Base, Bytes, Pred)) {
         MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::db, true, Offset));
         MBB.erase(PrevMBBI);
         return true;
@@ -356,7 +371,7 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
     if (MBBI != MBB.end()) {
       MachineBasicBlock::iterator NextMBBI = next(MBBI);
       if (Mode == ARM_AM::ia &&
-          isMatchingIncrement(NextMBBI, Base, Bytes)) {
+          isMatchingIncrement(NextMBBI, Base, Bytes, Pred)) {
         MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::ia, true, Offset));
         MBB.erase(NextMBBI);
       }
@@ -414,16 +429,17 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
   if (isLd && MI->getOperand(0).getReg() == Base)
     return false;
 
+  ARMCC::CondCodes Pred = getInstrPredicate(MI);
   bool DoMerge = false;
   ARM_AM::AddrOpc AddSub = ARM_AM::add;
   unsigned NewOpc = 0;
   if (MBBI != MBB.begin()) {
     MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
-    if (isMatchingDecrement(PrevMBBI, Base, Bytes)) {
+    if (isMatchingDecrement(PrevMBBI, Base, Bytes, Pred)) {
       DoMerge = true;
       AddSub = ARM_AM::sub;
       NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
-    } else if (isAM2 && isMatchingIncrement(PrevMBBI, Base, Bytes)) {
+    } else if (isAM2 && isMatchingIncrement(PrevMBBI, Base, Bytes, Pred)) {
       DoMerge = true;
       NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
     }
@@ -433,11 +449,11 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
 
   if (!DoMerge && MBBI != MBB.end()) {
     MachineBasicBlock::iterator NextMBBI = next(MBBI);
-    if (isAM2 && isMatchingDecrement(NextMBBI, Base, Bytes)) {
+    if (isAM2 && isMatchingDecrement(NextMBBI, Base, Bytes, Pred)) {
       DoMerge = true;
       AddSub = ARM_AM::sub;
       NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
-    } else if (isMatchingIncrement(NextMBBI, Base, Bytes)) {
+    } else if (isMatchingIncrement(NextMBBI, Base, Bytes, Pred)) {
       DoMerge = true;
       NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
     }
@@ -457,20 +473,22 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
       // LDR_PRE, LDR_POST;
       BuildMI(MBB, MBBI, TII->get(NewOpc), MI->getOperand(0).getReg())
         .addReg(Base, true)
-        .addReg(Base).addReg(0).addImm(Offset);
+        .addReg(Base).addReg(0).addImm(Offset).addImm(Pred);
     else
+      // FLDMS, FLDMD
       BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base, false, false, BaseKill)
-        .addImm(Offset).addReg(MI->getOperand(0).getReg(), true);
+        .addImm(Offset).addImm(Pred).addReg(MI->getOperand(0).getReg(), true);
   } else {
     MachineOperand &MO = MI->getOperand(0);
     if (isAM2)
       // STR_PRE, STR_POST;
       BuildMI(MBB, MBBI, TII->get(NewOpc), Base)
         .addReg(MO.getReg(), false, false, MO.isKill())
-        .addReg(Base).addReg(0).addImm(Offset);
+        .addReg(Base).addReg(0).addImm(Offset).addImm(Pred);
     else
-      BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base)
-        .addImm(Offset).addReg(MO.getReg(), false, false, MO.isKill());
+      // FSTMS, FSTMD
+      BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base).addImm(Offset)
+        .addImm(Pred).addReg(MO.getReg(), false, false, MO.isKill());
   }
   MBB.erase(MBBI);
 
@@ -521,6 +539,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
   unsigned CurrBase = 0;
   int CurrOpc = -1;
   unsigned CurrSize = 0;
+  ARMCC::CondCodes CurrPred = ARMCC::AL;
   unsigned Position = 0;
 
   RS->enterBasicBlock(&MBB);
@@ -536,8 +555,9 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
       bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
       unsigned Size = getLSMultipleTransferSize(MBBI);
       unsigned Base = MBBI->getOperand(1).getReg();
-      unsigned OffIdx = MBBI->getNumOperands()-1;
-      unsigned OffField = MBBI->getOperand(OffIdx).getImm();
+      ARMCC::CondCodes Pred = getInstrPredicate(MBBI);
+      const TargetInstrDescriptor *TID = MBBI->getInstrDescriptor();
+      unsigned OffField = MBBI->getOperand(TID->numOperands-2).getImm();
       int Offset = isAM2
         ? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
       if (isAM2) {
@@ -562,6 +582,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
         CurrBase = Base;
         CurrOpc  = Opcode;
         CurrSize = Size;
+        CurrPred = Pred;
         MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
         NumMemOps++;
         Advance = true;
@@ -571,7 +592,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
           Advance = true;
         }
 
-        if (CurrOpc == Opcode && CurrBase == Base) {
+        if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {
           // Continue adding to the queue.
           if (Offset > MemOps.back().Offset) {
             MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
@@ -617,7 +638,8 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
 
         // Merge ops.
         SmallVector<MachineBasicBlock::iterator,4> MBBII =
-          MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize, Scratch, MemOps);
+          MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize, CurrPred,
+                       Scratch, MemOps);
 
         // Try folding preceeding/trailing base inc/dec into the generated
         // LDM/STM ops.
@@ -639,6 +661,8 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
 
       CurrBase = 0;
       CurrOpc = -1;
+      CurrSize = 0;
+      CurrPred = ARMCC::AL;
       if (NumMemOps) {
         MemOps.clear();
         NumMemOps = 0;