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path: root/lib/Target/ARM/ARMInstrFormats.td
AgeCommit message (Expand)Author
2008-11-13Handle the rest of pseudo instructions.Evan Cheng
2008-11-13Fix pre- and post-indexed load / store encoding bugs.Evan Cheng
2008-11-12Consolidate formats; fix FCMPED etc. encodings.Evan Cheng
2008-11-12Fix VFP conversion instruction encodings.Evan Cheng
2008-11-11Fix FMDRR encoding.Evan Cheng
2008-11-11Encode VFP load / store instructions.Evan Cheng
2008-11-11Encode VFP conversion instructions.Evan Cheng
2008-11-11Encode VFP arithmetic instructions.Evan Cheng
2008-11-07Jump table JIT support. Work in progress.Evan Cheng
2008-11-07Encode misc arithmetic instructions.Evan Cheng
2008-11-06Encode extend instructions; more clean up.Evan Cheng
2008-11-06- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.Evan Cheng
2008-11-06Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 enc...Evan Cheng
2008-11-06Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.Evan Cheng
2008-11-06Fix encoding of multiple instructions with 3 src operands; also handle smmul,...Evan Cheng
2008-11-05Encode pic load / store instructions; fix some encoding bugs.Evan Cheng
2008-11-05Restructure ARM code emitter to use instruction formats instead of addressing...Evan Cheng
2008-11-04LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.Evan Cheng
2008-11-03Add binary encoding support for multiply instructions. Some blanks left to fi...Jim Grosbach
2008-10-14Update ARM Insn encoding to get endian-ness to match the documentation (31-0 ...Jim Grosbach
2008-09-17Fix addrmode1 instruction encodings; fix bx_ret encoding.Evan Cheng
2008-09-17Specify instruction encoding using range list to avoid endianess issues.Evan Cheng
2008-09-13Revert 56176. All those instruction formats are still needed.Evan Cheng
2008-09-12Eliminate unnecessary instruction formats.Evan Cheng
2008-09-12Addrmode 1 S bit can be dynamically set. Look for CPSR def.Evan Cheng
2008-09-01Control flow instruction encodings.Evan Cheng
2008-09-01ldm / stm instruction encodings.Evan Cheng
2008-09-01AXI2 and AXI3 instruction encodings.Evan Cheng
2008-09-01Reorganize instruction formats again; AXI1 encoding.Evan Cheng
2008-09-01addrmode3 instruction encodings.Evan Cheng
2008-09-01Reorganize some instruction format definitions. No functionality change.Evan Cheng
2008-09-01Rest of addrmode2 instruction encodings.Evan Cheng
2008-08-31Addr2 word / byte load encodings.Evan Cheng
2008-08-31Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.Evan Cheng
2008-08-29addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 e...Evan Cheng
2008-08-29More refactoring.Evan Cheng
2008-08-28Refactor ARM instruction format definitions into a separate file. No function...Evan Cheng
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