llvm - http://llvm.org

Age	Commit message (Expand)	Author
2010-07-08	Changes to ARM tail calls, mostly cosmetic.	Dale Johannesen
2010-07-07	Split the SDValue out of OutputArg so that SelectionDAG-independent	Dan Gohman
2010-07-07	Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where	Jim Grosbach
2010-07-06	By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather	Jim Grosbach
2010-07-06	Propagate debug loc.	Devang Patel
2010-07-06	Reapply r107655 with fixes; insert the pseudo instruction into	Dan Gohman
2010-07-06	Revert r107655.	Dan Gohman
2010-07-06	Fix a bunch of custom-inserter functions to handle the case where	Dan Gohman
2010-07-03	Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill sl...	Evan Cheng
2010-07-01	ARM function alignments were off by a power of two. svn 83242 changed	Bob Wilson
2010-06-29	Remove initialized but otherwise unused variables.	Duncan Sands
2010-06-26	Followup to r106770: actually generate SXTB and SXTH for sign-extensions.	Eli Friedman
2010-06-26	It's now possible to run code placement pass for ARM.	Evan Cheng
2010-06-25	Change if-conversion block size limit checks to add some flexibility.	Evan Cheng
2010-06-25	The hasMemory argument is irrelevant to how the argument	Dale Johannesen
2010-06-25	Reduce indentation.	Bob Wilson
2010-06-23	Do not do tail calls to external symbols. If the	Dale Johannesen
2010-06-23	When using libcall expansions for the atomic intrinsics, the explicit	Jim Grosbach
2010-06-21	sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM.	Bob Wilson
2010-06-19	Fix error message to match function name.	Bob Wilson
2010-06-19	Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emi...	Evan Cheng
2010-06-18	back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)	Jim Grosbach
2010-06-18	Enable Expand handling of atomics for subtargets that can't do them inline.	Jim Grosbach
2010-06-18	Enable tail calls on ARM by default, with some	Dale Johannesen
2010-06-18	Last round of changes for ARM tail calls.	Dale Johannesen
2010-06-18	Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86	Jakob Stoklund Olesen
2010-06-17	Thumb1 and any pre-v6 ARM target should use the libcall expansion of	Jim Grosbach
2010-06-17	simplify code a bit and add a more explanatory assert for cases that	Jim Grosbach
2010-06-16	format and 80-column cleanup	Jim Grosbach
2010-06-16	Remove the hidden "neon-reg-sequence" option. The reg sequences are working	Bob Wilson
2010-06-16	Make post-ra scheduling, anti-dep breaking, and register scavenger (conservat...	Evan Cheng
2010-06-15	Next round of tail call changes. Register used in a tail	Dale Johannesen
2010-06-15	Add basic support for NEON modified immediates besides VMOV.	Bob Wilson
2010-06-14	Rename functions referring to VMOV immediates to refer to NEON "modified	Bob Wilson
2010-06-11	Add a missing bitcast. This code used to only handle conversions between	Bob Wilson
2010-06-11	Add instruction encoding for the Neon VMOV immediate instruction. This changes	Bob Wilson
2010-06-07	Further changes for Neon vector shuffles:	Bob Wilson
2010-06-05	Improvements to tail call code. No functional effect	Dale Johannesen
2010-06-04	More thoroughly disable tails calls by default.	Dale Johannesen
2010-06-04	For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and	Bob Wilson
2010-06-03	Early implementation of tail call for ARM.	Dale Johannesen
2010-06-02	Clean up 80 column violations. No functional change.	Jim Grosbach
2010-05-28	Schedule high latency instructions for latency reduction even if they are not...	Evan Cheng
2010-05-27	Update the saved stack pointer in the sjlj function context following either	Jim Grosbach
2010-05-27	back out 104862/104869. Can reuse stacksave after all. Very cool.	Jim Grosbach
2010-05-27	add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH	Jim Grosbach
2010-05-26	Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in	Jim Grosbach
2010-05-25	Clean up indentation.	Bob Wilson
2010-05-24	LR is in GPR, not tGPR even in Thumb1 mode.	Evan Cheng
2010-05-23	VDUP doesn't support vectors with 64-bit elements.	Bob Wilson