aboutsummaryrefslogtreecommitdiff
path: root/lib/Target
AgeCommit message (Expand)Author
2013-03-27Use the PPC no-r0 class on the TOC LD pseudosHal Finkel
2013-03-27Apply the no-r0 register class to the PPC SELECT_CC_I[4|8] pseudosHal Finkel
2013-03-27Apply the no-r0 class to PPC TOC ADDI[S] pseudo instructionsHal Finkel
2013-03-27Remove the link register from the GPR classes on PowerPC.Bill Schmidt
2013-03-27Don't spill PPC VRSAVE on non-Darwin (even in SjLj)Hal Finkel
2013-03-26Add XTEST codegen supportMichael Liao
2013-03-26Add HLE target featureMichael Liao
2013-03-26Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen
2013-03-26Restore real bit lengths on PPC register numbersHal Finkel
2013-03-26PPC: Use HWEncoding and TRI->getEncodingValueHal Finkel
2013-03-26R600/SIMCCodeEmitter.cpp: Prune a couple of unused members, STI and Ctx. [-Wu...NAKAMURA Takumi
2013-03-26Use multiple virtual registers in PPC CR spillingHal Finkel
2013-03-26Update PPCRegisterInfo's use of virtual registers to be SSAHal Finkel
2013-03-26Annotate the remaining x86 instructions with SchedRW lists.Jakob Stoklund Olesen
2013-03-26Annotate x87 and mmx instructions with SchedRW lists.Jakob Stoklund Olesen
2013-03-26Annotate control instructions with SchedRW lists.Jakob Stoklund Olesen
2013-03-26Annotate the rest of X86InstrInfo.td with SchedRW lists.Jakob Stoklund Olesen
2013-03-26Add PREFETCHW codegen supportMichael Liao
2013-03-26Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.Jyotsna Verma
2013-03-26Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/...Jyotsna Verma
2013-03-26Revert ARM Scheduler Model: Add resources instructions, map resourcesArnold Schwaighofer
2013-03-26Remove default case from fully covered switch.Benjamin Kramer
2013-03-26R600/SI: improve post ISel foldingChristian Konig
2013-03-26R600/SI: improve vector interpolationChristian Konig
2013-03-26R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLEChristian Konig
2013-03-26R600/SI: switch back to RegPressure schedulingChristian Konig
2013-03-26R600/SI: mark most intrinsics as readnone v2Christian Konig
2013-03-26R600/SI: replace WQM intrinsicChristian Konig
2013-03-26R600/SI: fix ELSE pseudo op handlingChristian Konig
2013-03-26Patch by Gordon Keiser!Joe Abbey
2013-03-26PowerPC: Mark patterns as isCodeGenOnly.Ulrich Weigand
2013-03-26PowerPC: Simplify handling of fixups.Ulrich Weigand
2013-03-26PowerPC: Simplify FADD in round-to-zero mode.Ulrich Weigand
2013-03-26PowerPC: Remove LDrs pattern.Ulrich Weigand
2013-03-26PowerPC: Remove ADDIL patterns.Ulrich Weigand
2013-03-26PowerPC: Use CCBITRC operand for ISEL patterns.Ulrich Weigand
2013-03-26PowerPC: Simplify BLR pattern.Ulrich Weigand
2013-03-26PowerPC: Move some 64-bit branch patterns.Ulrich Weigand
2013-03-26R600: fix DenseMap with pointer key iteration in the structurizerChristian Konig
2013-03-26ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer
2013-03-26ARM Scheduler Model: Partial implementation of the new machine scheduler modelArnold Schwaighofer
2013-03-25Revise alignment checking/calculation on 256-bit unaligned memory accessMichael Liao
2013-03-25Add a scheduling model for Intel Sandy Bridge microarchitecture.Jakob Stoklund Olesen
2013-03-25Remove IIC_DEFAULT from X86Schedule.tdJakob Stoklund Olesen
2013-03-25Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen
2013-03-25Annotate shifts and rotates with SchedRW lists.Jakob Stoklund Olesen
2013-03-25X86DisassemblerDecoder.c: Make this C89-compliant.NAKAMURA Takumi
2013-03-25Whitespace.NAKAMURA Takumi
2013-03-25Fix comment.Akira Hatanaka
2013-03-25Use direct types in PowerPC instruction patterns.Ulrich Weigand
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-12-29 20:08:31 +0000