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shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.
Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.
Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.
These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57662 91177308-0d34-0410-b5e6-96231b3b80d8
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because it declares a std::vector<MachineMove>, and strict
concept checking requires the definition of MachineMove to be
available.
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computation. A def of a register doesn't necessarily kill
live super-registers.
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with other debug messages.
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i.e. conditions that cannot be checked with a single instruction. For example,
SETONE and SETUEQ on x86.
- Teach legalizer to implement *illegal* setcc as a and / or of a number of
legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is
implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ.
- Move x86 target over.
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- Move the EH landing-pad code and adjust it so that it works
with FastISel as well as with SDISel.
- Add FastISel support for @llvm.eh.exception and
@llvm.eh.selector.
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instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.
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LegalizeSetCCOperands are leglized. Patch by Richard Pennington.
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for a copy instruction. PR2775.
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null. This assumes that any target that does not have AsmInfo, does not
support "LocAndDot".
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NULL, but just hide some debug output then.
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parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
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valid comments in inline assembly.
gcc.target/i386/20011009-1.c
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and APFloat::convertToInteger. Restore return value to
IEEE754. Adjust all users accordingly.
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make it clearer what the function does. No functional
change.
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thus aligning the label.
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registers that alias its inputs.
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instead.
So now: -fast-isel or -fast-isel=true enable fast-isel, and
-fast-isel=false disables it. Fast-isel is also on by default
with -fast, and off by default otherwise.
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for things like null pointers, which at this level aren't
different from regular integer constants.
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test/Codegen/Generic/i128-addsub.ll on x86
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2006-01-23-UnionInit on x86-64 when inlining is not enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57223 91177308-0d34-0410-b5e6-96231b3b80d8
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ENABLE_EXPENSIVE_CHECKS for finding this.
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patch by Mikael Lepisto!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57077 91177308-0d34-0410-b5e6-96231b3b80d8
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for llvmc2 incomplete.
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expand to multiple basic blocks, in which case fast-isel
needs to informed of which block to use as it resumes
inserting instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57040 91177308-0d34-0410-b5e6-96231b3b80d8
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was setting kill flags on tied uses in two-address instructions.
The kill flags were causing the allocator to think it could
allocate the use and its tied def in different registers.
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incidentally making the case where the memop is a
pointer deref work. Fix cmp-and-swap regression.
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isReg, etc., from isRegister, etc.
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than the type an i1 is promoted to (eg: i8). Account
for this. Noticed by Tilmann Scheller on CellSPU; he
will hopefully take care of fixing this in LegalizeDAG
and adding a testcase!
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It turns out that this is a fairly common operation,
and it's easy enough to handle.
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sequences like this:
sete %al
testb %al, %al
jne LBB11_1
with this:
je LBB11_1
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can be used when deciding if a block can transfer control to another
via a fall-through instead of a branch.
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