diff options
| author | Chris Lattner <sabre@nondot.org> | 2008-10-04 21:27:46 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-10-04 21:27:46 +0000 |
| commit | 31d7161206d7502e97a01a51a76445a8d9ac6ea5 (patch) | |
| tree | a75d03f5732651867aee4096c1bf8889415b4bf1 /lib/CodeGen | |
| parent | 80533040bc3b19f88c64bb8c4900af2e0128858d (diff) | |
wrap some long lines and expand i32 mul's to libcalls, inspired by a
patch by Mikael Lepisto!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57077 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index c19ea67623..e61cb0c1e5 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3007,22 +3007,26 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { } if (Node->getOpcode() == ISD::MULHS && TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { - Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1); + Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), + 1); break; } if (Node->getOpcode() == ISD::MULHU && TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { - Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1); + Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), + 1); break; } if (Node->getOpcode() == ISD::SDIV && TLI.isOperationLegal(ISD::SDIVREM, VT)) { - Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 0); + Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), + 0); break; } if (Node->getOpcode() == ISD::UDIV && TLI.isOperationLegal(ISD::UDIVREM, VT)) { - Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 0); + Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), + 0); break; } @@ -3038,6 +3042,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { isSigned = Node->getOpcode() == ISD::SDIV; } break; + case ISD::MUL: + if (VT == MVT::i32) + LC = RTLIB::MUL_I32; + break; case ISD::FPOW: LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, RTLIB::POW_PPCF128); |