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authorEvan Cheng <evan.cheng@apple.com>2008-10-13 18:35:52 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-10-13 18:35:52 +0000
commit195cd3a58d17f1c98352c6d944549b6c3a50aa1b (patch)
tree87ebaf6af3f14519e88595305b2b23ced719e504 /lib/CodeGen
parentbf8c4f2c6e3d7f614fd89684f38b5b3d1dfe6e5e (diff)
Also update sub-register intervals after a trivial computation is rematt'ed for a copy instruction. PR2775.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57458 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r--lib/CodeGen/SimpleRegisterCoalescing.cpp10
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index bb860d293e..2f2d549a19 100644
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -460,6 +460,16 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
unsigned DefIdx = li_->getDefIndex(CopyIdx);
const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
DLR->valno->copy = NULL;
+ // Don't forget to update sub-register intervals.
+ if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
+ for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
+ if (!li_->hasInterval(*SR))
+ continue;
+ DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
+ if (DLR && DLR->valno->copy == CopyMI)
+ DLR->valno->copy = NULL;
+ }
+ }
MachineBasicBlock::iterator MII = CopyMI;
MachineBasicBlock *MBB = CopyMI->getParent();