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path: root/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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2007-05-16Bug fix: should check ABI alignment, not pref. alignment.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37094 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-15Fix an infinite recursion in GetNegatedExpression.Lauro Ramos Venancio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37086 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-14implement a simple fneg optimization/propagation thing. This compiles:Chris Lattner
CodeGen/PowerPC/fneg.ll into: _t4: fmul f0, f3, f4 fmadd f1, f1, f2, f0 blr instead of: _t4: fneg f0, f3 fmul f0, f0, f4 fmsub f1, f1, f2, f0 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37054 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-09Can't fold the bit_convert is the store is a truncating store.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36962 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-07Forgot a check.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36910 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-07Enable a couple of xforms:Evan Cheng
- (store (bitconvert v)) -> (store v) if resultant store does not require higher alignment - (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not require higher alignment git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36908 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03Don't create indexed load / store with zero offset!Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36716 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01Forgot about chain result; also UNDEF cannot have multiple values.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36622 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01* Only turn a load to UNDEF if all of its outputs have no uses (indexed loadsEvan Cheng
produce two results.) * Do not touch volatile loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36604 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-22PR400 phase 2. Propagate attributed load/store information through DAGs.Christopher Lamb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36356 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-21Revert Christopher Lamb's load/store alignment changes.Reid Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36309 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-21add support for alignment attributes on load/store instructionsChristopher Lamb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36301 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18allow SRL to simplify its operands, as it doesn't demand all bits as input.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36245 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-18When replacing a node in SimplifyDemandedBits, if the old node used anyChris Lattner
single-use nodes, they will be dead soon. Make sure to remove them before processing other nodes. This implements CodeGen/X86/shl_elim.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36244 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBitsChris Lattner
a chance to hack on it. This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr instead of: _baz: srwi r2, r4, 24 rlwimi r2, r3, 8, 0, 23 srwi r2, r2, 9 extsh r3, r2 blr This implements CodeGen/PowerPC/sign_ext_inreg1.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36212 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11fix an infinite loop compiling ldecod, notice by JeffC.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35910 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11Fix this harder.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35888 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11don't create shifts by zero, fix some problems with my previous patchChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35887 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which oftenChris Lattner
allows other simplifications. For example, this compiles: int isnegative(unsigned int X) { return !(X < 2147483648U); } Into this code: x86: movl 4(%esp), %eax shrl $31, %eax ret arm: mov r0, r0, lsr #31 bx lr thumb: lsr r0, r0, #31 bx lr instead of: x86: cmpl $0, 4(%esp) sets %al movzbl %al, %eax ret arm: mov r3, #0 cmp r0, #0 movlt r3, #1 mov r0, r3 bx lr thumb: mov r2, #1 mov r1, #0 cmp r0, #0 blt LBB1_2 @entry LBB1_1: @entry cpy r2, r1 LBB1_2: @entry cpy r0, r2 bx lr Testcase here: test/CodeGen/Generic/ispositive.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35883 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11Codegen integer abs more efficiently using the trick from the PPC CWG. ThisChris Lattner
improves codegen on many architectures. Tests committed as CodeGen/*/iabs.ll X86 Old: X86 New: _test: _test: movl 4(%esp), %ecx movl 4(%esp), %eax movl %ecx, %eax movl %eax, %ecx negl %eax sarl $31, %ecx testl %ecx, %ecx addl %ecx, %eax cmovns %ecx, %eax xorl %ecx, %eax ret ret PPC Old: PPC New: _test: _test: cmpwi cr0, r3, -1 srawi r2, r3, 31 neg r2, r3 add r3, r3, r2 bgt cr0, LBB1_2 ; xor r3, r3, r2 LBB1_1: ; blr mr r3, r2 LBB1_2: ; blr ARM Old: ARM New: _test: _test: rsb r3, r0, #0 add r3, r0, r0, asr #31 cmp r0, #0 eor r0, r3, r0, asr #31 movge r3, r0 bx lr mov r0, r3 bx lr Thumb Old: Thumb New: _test: _test: neg r2, r0 asr r2, r0, #31 cmp r0, #0 add r0, r0, r2 bge LBB1_2 eor r0, r2 LBB1_1: @ bx lr cpy r0, r2 LBB1_2: @ bx lr Sparc Old: Sparc New: test: test: save -96, %o6, %o6 save -96, %o6, %o6 sethi 0, %l0 sra %i0, 31, %l0 sub %l0, %i0, %l0 add %i0, %l0, %l1 subcc %i0, -1, %l1 xor %l1, %l0, %i0 bg .BB1_2 restore %g0, %g0, %g0 nop retl .BB1_1: nop or %g0, %l0, %i0 .BB1_2: restore %g0, %g0, %g0 retl nop It also helps alpha/ia64 :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35881 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-021. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.Scott Michel
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL patterns. This was motivated by the X86/rotate.ll testcase, which should now generate code for other platforms (and soon-to-come platforms.) Rewrote code slightly to make it easier to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35605 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-30Fix incorrect combination of different loads. Reenable zext-over-truncateDale Johannesen
combination. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35517 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-29Disable load width reduction xform of variant (zext (truncate load x)) forEvan Cheng
big endian targets until llvm-gcc build issue has been resolved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35449 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-26SIGN_EXTEND_INREG requires one extra operand, a ValueType node.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35350 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-24Adjust offset to compensate for big endian machines.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35293 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-23Make sure SEXTLOAD of the specific type is supported on the target.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35289 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-23Also replace uses of SRL if that's also folded during ReduceLoadWidth().Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35286 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-23A couple of bug fixes for reducing load width xform:Evan Cheng
1. Address offset is in bytes. 2. Make sure truncate node uses are replaced with new load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35274 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-22More opportunities to reduce load size.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35254 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-21fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits))Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35239 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-07Avoid combining indexed load further.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35005 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-04fold away addc nodes when we know there cannot be a carry-out.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34913 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-04generalizeChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34910 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-04canonicalize constants to the RHS of addc/adde. If nothing uses the carry ↵Chris Lattner
out of addc, turn it into add. This allows us to compile: long long test(long long A, unsigned B) { return (A + ((long long)B << 32)) & 123; } into: _test: movl $123, %eax andl 4(%esp), %eax xorl %edx, %edx ret instead of: _test: xorl %edx, %edx movl %edx, %eax addl 4(%esp), %eax ;; add of zero andl $123, %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34909 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-26Fold (sext (truncate x)) more aggressively, by avoiding creation of aChris Lattner
sextinreg if not needed. This is useful in two cases: before legalize, it avoids creating a sextinreg that will be trivially removed. After legalize if the target doesn't support sextinreg, the trunc/sext would not have been removed before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34621 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-08Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34065 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-20Fix for PR1108: type of insert_vector_elt index operand is PtrVT, not MVT::i32.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33398 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-19Remove this xform:Evan Cheng
(shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) Replace it with: (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) This fixes test/CodeGen/ARM/smul.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33361 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-16Fix PR1114 and CodeGen/Generic/2007-01-15-LoadSelectCycle.ll by beingChris Lattner
careful when folding "c ? load p : load q" that C doesn't reach either load. If so, folding this into load (c ? p : q) will induce a cycle in the graph. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33251 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-16add options to view the dags before the first or second pass of dag combine.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33249 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-08Implement some trivial FP foldings when -enable-unsafe-fp-math is specified.Chris Lattner
This implements CodeGen/PowerPC/unsafe-math.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33024 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-19Eliminate static ctors from StatisticsChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32698 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-16Cannot combine an indexed load / store any further.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32629 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-15This code was usurping the sextload expand in teh legalizer. Just makeJim Laskey
sure the right conditions are checked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32611 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-12make this code more aggressive about turning store fpimm into store int imm.Chris Lattner
This is not sufficient to fix X86/store-fp-constant.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32465 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-11Don't convert store double C, Ptr to store long C, Ptr if i64 is not a legal ↵Evan Cheng
type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32434 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-11Move something that should be in the dag combiner from the legalizer to theNate Begeman
dag combiner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32431 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-07Fix CodeGen/PowerPC/2006-12-07-SelectCrash.ll on PPC64Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32336 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-07Removing even more <iostream> includes.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32320 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-06Detemplatize the Statistic class. The only type it is instantiated withChris Lattner
is 'unsigned'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32279 91177308-0d34-0410-b5e6-96231b3b80d8
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