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path: root/lib/CodeGen/MachineScheduler.cpp
AgeCommit message (Expand)Author
2012-05-24Silence unused variable warnings from when assertions are disabled.Kaelyn Uhrain
2012-05-24misched: Use the same scheduling heuristics with -misched-topdown/bottomup.Andrew Trick
2012-05-24misched: Trace regpressure.Andrew Trick
2012-05-24misched: Give each ReadyQ a unique IDAndrew Trick
2012-05-24misched: Added ScoreboardHazardRecognizer.Andrew Trick
2012-05-24misched: Release bottom roots in reverse order.Andrew Trick
2012-05-24misched: rename ReadyQ classAndrew Trick
2012-05-24misched: copy comments so compareRPDelta is readable by itself.Andrew Trick
2012-05-17commentsAndrew Trick
2012-05-17misched: trace ReadyQ.Andrew Trick
2012-05-17misched: Added 3-level regpressure back-off.Andrew Trick
2012-05-17commentAndrew Trick
2012-05-17misched: fix liveness iteratorsAndrew Trick
2012-05-10misched: Print machineinstrs with -debug-only=mischedAndrew Trick
2012-05-10misched: tracing register pressure heuristics.Andrew Trick
2012-05-10misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick
2012-05-10misched: Release only unscheduled nodes into ReadyQ.Andrew Trick
2012-05-10misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick
2012-05-10misched: Introducing Top and Bottom register pressure trackers during schedul...Andrew Trick
2012-04-24Fix a naughty header include that breaks "installed" builds.Andrew Trick
2012-04-24misched: try (not too hard) to place debug values where they belongAndrew Trick
2012-04-24misched: ignore debug values during schedulingAndrew Trick
2012-04-24misched: DAG builder support for tracking register pressure within the curren...Andrew Trick
2012-04-01misched: Add finalizeScheduler to complete the target interface.Andrew Trick
2012-03-21misched: trace LiveIntervals after scheduling.Andrew Trick
2012-03-21misched: obvious iterator update fixes for bottom-up.Andrew Trick
2012-03-21misched: cleanup main loopAndrew Trick
2012-03-19Add an option to the MI scheduler to cut off scheduling after a fixed number ofLang Hames
2012-03-14Silence operator precedence warnings.Benjamin Kramer
2012-03-14misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick
2012-03-14misched commentsAndrew Trick
2012-03-09misched: handle scheduler that insert instructions at empty region boundaries.Andrew Trick
2012-03-09misched: handle scheduling region boundaries nicely.Andrew Trick
2012-03-09misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...Andrew Trick
2012-03-09misched commentsAndrew Trick
2012-03-09revert 152356: verify misched changes using -misched=shuffle.Andrew Trick
2012-03-09misched: allow the default scheduler to be one chosen by the target.Andrew Trick
2012-03-09Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin().Evan Cheng
2012-03-08misched interface: Expose the MachineScheduler pass.Andrew Trick
2012-03-07misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick
2012-03-07misched prep: rename InsertPos to End.Andrew Trick
2012-03-07misched preparation: rename core scheduler methods for consistency.Andrew Trick
2012-03-07misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick
2012-03-07Added -view-misched=dags options.Andrew Trick
2012-03-07misched: Use the StartBlock/FinishBlock hooksAndrew Trick
2012-02-22Initialize SUnits before DAG building.Andrew Trick
2012-02-17MachineScheduler shouldn't use/preserve LiveDebugVariables.Lang Hames
2012-02-15Disentangle moving a machine instr from updating LiveIntervals.Lang Hames
2012-02-10RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick
2012-02-09commentAndrew Trick
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