diff options
Diffstat (limited to 'test/CodeGen')
242 files changed, 5871 insertions, 981 deletions
diff --git a/test/CodeGen/AArch64/alloca.ll b/test/CodeGen/AArch64/alloca.ll index 64217695d8..c62edf6503 100644 --- a/test/CodeGen/AArch64/alloca.ll +++ b/test/CodeGen/AArch64/alloca.ll @@ -71,8 +71,8 @@ define void @test_variadic_alloca(i64 %n, ...) { ; CHECK: sub sp, sp, #208 ; CHECK: stp x29, x30, [sp, #192] ; CHECK: add x29, sp, #192 -; CHECK: sub x9, x29, #192 -; CHECK: add x8, x9, #0 +; CHECK: sub [[TMP:x[0-9]+]], x29, #192 +; CHECK: add x8, [[TMP]], #0 ; CHECK: str q7, [x8, #112] ; [...] ; CHECK: str q1, [x8, #16] @@ -131,4 +131,4 @@ define void @test_scoped_alloca(i64 %n) { ; CHECK: mov sp, [[SAVED_SP]] ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/ARM/Stats/2007-03-13-InstrSched.ll b/test/CodeGen/ARM/2007-03-13-InstrSched.ll index a63cdd46e2..4783f37076 100644 --- a/test/CodeGen/ARM/Stats/2007-03-13-InstrSched.ll +++ b/test/CodeGen/ARM/2007-03-13-InstrSched.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \ ; RUN: -mattr=+v6 | grep r9 ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \ diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll index 29ccf22eee..91a9903f38 100644 --- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -76,27 +76,27 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!3} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] +!0 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786451, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ] -!2 = metadata !{i32 786473, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 0, i32 4, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0, metadata !47, metadata !47, metadata !46, metadata !47} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786473, metadata !48} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, i32 4, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !47, metadata !47, metadata !46, metadata !47, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9} !5 = metadata !{i32 786445, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] !6 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] !7 = metadata !{i32 786445, metadata !1, metadata !"Kind", metadata !2, i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ] !8 = metadata !{i32 786468, metadata !2, metadata !"unsigned int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!9 = metadata !{i32 786478, i32 0, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", metadata !2, i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 786478, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", metadata !2, i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] !10 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] !11 = metadata !{null, metadata !12, metadata !13} !12 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] !13 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !14 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ] !15 = metadata !{null, metadata !12} -!16 = metadata !{i32 786478, i32 0, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", metadata !2, i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev} ; [ DW_TAG_subprogram ] -!17 = metadata !{i32 786478, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", metadata !2, i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal} ; [ DW_TAG_subprogram ] +!16 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", metadata !2, i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev} ; [ DW_TAG_subprogram ] +!17 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", metadata !2, i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal} ; [ DW_TAG_subprogram ] !18 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ] !19 = metadata !{metadata !13, metadata !13, metadata !1} -!20 = metadata !{i32 786478, i32 0, metadata !2, metadata !"main", metadata !"main", metadata !"main", metadata !2, i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!20 = metadata !{i32 786478, metadata !2, metadata !"main", metadata !"main", metadata !"main", metadata !2, i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] !21 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ] !22 = metadata !{metadata !13} !23 = metadata !{i32 786689, metadata !17, metadata !"i", metadata !2, i32 16, metadata !13, i32 0, i32 0} ; [ DW_TAG_arg_variable ] @@ -104,7 +104,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !25 = metadata !{i32 786689, metadata !17, metadata !"location", metadata !2, i32 16, metadata !26, i32 0, i32 0} ; [ DW_TAG_arg_variable ] !26 = metadata !{i32 786448, metadata !2, metadata !"SVal", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ] !27 = metadata !{i32 17, i32 0, metadata !28, null} -!28 = metadata !{i32 786443, metadata !17, i32 16, i32 0, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 786443, metadata !2, metadata !17, i32 16, i32 0, i32 2} ; [ DW_TAG_lexical_block ] !29 = metadata !{i32 18, i32 0, metadata !28, null} !30 = metadata !{i32 20, i32 0, metadata !28, null} !31 = metadata !{i32 786689, metadata !16, metadata !"this", metadata !2, i32 11, metadata !32, i32 0, i32 0} ; [ DW_TAG_arg_variable ] @@ -112,11 +112,11 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !33 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_pointer_type ] !34 = metadata !{i32 11, i32 0, metadata !16, null} !35 = metadata !{i32 11, i32 0, metadata !36, null} -!36 = metadata !{i32 786443, metadata !37, i32 11, i32 0, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] -!37 = metadata !{i32 786443, metadata !16, i32 11, i32 0, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!36 = metadata !{i32 786443, metadata !2, metadata !37, i32 11, i32 0, i32 1} ; [ DW_TAG_lexical_block ] +!37 = metadata !{i32 786443, metadata !2, metadata !16, i32 11, i32 0, i32 0} ; [ DW_TAG_lexical_block ] !38 = metadata !{i32 786688, metadata !39, metadata !"v", metadata !2, i32 24, metadata !1, i32 0, i32 0} ; [ DW_TAG_auto_variable ] -!39 = metadata !{i32 786443, metadata !40, i32 23, i32 0, metadata !2, i32 4} ; [ DW_TAG_lexical_block ] -!40 = metadata !{i32 786443, metadata !20, i32 23, i32 0, metadata !2, i32 3} ; [ DW_TAG_lexical_block ] +!39 = metadata !{i32 786443, metadata !2, metadata !40, i32 23, i32 0, i32 4} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 786443, metadata !2, metadata !20, i32 23, i32 0, i32 3} ; [ DW_TAG_lexical_block ] !41 = metadata !{i32 24, i32 0, metadata !39, null} !42 = metadata !{i32 25, i32 0, metadata !39, null} !43 = metadata !{i32 26, i32 0, metadata !39, null} @@ -124,3 +124,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !45 = metadata !{i32 27, i32 0, metadata !39, null} !46 = metadata !{metadata !0, metadata !9, metadata !16, metadata !17, metadata !20} !47 = metadata !{i32 0} +!48 = metadata !{metadata !"small.cc", metadata !"/Users/manav/R8248330"} diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index c8ce6eec62..1d1b89a34f 100644 --- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -76,24 +76,17 @@ entry: } !llvm.dbg.cu = !{!2} -!40 = metadata !{metadata !0, metadata !6, metadata !7, metadata !8, metadata !9} -!41 = metadata !{metadata !13, metadata !14, metadata !15, metadata !16, metadata !17} -!42 = metadata !{metadata !10, metadata !11} -!43 = metadata !{metadata !18, metadata !19} -!44 = metadata !{metadata !21, metadata !22} -!45 = metadata !{metadata !24, metadata !25} -!46 = metadata !{metadata !27, metadata !28} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"get1", metadata !"get1", metadata !"get1", metadata !1, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get1, null, null, metadata !42, i32 4} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"foo.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 1, metadata !"foo.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"get1", metadata !"get1", metadata !"get1", metadata !1, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get1, null, null, metadata !42, i32 4} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !47, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !1, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5, metadata !5} -!5 = metadata !{i32 786468, metadata !1, metadata !"_Bool", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 786478, i32 0, metadata !1, metadata !"get2", metadata !"get2", metadata !"get2", metadata !1, i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get2, null, null, metadata !43, i32 7} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 786478, i32 0, metadata !1, metadata !"get3", metadata !"get3", metadata !"get3", metadata !1, i32 10, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get3, null, null, metadata !44, i32 10} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 786478, i32 0, metadata !1, metadata !"get4", metadata !"get4", metadata !"get4", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get4, null, null, metadata !45, i32 13} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 786478, i32 0, metadata !1, metadata !"get5", metadata !"get5", metadata !"get5", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get5, null, null, metadata !46, i32 16} ; [ DW_TAG_subprogram ] +!5 = metadata !{i32 786468, metadata !1, metadata !1, metadata !"_Bool", i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786478, metadata !1, metadata !"get2", metadata !"get2", metadata !"get2", metadata !1, i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get2, null, null, metadata !43, i32 7} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786478, metadata !1, metadata !"get3", metadata !"get3", metadata !"get3", metadata !1, i32 10, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get3, null, null, metadata !44, i32 10} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 786478, metadata !1, metadata !"get4", metadata !"get4", metadata !"get4", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get4, null, null, metadata !45, i32 13} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 786478, metadata !1, metadata !"get5", metadata !"get5", metadata !"get5", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get5, null, null, metadata !46, i32 16} ; [ DW_TAG_subprogram ] !10 = metadata !{i32 786689, metadata !0, metadata !"a", metadata !1, i32 4, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !11 = metadata !{i32 786688, metadata !12, metadata !"b", metadata !1, i32 4, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] !12 = metadata !{i32 786443, metadata !0, i32 4, i32 0, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] @@ -124,3 +117,11 @@ entry: !37 = metadata !{i32 13, i32 0, metadata !26, null} !38 = metadata !{i32 16, i32 0, metadata !9, null} !39 = metadata !{i32 16, i32 0, metadata !29, null} +!40 = metadata !{metadata !0, metadata !6, metadata !7, metadata !8, metadata !9} +!41 = metadata !{metadata !13, metadata !14, metadata !15, metadata !16, metadata !17} +!42 = metadata !{metadata !10, metadata !11} +!43 = metadata !{metadata !18, metadata !19} +!44 = metadata !{metadata !21, metadata !22} +!45 = metadata !{metadata !24, metadata !25} +!46 = metadata !{metadata !27, metadata !28} +!47 = metadata !{metadata !"foo.c", metadata !"/tmp/"} diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll index 2cd4acea63..266609b8ce 100644 --- a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -73,24 +73,17 @@ define i32 @get5(i32 %a) nounwind optsize ssp { declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!40 = metadata !{metadata !1, metadata !6, metadata !7, metadata !8, metadata !9} -!42 = metadata !{metadata !10, metadata !11} -!43 = metadata !{metadata !13, metadata !14} -!44 = metadata !{metadata !16, metadata !17} -!45 = metadata !{metadata !19, metadata !20} -!46 = metadata !{metadata !27, metadata !28} -!41 = metadata !{metadata !22, metadata !23, metadata !24, metadata !25, metadata !26} -!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"ss3.c", metadata !"/private/tmp", metadata !"clang", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"get1", metadata !"get1", metadata !"", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get1, null, null, metadata !42, i32 5} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 786473, metadata !"ss3.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786449, metadata !47, i32 12, metadata !"clang", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, null} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !2, metadata !"get1", metadata !"get1", metadata !"", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get1, null, null, metadata !42, i32 5} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786453, metadata !2, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 786478, i32 0, metadata !2, metadata !"get2", metadata !"get2", metadata !"", metadata !2, i32 8, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get2, null, null, metadata !43, i32 8} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 786478, i32 0, metadata !2, metadata !"get3", metadata !"get3", metadata !"", metadata !2, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get3, null, null, metadata !44, i32 11} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 786478, i32 0, metadata !2, metadata !"get4", metadata !"get4", metadata !"", metadata !2, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get4, null, null, metadata !45, i32 14} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 786478, i32 0, metadata !2, metadata !"get5", metadata !"get5", metadata !"", metadata !2, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get5, null, null, metadata !46, i32 17} ; [ DW_TAG_subprogram ] +!5 = metadata !{i32 786468, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786478, metadata !2, metadata !"get2", metadata !"get2", metadata !"", metadata !2, i32 8, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get2, null, null, metadata !43, i32 8} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786478, metadata !2, metadata !"get3", metadata !"get3", metadata !"", metadata !2, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get3, null, null, metadata !44, i32 11} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 786478, metadata !2, metadata !"get4", metadata !"get4", metadata !"", metadata !2, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get4, null, null, metadata !45, i32 14} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 786478, metadata !2, metadata !"get5", metadata !"get5", metadata !"", metadata !2, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get5, null, null, metadata !46, i32 17} ; [ DW_TAG_subprogram ] !10 = metadata !{i32 786689, metadata !1, metadata !"a", metadata !2, i32 16777221, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !11 = metadata !{i32 786688, metadata !12, metadata !"b", metadata !2, i32 5, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] !12 = metadata !{i32 786443, metadata !1, i32 5, i32 19, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] @@ -121,3 +114,11 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !37 = metadata !{i32 14, i32 32, metadata !21, null} !38 = metadata !{i32 17, i32 16, metadata !9, null} !39 = metadata !{i32 17, i32 32, metadata !29, null} +!40 = metadata !{metadata !1, metadata !6, metadata !7, metadata !8, metadata !9} +!41 = metadata !{metadata !22, metadata !23, metadata !24, metadata !25, metadata !26} +!42 = metadata !{metadata !10, metadata !11} +!43 = metadata !{metadata !13, metadata !14} +!44 = metadata !{metadata !16, metadata !17} +!45 = metadata !{metadata !19, metadata !20} +!46 = metadata !{metadata !27, metadata !28} +!47 = metadata !{metadata !"ss3.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/ARM/Stats/2011-12-14-machine-sink.ll b/test/CodeGen/ARM/2011-12-14-machine-sink.ll index b21bb006e3..1b21f7571d 100644 --- a/test/CodeGen/ARM/Stats/2011-12-14-machine-sink.ll +++ b/test/CodeGen/ARM/2011-12-14-machine-sink.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -o /dev/null -stats 2>&1 | FileCheck %s -check-prefix=STATS ; Radar 10266272 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" diff --git a/test/CodeGen/ARM/DbgValueOtherTargets.test b/test/CodeGen/ARM/DbgValueOtherTargets.test index 8739a43640..bf90891de0 100644 --- a/test/CodeGen/ARM/DbgValueOtherTargets.test +++ b/test/CodeGen/ARM/DbgValueOtherTargets.test @@ -1 +1 @@ -; RUN: llc -O0 -march=arm -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -march=arm -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/ARM/Stats/lit.local.cfg b/test/CodeGen/ARM/Stats/lit.local.cfg deleted file mode 100644 index f6194d2421..0000000000 --- a/test/CodeGen/ARM/Stats/lit.local.cfg +++ /dev/null @@ -1,8 +0,0 @@ -config.suffixes = ['.ll', '.c', '.cpp'] - -targets = set(config.root.targets_to_build.split()) -if not 'ARM' in targets: - config.unsupported = True - -if not config.root.enable_assertions: - config.unsupported = True diff --git a/test/CodeGen/ARM/a15-SD-dep.ll b/test/CodeGen/ARM/a15-SD-dep.ll new file mode 100644 index 0000000000..a52468e5be --- /dev/null +++ b/test/CodeGen/ARM/a15-SD-dep.ll @@ -0,0 +1,58 @@ +; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s | FileCheck -check-prefix=DISABLED %s +; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=ENABLED %s + +; CHECK-ENABLED: t1: +; CHECK-DISABLED: t1: +define <2 x float> @t1(float %f) { + ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] + ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] + %i1 = insertelement <2 x float> undef, float %f, i32 1 + %i2 = fadd <2 x float> %i1, %i1 + ret <2 x float> %i2 +} + +; CHECK-ENABLED: t2: +; CHECK-DISABLED: t2: +define <4 x float> @t2(float %g, float %f) { + ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0] + ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] + %i1 = insertelement <4 x float> undef, float %f, i32 1 + %i2 = fadd <4 x float> %i1, %i1 + ret <4 x float> %i2 +} + +; CHECK-ENABLED: t3: +; CHECK-DISABLED: t3: +define arm_aapcs_vfpcc <2 x float> @t3(float %f) { + ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] + ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] + %i1 = insertelement <2 x float> undef, float %f, i32 1 + %i2 = fadd <2 x float> %i1, %i1 + ret <2 x float> %i2 +} + +; CHECK-ENABLED: t4: +; CHECK-DISABLED: t4: +define <2 x float> @t4(float %f) { + ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] + ; CHECK-DISABLED-NOT: vdup + %i1 = insertelement <2 x float> undef, float %f, i32 1 + br label %b + + ; Block %b has an S-reg as live-in. +b: + %i2 = fadd <2 x float> %i1, %i1 + ret <2 x float> %i2 +} + +; CHECK-ENABLED: t5: +; CHECK-DISABLED: t5: +define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) { + ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0] + ; CHECK-ENABLED: vadd.f32 + ; CHECK-ENABLED-NEXT: bx lr + ; CHECK-DISABLED-NOT: vdup + %i1 = insertelement <4 x float> %q, float %f, i32 1 + %i2 = fadd <4 x float> %i1, %i1 + ret <4 x float> %i2 +} diff --git a/test/CodeGen/ARM/a15-partial-update.ll b/test/CodeGen/ARM/a15-partial-update.ll new file mode 100644 index 0000000000..6306790d15 --- /dev/null +++ b/test/CodeGen/ARM/a15-partial-update.ll @@ -0,0 +1,38 @@ +; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s + +; CHECK: t1: +define <2 x float> @t1(float* %A, <2 x float> %B) { +; The generated code for this test uses a vld1.32 instruction +; to write the lane 1 of a D register containing the value of +; <2 x float> %B. Since the D register is defined, it would +; be incorrect to fully write it (with a vmov.f64) before the +; vld1.32 instruction. The test checks that a vmov.f64 was not +; generated. + +; CHECK-NOT: vmov.{{.*}} d{{[0-9]+}}, + %tmp2 = load float* %A, align 4 + %tmp3 = insertelement <2 x float> %B, float %tmp2, i32 1 + ret <2 x float> %tmp3 +} + +; CHECK: t2: +define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) { +entry: + br label %loop +loop: +; The code generated by this test uses a vld1.32 instruction. +; We check that a dependency breaking vmov* instruction was +; generated. + +; CHECK: vmov.{{.*}} d{{[0-9]+}}, + %oldcount = phi i32 [0, %entry], [%newcount, %loop] + %newcount = add i32 %oldcount, 1 + %p1 = getelementptr <4 x i8> *%in, i32 %newcount + %p2 = getelementptr <4 x i8> *%out, i32 %newcount + %tmp1 = load <4 x i8> *%p1, align 4 + store <4 x i8> %tmp1, <4 x i8> *%p2 + %cmp = icmp eq i32 %newcount, %n + br i1 %cmp, label %loop, label %ret +ret: + ret void +} diff --git a/test/CodeGen/ARM/Stats/addrmode.ll b/test/CodeGen/ARM/addrmode.ll index 6da90897b9..748d258044 100644 --- a/test/CodeGen/ARM/Stats/addrmode.ll +++ b/test/CodeGen/ARM/addrmode.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=arm -stats 2>&1 | grep asm-printer | grep 4 define i32 @t1(i32 %a) { diff --git a/test/CodeGen/ARM/call_nolink.ll b/test/CodeGen/ARM/call_nolink.ll index 00b16888f3..5ec7f74a60 100644 --- a/test/CodeGen/ARM/call_nolink.ll +++ b/test/CodeGen/ARM/call_nolink.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \ -; RUN: not grep "bx lr" +; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | FileCheck %s %struct.anon = type { i32 (i32, i32, i32)*, i32, i32, [3 x i32], i8*, i8*, i8* } @r = external global [14 x i32] ; <[14 x i32]*> [#uses=4] @@ -8,6 +7,8 @@ @numi = external global i32 ; <i32*> [#uses=1] @counter = external global [2 x i32] ; <[2 x i32]*> [#uses=1] +; CHECK: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i: +; CHECK-NOT: bx lr define void @main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i() { newFuncRoot: @@ -50,3 +51,12 @@ bb115.i.i: ; preds = %bb115.i.i.bb115.i.i_crit_edge, %newFuncRoot icmp slt i32 %tmp166.i.i, %tmp168.i.i ; <i1>:0 [#uses=1] br i1 %0, label %bb115.i.i.bb115.i.i_crit_edge, label %bb115.i.i.bb170.i.i_crit_edge.exitStub } + +define void @PR15520(void ()* %fn) { + call void %fn() + ret void + +; CHECK: PR15520: +; CHECK: mov lr, pc +; CHECK: mov pc, r0 +} diff --git a/test/CodeGen/ARM/commute-movcc.ll b/test/CodeGen/ARM/commute-movcc.ll index 7316452cd6..769ba55eb9 100644 --- a/test/CodeGen/ARM/commute-movcc.ll +++ b/test/CodeGen/ARM/commute-movcc.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=thumbv7-apple-ios -disable-code-place < %s | FileCheck %s -; RUN: llc -mtriple=armv7-apple-ios -disable-code-place < %s | FileCheck %s +; RUN: llc -mtriple=thumbv7-apple-ios -disable-block-placement < %s | FileCheck %s +; RUN: llc -mtriple=armv7-apple-ios -disable-block-placement < %s | FileCheck %s ; LLVM IR optimizers canonicalize icmp+select this way. ; Make sure that TwoAddressInstructionPass can commute the corresponding diff --git a/test/CodeGen/ARM/debug-info-arg.ll b/test/CodeGen/ARM/debug-info-arg.ll index 1694d6412f..33c8e9daae 100644 --- a/test/CodeGen/ARM/debug-info-arg.ll +++ b/test/CodeGen/ARM/debug-info-arg.ll @@ -30,26 +30,24 @@ declare void @foobar(i64, i64) declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!30 = metadata !{metadata !1} -!31 = metadata !{metadata !5, metadata !13, metadata !14, metadata !17, metadata !18, metadata!19} -!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"one.c", metadata !"/Volumes/Athwagate/R10048772", metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !30, null, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, null, null, metadata !31, i32 11} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 786473, metadata !"one.c", metadata !"/Volumes/Athwagate/R10048772", metadata !0} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786449, metadata !32, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, null, null, metadata !30, null, null} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !2, metadata !2, metadata !"foo", metadata !"foo", metadata !"", i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, null, null, metadata !31, i32 11} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !32} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786453, metadata !32, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{null} !5 = metadata !{i32 786689, metadata !1, metadata !"this", metadata !2, i32 16777227, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] -!6 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ] -!7 = metadata !{i32 786451, metadata !0, metadata !"tag_s", metadata !2, i32 5, i64 96, i64 32, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!6 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ] +!7 = metadata !{i32 786451, metadata !32, metadata !0, metadata !"tag_s", i32 5, i64 96, i64 32, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_structure_type ] !8 = metadata !{metadata !9, metadata !11, metadata !12} -!9 = metadata !{i32 786445, metadata !7, metadata !"x", metadata !2, i32 6, i64 32, i64 32, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] -!10 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!11 = metadata !{i32 786445, metadata !7, metadata !"y", metadata !2, i32 7, i64 32, i64 32, i64 32, i32 0, metadata !10} ; [ DW_TAG_member ] -!12 = metadata !{i32 786445, metadata !7, metadata !"z", metadata !2, i32 8, i64 32, i64 32, i64 64, i32 0, metadata !10} ; [ DW_TAG_member ] +!9 = metadata !{i32 786445, metadata !32, metadata !7, metadata !"x", i32 6, i64 32, i64 32, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] +!10 = metadata !{i32 786468, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!11 = metadata !{i32 786445, metadata !32, metadata !7, metadata !"y", i32 7, i64 32, i64 32, i64 32, i32 0, metadata !10} ; [ DW_TAG_member ] +!12 = metadata !{i32 786445, metadata !32, metadata !7, metadata !"z", i32 8, i64 32, i64 32, i64 64, i32 0, metadata !10} ; [ DW_TAG_member ] !13 = metadata !{i32 786689, metadata !1, metadata !"c", metadata !2, i32 33554443, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] !14 = metadata !{i32 786689, metadata !1, metadata !"x", metadata !2, i32 50331659, metadata !15, i32 0, null} ; [ DW_TAG_arg_variable ] -!15 = metadata !{i32 786454, metadata !0, metadata !"UInt64", metadata !2, i32 1, i64 0, i64 0, i64 0, i32 0, metadata !16} ; [ DW_TAG_typedef ] -!16 = metadata !{i32 786468, metadata !0, metadata !"long long unsigned int", null, i32 0, i64 64, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!15 = metadata !{i32 786454, metadata !32, metadata !0, metadata !"UInt64", i32 1, i64 0, i64 0, i64 0, i32 0, metadata !16} ; [ DW_TAG_typedef ] +!16 = metadata !{i32 786468, null, metadata !0, metadata !"long long unsigned int", i32 0, i64 64, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] !17 = metadata !{i32 786689, metadata !1, metadata !"y", metadata !2, i32 67108875, metadata !15, i32 0, null} ; [ DW_TAG_arg_variable ] !18 = metadata !{i32 786689, metadata !1, metadata !"ptr1", metadata !2, i32 83886091, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] !19 = metadata !{i32 786689, metadata !1, metadata !"ptr2", metadata !2, i32 100663307, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] @@ -63,3 +61,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !27 = metadata !{i32 786443, metadata !1, i32 11, i32 107, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] !28 = metadata !{i32 13, i32 5, metadata !27, null} !29 = metadata !{i32 14, i32 1, metadata !27, null} +!30 = metadata !{metadata !1} +!31 = metadata !{metadata !5, metadata !13, metadata !14, metadata !17, metadata !18, metadata!19} +!32 = metadata !{metadata !"one.c", metadata !"/Volumes/Athwagate/R10048772"} diff --git a/test/CodeGen/ARM/debug-info-blocks.ll b/test/CodeGen/ARM/debug-info-blocks.ll index 2cb24bd11e..d0bfecc5af 100644 --- a/test/CodeGen/ARM/debug-info-blocks.ll +++ b/test/CodeGen/ARM/debug-info-blocks.ll @@ -93,138 +93,136 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load } !llvm.dbg.cu = !{!0} -!147 = metadata !{metadata !1, metadata !1, metadata !5, metadata !5, metadata !9, metadata !14, metadata !19, metadata !19, metadata !14, metadata !14, metadata !14, metadata !19, metadata !19, metadata !19} -!148 = metadata !{metadata !23} -!0 = metadata !{i32 786449, i32 0, i32 16, metadata !"MyLibrary.i", metadata !"/Volumes/Sandbox/llvm", metadata !"Apple clang version 2.1", i1 true, i1 false, metadata !"", i32 2, metadata !147, null, metadata !148, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 786433, metadata !0, metadata !"", metadata !2, i32 248, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !3, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] -!2 = metadata !{i32 786473, metadata !"header.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] +!0 = metadata !{i32 786449, i32 16, metadata !40, metadata !"Apple clang version 2.1", i1 false, metadata !"", i32 2, metadata !147, null, metadata !148, null, metadata !""} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786433, metadata !160, metadata !0, metadata !"", i32 248, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !3, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] +!2 = metadata !{i32 786473, metadata !160} ; [ DW_TAG_file_type ] !3 = metadata !{metadata !4} !4 = metadata !{i32 786472, metadata !"Ver1", i64 0} ; [ DW_TAG_enumerator ] -!5 = metadata !{i32 786433, metadata !0, metadata !"Mode", metadata !6, i32 79, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !7, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] -!6 = metadata !{i32 786473, metadata !"header2.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] +!5 = metadata !{i32 786433, metadata !160, metadata !0, metadata !"Mode", i32 79, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !7, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] +!6 = metadata !{i32 786473, metadata !161} ; [ DW_TAG_file_type ] !7 = metadata !{metadata !8} !8 = metadata !{i32 786472, metadata !"One", i64 0} ; [ DW_TAG_enumerator ] -!9 = metadata !{i32 786433, metadata !0, metadata !"", metadata !10, i32 15, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !11, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] -!10 = metadata !{i32 786473, metadata !"header3.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] +!9 = metadata !{i32 786433, metadata !149, metadata !0, metadata !"", i32 15, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !11, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] +!10 = metadata !{i32 786473, metadata !149} ; [ DW_TAG_file_type ] !11 = metadata !{metadata !12, metadata !13} !12 = metadata !{i32 786472, metadata !"Unknown", i64 0} ; [ DW_TAG_enumerator ] !13 = metadata !{i32 786472, metadata !"Known", i64 1} ; [ DW_TAG_enumerator ] -!14 = metadata !{i32 786433, metadata !0, metadata !"", metadata !15, i32 20, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !16, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] -!15 = metadata !{i32 786473, metadata !"Private.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] +!14 = metadata !{i32 786433, metadata !150, metadata !0, metadata !"", i32 20, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !16, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] +!15 = metadata !{i32 786473, metadata !150} ; [ DW_TAG_file_type ] !16 = metadata !{metadata !17, metadata !18} !17 = metadata !{i32 786472, metadata !"Single", i64 0} ; [ DW_TAG_enumerator ] !18 = metadata !{i32 786472, metadata !"Double", i64 1} ; [ DW_TAG_enumerator ] -!19 = metadata !{i32 786433, metadata !0, metadata !"", metadata !20, i32 14, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !21, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] -!20 = metadata !{i32 786473, metadata !"header4.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] +!19 = metadata !{i32 786433, metadata !151, metadata !0, metadata !"", i32 14, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !21, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] +!20 = metadata !{i32 786473, metadata !151} ; [ DW_TAG_file_type ] !21 = metadata !{metadata !22} !22 = metadata !{i32 786472, metadata !"Eleven", i64 0} ; [ DW_TAG_enumerator ] -!23 = metadata !{i32 786478, i32 0, metadata !24, metadata !"foobar_func_block_invoke_0", metadata !"foobar_func_block_invoke_0", metadata !"", metadata !24, i32 609, metadata !25, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0, null, null, null, i32 609} ; [ DW_TAG_subprogram ] -!24 = metadata !{i32 786473, metadata !"MyLibrary.m", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] -!25 = metadata !{i32 786453, metadata !24, metadata !"", metadata !24, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !26, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!23 = metadata !{i32 786478, metadata !24, metadata !"foobar_func_block_invoke_0", metadata !"foobar_func_block_invoke_0", metadata !"", metadata !24, i32 609, metadata !25, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0, null, null, null, i32 609} ; [ DW_TAG_subprogram ] +!24 = metadata !{i32 786473, metadata !152} ; [ DW_TAG_file_type ] +!25 = metadata !{i32 786453, metadata !152, metadata !24, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !26, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !26 = metadata !{null} !27 = metadata !{i32 786689, metadata !23, metadata !".block_descriptor", metadata !24, i32 16777825, metadata !28, i32 64, null} ; [ DW_TAG_arg_variable ] -!28 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 32, i64 0, i64 0, i32 0, metadata !29} ; [ DW_TAG_pointer_type ] -!29 = metadata !{i32 786451, metadata !24, metadata !"__block_literal_14", metadata !24, i32 609, i64 256, i64 32, i32 0, i32 0, i32 0, metadata !30, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!28 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 0, i64 0, i32 0, metadata !29} ; [ DW_TAG_pointer_type ] +!29 = metadata !{i32 786451, metadata !152, metadata !24, metadata !"__block_literal_14", i32 609, i64 256, i64 32, i32 0, i32 0, i32 0, metadata !30, i32 0, i32 0} ; [ DW_TAG_structure_type ] !30 = metadata !{metadata !31, metadata !33, metadata !35, metadata !36, metadata !37, metadata !48, metadata !89, metadata !124} -!31 = metadata !{i32 786445, metadata !24, metadata !"__isa", metadata !24, i32 609, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_member ] -!32 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] -!33 = metadata !{i32 786445, metadata !24, metadata !"__flags", metadata !24, i32 609, i64 32, i64 32, i64 32, i32 0, metadata !34} ; [ DW_TAG_member ] -!34 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!35 = metadata !{i32 786445, metadata !24, metadata !"__reserved", metadata !24, i32 609, i64 32, i64 32, i64 64, i32 0, metadata !34} ; [ DW_TAG_member ] -!36 = metadata !{i32 786445, metadata !24, metadata !"__FuncPtr", metadata !24, i32 609, i64 32, i64 32, i64 96, i32 0, metadata !32} ; [ DW_TAG_member ] -!37 = metadata !{i32 786445, metadata !24, metadata !"__descriptor", metadata !24, i32 609, i64 32, i64 32, i64 128, i32 0, metadata !38} ; [ DW_TAG_member ] -!38 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !39} ; [ DW_TAG_pointer_type ] -!39 = metadata !{i32 786451, metadata !0, metadata !"__block_descriptor_withcopydispose", metadata !40, i32 307, i64 128, i64 32, i32 0, i32 0, i32 0, metadata !41, i32 0, i32 0} ; [ DW_TAG_structure_type ] -!40 = metadata !{i32 786473, metadata !"MyLibrary.i", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] +!31 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__isa", i32 609, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_member ] +!32 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!33 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__flags", i32 609, i64 32, i64 32, i64 32, i32 0, metadata !34} ; [ DW_TAG_member ] +!34 = metadata !{i32 786468, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!35 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__reserved", i32 609, i64 32, i64 32, i64 64, i32 0, metadata !34} ; [ DW_TAG_member ] +!36 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__FuncPtr", i32 609, i64 32, i64 32, i64 96, i32 0, metadata !32} ; [ DW_TAG_member ] +!37 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__descriptor", i32 609, i64 32, i64 32, i64 128, i32 0, metadata !38} ; [ DW_TAG_member ] +!38 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !39} ; [ DW_TAG_pointer_type ] +!39 = metadata !{i32 786451, metadata !153, metadata !0, metadata !"__block_descriptor_withcopydispose", i32 307, i64 128, i64 32, i32 0, i32 0, i32 0, metadata !41, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!40 = metadata !{i32 786473, metadata !153} ; [ DW_TAG_file_type ] !41 = metadata !{metadata !42, metadata !44, metadata !45, metadata !47} -!42 = metadata !{i32 786445, metadata !40, metadata !"reserved", metadata !40, i32 307, i64 32, i64 32, i64 0, i32 0, metadata !43} ; [ DW_TAG_member ] -!43 = metadata !{i32 786468, metadata !0, metadata !"long unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!44 = metadata !{i32 786445, metadata !40, metadata !"Size", metadata !40, i32 307, i64 32, i64 32, i64 32, i32 0, metadata !43} ; [ DW_TAG_member ] -!45 = metadata !{i32 786445, metadata !40, metadata !"CopyFuncPtr", metadata !40, i32 307, i64 32, i64 32, i64 64, i32 0, metadata !46} ; [ DW_TAG_member ] -!46 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_pointer_type ] -!47 = metadata !{i32 786445, metadata !40, metadata !"DestroyFuncPtr", metadata !40, i32 307, i64 32, i64 32, i64 96, i32 0, metadata !46} ; [ DW_TAG_member ] -!48 = metadata !{i32 786445, metadata !24, metadata !"mydata", metadata !24, i32 609, i64 32, i64 32, i64 160, i32 0, metadata !49} ; [ DW_TAG_member ] -!49 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 32, i64 0, i64 0, i32 0, metadata !50} ; [ DW_TAG_pointer_type ] -!50 = metadata !{i32 786451, metadata !24, metadata !"", metadata !24, i32 0, i64 224, i64 0, i32 0, i32 16, i32 0, metadata !51, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!42 = metadata !{i32 786445, metadata !153, metadata !40, metadata !"reserved", i32 307, i64 32, i64 32, i64 0, i32 0, metadata !43} ; [ DW_TAG_member ] +!43 = metadata !{i32 786468, null, metadata !0, metadata !"long unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!44 = metadata !{i32 786445, metadata !153, metadata !40, metadata !"Size", i32 307, i64 32, i64 32, i64 32, i32 0, metadata !43} ; [ DW_TAG_member ] +!45 = metadata !{i32 786445, metadata !153, metadata !40, metadata !"CopyFuncPtr", i32 307, i64 32, i64 32, i64 64, i32 0, metadata !46} ; [ DW_TAG_member ] +!46 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_pointer_type ] +!47 = metadata !{i32 786445, metadata !153, metadata !40, metadata !"DestroyFuncPtr", i32 307, i64 32, i64 32, i64 96, i32 0, metadata !46} ; [ DW_TAG_member ] +!48 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"mydata", i32 609, i64 32, i64 32, i64 160, i32 0, metadata !49} ; [ DW_TAG_member ] +!49 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 0, i64 0, i32 0, metadata !50} ; [ DW_TAG_pointer_type ] +!50 = metadata !{i32 786451, metadata !152, metadata !24, metadata !"", i32 0, i64 224, i64 0, i32 0, i32 16, i32 0, metadata !51, i32 0, i32 0} ; [ DW_TAG_structure_type ] !51 = metadata !{metadata !52, metadata !53, metadata !54, metadata !55, metadata !56, metadata !57, metadata !58} -!52 = metadata !{i32 786445, metadata !24, metadata !"__isa", metadata !24, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_member ] -!53 = metadata !{i32 786445, metadata !24, metadata !"__forwarding", metadata !24, i32 0, i64 32, i64 32, i64 32, i32 0, metadata !32} ; [ DW_TAG_member ] -!54 = metadata !{i32 786445, metadata !24, metadata !"__flags", metadata !24, i32 0, i64 32, i64 32, i64 64, i32 0, metadata !34} ; [ DW_TAG_member ] -!55 = metadata !{i32 786445, metadata !24, metadata !"__size", metadata !24, i32 0, i64 32, i64 32, i64 96, i32 0, metadata !34} ; [ DW_TAG_member ] -!56 = metadata !{i32 786445, metadata !24, metadata !"__copy_helper", metadata !24, i32 0, i64 32, i64 32, i64 128, i32 0, metadata !32} ; [ DW_TAG_member ] -!57 = metadata !{i32 786445, metadata !24, metadata !"__destroy_helper", metadata !24, i32 0, i64 32, i64 32, i64 160, i32 0, metadata !32} ; [ DW_TAG_member ] -!58 = metadata !{i32 786445, metadata !24, metadata !"mydata", metadata !24, i32 0, i64 32, i64 32, i64 192, i32 0, metadata !59} ; [ DW_TAG_member ] -!59 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !60} ; [ DW_TAG_pointer_type ] -!60 = metadata !{i32 786451, metadata !24, metadata !"UIMydata", metadata !61, i32 26, i64 128, i64 32, i32 0, i32 0, i32 0, metadata !62, i32 16, i32 0} ; [ DW_TAG_structure_type ] -!61 = metadata !{i32 786473, metadata !"header11.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] +!52 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__isa", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_member ] +!53 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__forwarding", i32 0, i64 32, i64 32, i64 32, i32 0, metadata !32} ; [ DW_TAG_member ] +!54 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__flags", i32 0, i64 32, i64 32, i64 64, i32 0, metadata !34} ; [ DW_TAG_member ] +!55 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__size", i32 0, i64 32, i64 32, i64 96, i32 0, metadata !34} ; [ DW_TAG_member ] +!56 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__copy_helper", i32 0, i64 32, i64 32, i64 128, i32 0, metadata !32} ; [ DW_TAG_member ] +!57 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__destroy_helper", i32 0, i64 32, i64 32, i64 160, i32 0, metadata !32} ; [ DW_TAG_member ] +!58 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"mydata", i32 0, i64 32, i64 32, i64 192, i32 0, metadata !59} ; [ DW_TAG_member ] +!59 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !60} ; [ DW_TAG_pointer_type ] +!60 = metadata !{i32 786451, metadata !154, metadata !24, metadata !"UIMydata", i32 26, i64 128, i64 32, i32 0, i32 0, i32 0, metadata !62, i32 16, i32 0} ; [ DW_TAG_structure_type ] +!61 = metadata !{i32 786473, metadata !154} ; [ DW_TAG_file_type ] !62 = metadata !{metadata !63, metadata !71, metadata !75, metadata !79} !63 = metadata !{i32 786460, metadata !60, null, metadata !61, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !64} ; [ DW_TAG_inheritance ] -!64 = metadata !{i32 786451, metadata !40, metadata !"NSO", metadata !65, i32 66, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !66, i32 16, i32 0} ; [ DW_TAG_structure_type ] -!65 = metadata !{i32 786473, metadata !"NSO.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] +!64 = metadata !{i32 786451, metadata !155, metadata !40, metadata !"NSO", i32 66, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !66, i32 16, i32 0} ; [ DW_TAG_structure_type ] +!65 = metadata !{i32 786473, metadata !155} ; [ DW_TAG_file_type ] !66 = metadata !{metadata !67} -!67 = metadata !{i32 786445, metadata !65, metadata !"isa", metadata !65, i32 67, i64 32, i64 32, i64 0, i32 2, metadata !68, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] +!67 = metadata !{i32 786445, metadata !155, metadata !65, metadata !"isa", i32 67, i64 32, i64 32, i64 0, i32 2, metadata !68, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] !68 = metadata !{i32 786454, metadata !0, metadata !"Class", metadata !40, i32 197, i64 0, i64 0, i64 0, i32 0, metadata !69} ; [ DW_TAG_typedef ] -!69 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !70} ; [ DW_TAG_pointer_type ] -!70 = metadata !{i32 786451, metadata !0, metadata !"objc_class", metadata !40, i32 0, i64 0, i64 0, i32 0, i32 4, i32 0, null, i32 0, i32 0} ; [ DW_TAG_structure_type ] -!71 = metadata !{i32 786445, metadata !61, metadata !"_mydataRef", metadata !61, i32 28, i64 32, i64 32, i64 32, i32 0, metadata !72, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] +!69 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !70} ; [ DW_TAG_pointer_type ] +!70 = metadata !{i32 786451, metadata !40, metadata !0, metadata !"objc_class", i32 0, i64 0, i64 0, i32 0, i32 4, i32 0, null, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!71 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"_mydataRef", i32 28, i64 32, i64 32, i64 32, i32 0, metadata !72, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] !72 = metadata !{i32 786454, metadata !0, metadata !"CFTypeRef", metadata !24, i32 313, i64 0, i64 0, i64 0, i32 0, metadata !73} ; [ DW_TAG_typedef ] -!73 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !74} ; [ DW_TAG_pointer_type ] -!74 = metadata !{i32 786470, metadata !0, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, null} ; [ DW_TAG_const_type ] -!75 = metadata !{i32 786445, metadata !61, metadata !"_scale", metadata !61, i32 29, i64 32, i64 32, i64 64, i32 0, metadata !76, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] +!73 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !74} ; [ DW_TAG_pointer_type ] +!74 = metadata !{i32 786470, null, metadata !0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null} ; [ DW_TAG_const_type ] +!75 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"_scale", i32 29, i64 32, i64 32, i64 64, i32 0, metadata !76, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] !76 = metadata !{i32 786454, metadata !0, metadata !"Float", metadata !77, i32 89, i64 0, i64 0, i64 0, i32 0, metadata !78} ; [ DW_TAG_typedef ] -!77 = metadata !{i32 786473, metadata !"header12.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] -!78 = metadata !{i32 786468, metadata !0, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!79 = metadata !{i32 786445, metadata !61, metadata !"_mydataFlags", metadata !61, i32 37, i64 8, i64 8, i64 96, i32 0, metadata !80, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] -!80 = metadata !{i32 786451, metadata !0, metadata !"", metadata !61, i32 30, i64 8, i64 8, i32 0, i32 0, i32 0, metadata !81, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!77 = metadata !{i32 786473, metadata !156} ; [ DW_TAG_file_type ] +!78 = metadata !{i32 786468, null, metadata !0, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!79 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"_mydataFlags", i32 37, i64 8, i64 8, i64 96, i32 0, metadata !80, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] +!80 = metadata !{i32 786451, metadata !154, metadata !0, metadata !"", i32 30, i64 8, i64 8, i32 0, i32 0, i32 0, metadata !81, i32 0, i32 0} ; [ DW_TAG_structure_type ] !81 = metadata !{metadata !82, metadata !84, metadata !85, metadata !86, metadata !87, metadata !88} -!82 = metadata !{i32 786445, metadata !61, metadata !"named", metadata !61, i32 31, i64 1, i64 32, i64 0, i32 0, metadata !83} ; [ DW_TAG_member ] -!83 = metadata !{i32 786468, metadata !0, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!84 = metadata !{i32 786445, metadata !61, metadata !"mydataO", metadata !61, i32 32, i64 3, i64 32, i64 1, i32 0, metadata !83} ; [ DW_TAG_member ] -!85 = metadata !{i32 786445, metadata !61, metadata !"cached", metadata !61, i32 33, i64 1, i64 32, i64 4, i32 0, metadata !83} ; [ DW_TAG_member ] -!86 = metadata !{i32 786445, metadata !61, metadata !"hasBeenCached", metadata !61, i32 34, i64 1, i64 32, i64 5, i32 0, metadata !83} ; [ DW_TAG_member ] -!87 = metadata !{i32 786445, metadata !61, metadata !"hasPattern", metadata !61, i32 35, i64 1, i64 32, i64 6, i32 0, metadata !83} ; [ DW_TAG_member ] -!88 = metadata !{i32 786445, metadata !61, metadata !"isCIMydata", metadata !61, i32 36, i64 1, i64 32, i64 7, i32 0, metadata !83} ; [ DW_TAG_member ] -!89 = metadata !{i32 786445, metadata !24, metadata !"self", metadata !24, i32 609, i64 32, i64 32, i64 192, i32 0, metadata !90} ; [ DW_TAG_member ] -!90 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !91} ; [ DW_TAG_pointer_type ] -!91 = metadata !{i32 786451, metadata !40, metadata !"MyWork", metadata !24, i32 36, i64 384, i64 32, i32 0, i32 0, i32 0, metadata !92, i32 16, i32 0} ; [ DW_TAG_structure_type ] +!82 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"named", i32 31, i64 1, i64 32, i64 0, i32 0, metadata !83} ; [ DW_TAG_member ] +!83 = metadata !{i32 786468, null, metadata !0, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!84 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"mydataO", i32 32, i64 3, i64 32, i64 1, i32 0, metadata !83} ; [ DW_TAG_member ] +!85 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"cached", i32 33, i64 1, i64 32, i64 4, i32 0, metadata !83} ; [ DW_TAG_member ] +!86 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"hasBeenCached", i32 34, i64 1, i64 32, i64 5, i32 0, metadata !83} ; [ DW_TAG_member ] +!87 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"hasPattern", i32 35, i64 1, i64 32, i64 6, i32 0, metadata !83} ; [ DW_TAG_member ] +!88 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"isCIMydata", i32 36, i64 1, i64 32, i64 7, i32 0, metadata !83} ; [ DW_TAG_member ] +!89 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"self", i32 609, i64 32, i64 32, i64 192, i32 0, metadata !90} ; [ DW_TAG_member ] +!90 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !91} ; [ DW_TAG_pointer_type ] +!91 = metadata !{i32 786451, metadata !152, metadata !40, metadata !"MyWork", i32 36, i64 384, i64 32, i32 0, i32 0, i32 0, metadata !92, i32 16, i32 0} ; [ DW_TAG_structure_type ] !92 = metadata !{metadata !93, metadata !98, metadata !101, metadata !107, metadata !123} !93 = metadata !{i32 786460, metadata !91, null, metadata !24, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !94} ; [ DW_TAG_inheritance ] -!94 = metadata !{i32 786451, metadata !40, metadata !"twork", metadata !95, i32 43, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !96, i32 16, i32 0} ; [ DW_TAG_structure_type ] -!95 = metadata !{i32 786473, metadata !"header13.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] +!94 = metadata !{i32 786451, metadata !157, metadata !40, metadata !"twork", i32 43, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !96, i32 16, i32 0} ; [ DW_TAG_structure_type ] +!95 = metadata !{i32 786473, metadata !157} ; [ DW_TAG_file_type ] !96 = metadata !{metadata !97} !97 = metadata !{i32 786460, metadata !94, null, metadata !95, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !64} ; [ DW_TAG_inheritance ] -!98 = metadata !{i32 786445, metadata !24, metadata !"_itemID", metadata !24, i32 38, i64 64, i64 32, i64 32, i32 1, metadata !99, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] +!98 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"_itemID", i32 38, i64 64, i64 32, i64 32, i32 1, metadata !99, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] !99 = metadata !{i32 786454, metadata !0, metadata !"uint64_t", metadata !40, i32 55, i64 0, i64 0, i64 0, i32 0, metadata !100} ; [ DW_TAG_typedef ] -!100 = metadata !{i32 786468, metadata !0, metadata !"long long unsigned int", null, i32 0, i64 64, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!101 = metadata !{i32 786445, metadata !24, metadata !"_library", metadata !24, i32 39, i64 32, i64 32, i64 96, i32 1, metadata !102, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] -!102 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !103} ; [ DW_TAG_pointer_type ] -!103 = metadata !{i32 786451, metadata !40, metadata !"MyLibrary2", metadata !104, i32 22, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !105, i32 16, i32 0} ; [ DW_TAG_structure_type ] -!104 = metadata !{i32 786473, metadata !"header14.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] +!100 = metadata !{i32 786468, null, metadata !0, metadata !"long long unsigned int", i32 0, i64 64, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!101 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"_library", i32 39, i64 32, i64 32, i64 96, i32 1, metadata !102, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] +!102 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !103} ; [ DW_TAG_pointer_type ] +!103 = metadata !{i32 786451, metadata !158, metadata !40, metadata !"MyLibrary2", i32 22, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !105, i32 16, i32 0} ; [ DW_TAG_structure_type ] +!104 = metadata !{i32 786473, metadata !158} ; [ DW_TAG_file_type ] !105 = metadata !{metadata !106} !106 = metadata !{i32 786460, metadata !103, null, metadata !104, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !64} ; [ DW_TAG_inheritance ] -!107 = metadata !{i32 786445, metadata !24, metadata !"_bounds", metadata !24, i32 40, i64 128, i64 32, i64 128, i32 1, metadata !108, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] +!107 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"_bounds", i32 40, i64 128, i64 32, i64 128, i32 1, metadata !108, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] !108 = metadata !{i32 786454, metadata !0, metadata !"CR", metadata !40, i32 33, i64 0, i64 0, i64 0, i32 0, metadata !109} ; [ DW_TAG_typedef ] -!109 = metadata !{i32 786451, metadata !0, metadata !"CR", metadata !77, i32 29, i64 128, i64 32, i32 0, i32 0, i32 0, metadata !110, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!109 = metadata !{i32 786451, metadata !156, metadata !0, metadata !"CR", i32 29, i64 128, i64 32, i32 0, i32 0, i32 0, metadata !110, i32 0, i32 0} ; [ DW_TAG_structure_type ] !110 = metadata !{metadata !111, metadata !117} -!111 = metadata !{i32 786445, metadata !77, metadata !"origin", metadata !77, i32 30, i64 64, i64 32, i64 0, i32 0, metadata !112} ; [ DW_TAG_member ] +!111 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"origin", i32 30, i64 64, i64 32, i64 0, i32 0, metadata !112} ; [ DW_TAG_member ] !112 = metadata !{i32 786454, metadata !0, metadata !"CP", metadata !77, i32 17, i64 0, i64 0, i64 0, i32 0, metadata !113} ; [ DW_TAG_typedef ] -!113 = metadata !{i32 786451, metadata !0, metadata !"CP", metadata !77, i32 13, i64 64, i64 32, i32 0, i32 0, i32 0, metadata !114, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!113 = metadata !{i32 786451, metadata !156, metadata !0, metadata !"CP", i32 13, i64 64, i64 32, i32 0, i32 0, i32 0, metadata !114, i32 0, i32 0} ; [ DW_TAG_structure_type ] !114 = metadata !{metadata !115, metadata !116} -!115 = metadata !{i32 786445, metadata !77, metadata !"x", metadata !77, i32 14, i64 32, i64 32, i64 0, i32 0, metadata !76} ; [ DW_TAG_member ] -!116 = metadata !{i32 786445, metadata !77, metadata !"y", metadata !77, i32 15, i64 32, i64 32, i64 32, i32 0, metadata !76} ; [ DW_TAG_member ] -!117 = metadata !{i32 786445, metadata !77, metadata !"size", metadata !77, i32 31, i64 64, i64 32, i64 64, i32 0, metadata !118} ; [ DW_TAG_member ] +!115 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"x", i32 14, i64 32, i64 32, i64 0, i32 0, metadata !76} ; [ DW_TAG_member ] +!116 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"y", i32 15, i64 32, i64 32, i64 32, i32 0, metadata !76} ; [ DW_TAG_member ] +!117 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"size", i32 31, i64 64, i64 32, i64 64, i32 0, metadata !118} ; [ DW_TAG_member ] !118 = metadata !{i32 786454, metadata !0, metadata !"Size", metadata !77, i32 25, i64 0, i64 0, i64 0, i32 0, metadata !119} ; [ DW_TAG_typedef ] -!119 = metadata !{i32 786451, metadata !0, metadata !"Size", metadata !77, i32 21, i64 64, i64 32, i32 0, i32 0, i32 0, metadata !120, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!119 = metadata !{i32 786451, metadata !156, metadata !0, metadata !"Size", i32 21, i64 64, i64 32, i32 0, i32 0, i32 0, metadata !120, i32 0, i32 0} ; [ DW_TAG_structure_type ] !120 = metadata !{metadata !121, metadata !122} -!121 = metadata !{i32 786445, metadata !77, metadata !"width", metadata !77, i32 22, i64 32, i64 32, i64 0, i32 0, metadata !76} ; [ DW_TAG_member ] -!122 = metadata !{i32 786445, metadata !77, metadata !"height", metadata !77, i32 23, i64 32, i64 32, i64 32, i32 0, metadata !76} ; [ DW_TAG_member ] -!123 = metadata !{i32 786445, metadata !24, metadata !"_data", metadata !24, i32 40, i64 128, i64 32, i64 256, i32 1, metadata !108, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] -!124 = metadata !{i32 786445, metadata !24, metadata !"semi", metadata !24, i32 609, i64 32, i64 32, i64 224, i32 0, metadata !125} ; [ DW_TAG_member ] +!121 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"width", i32 22, i64 32, i64 32, i64 0, i32 0, metadata !76} ; [ DW_TAG_member ] +!122 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"height", i32 23, i64 32, i64 32, i64 32, i32 0, metadata !76} ; [ DW_TAG_member ] +!123 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"_data", i32 40, i64 128, i64 32, i64 256, i32 1, metadata !108, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] +!124 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"semi", i32 609, i64 32, i64 32, i64 224, i32 0, metadata !125} ; [ DW_TAG_member ] !125 = metadata !{i32 786454, metadata !0, metadata !"d_t", metadata !24, i32 35, i64 0, i64 0, i64 0, i32 0, metadata !126} ; [ DW_TAG_typedef ] -!126 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !127} ; [ DW_TAG_pointer_type ] -!127 = metadata !{i32 786451, metadata !0, metadata !"my_struct", metadata !128, i32 49, i64 0, i64 0, i32 0, i32 4, i32 0, null, i32 0, i32 0} ; [ DW_TAG_structure_type ] -!128 = metadata !{i32 786473, metadata !"header15.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ] +!126 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !127} ; [ DW_TAG_pointer_type ] +!127 = metadata !{i32 786451, metadata !159, metadata !0, metadata !"my_struct", i32 49, i64 0, i64 0, i32 0, i32 4, i32 0, null, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!128 = metadata !{i32 786473, metadata !159} ; [ DW_TAG_file_type ] !129 = metadata !{i32 609, i32 144, metadata !23, null} !130 = metadata !{i32 786689, metadata !23, metadata !"loadedMydata", metadata !24, i32 33555041, metadata !59, i32 0, null} ; [ DW_TAG_arg_variable ] !131 = metadata !{i32 609, i32 155, metadata !23, null} @@ -243,3 +241,18 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !144 = metadata !{i32 612, i32 17, metadata !142, null} !145 = metadata !{i32 613, i32 17, metadata !142, null} !146 = metadata !{i32 615, i32 13, metadata !142, null} +!147 = metadata !{metadata !1, metadata !1, metadata !5, metadata !5, metadata !9, metadata !14, metadata !19, metadata !19, metadata !14, metadata !14, metadata !14, metadata !19, metadata !19, metadata !19} +!148 = metadata !{metadata !23} +!149 = metadata !{metadata !"header3.h", metadata !"/Volumes/Sandbox/llvm"} +!150 = metadata !{metadata !"Private.h", metadata !"/Volumes/Sandbox/llvm"} +!151 = metadata !{metadata !"header4.h", metadata !"/Volumes/Sandbox/llvm"} +!152 = metadata !{metadata !"MyLibrary.m", metadata !"/Volumes/Sandbox/llvm"} +!153 = metadata !{metadata !"MyLibrary.i", metadata !"/Volumes/Sandbox/llvm"} +!154 = metadata !{metadata !"header11.h", metadata !"/Volumes/Sandbox/llvm"} +!155 = metadata !{metadata !"NSO.h", metadata !"/Volumes/Sandbox/llvm"} +!156 = metadata !{metadata !"header12.h", metadata !"/Volumes/Sandbox/llvm"} +!157 = metadata !{metadata !"header13.h", metadata !"/Volumes/Sandbox/llvm"} +!158 = metadata !{metadata !"header14.h", metadata !"/Volumes/Sandbox/llvm"} +!159 = metadata !{metadata !"header15.h", metadata !"/Volumes/Sandbox/llvm"} +!160 = metadata !{metadata !"header.h", metadata !"/Volumes/Sandbox/llvm"} +!161 = metadata !{metadata !"header2.h", metadata !"/Volumes/Sandbox/llvm"} diff --git a/test/CodeGen/ARM/debug-info-branch-folding.ll b/test/CodeGen/ARM/debug-info-branch-folding.ll index f241c069c3..95e6cf2554 100644 --- a/test/CodeGen/ARM/debug-info-branch-folding.ll +++ b/test/CodeGen/ARM/debug-info-branch-folding.ll @@ -38,58 +38,59 @@ declare i32 @printf(i8* nocapture, ...) nounwind declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -!50 = metadata !{metadata !0, metadata !10, metadata !14} -!51 = metadata !{metadata !18} -!52 = metadata !{metadata !19, metadata !20, metadata !24, metadata !26, metadata !27, metadata !28, metadata !29} -!53 = metadata !{metadata !30} - !0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null, null, metadata !51, i32 0} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"build2.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"build2.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 129915)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !50, null, null} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!1 = metadata !{i32 786473, metadata !54} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !54, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, null, null, metadata !50, null, null} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 786454, metadata !2, metadata !"v4f32", metadata !1, i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] +!5 = metadata !{i32 786454, metadata !54, metadata !2, metadata !"v4f32", i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] !6 = metadata !{i32 786691, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_vector_type ] -!7 = metadata !{i32 786468, metadata !2, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 786468, null, metadata !2, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] !8 = metadata !{metadata !9} !9 = metadata !{i32 786465, i64 0, i64 4} ; [ DW_TAG_subrange_type ] !10 = metadata !{i32 786478, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**, i1)* @main, null, null, metadata !52, i32 0} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!11 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !12 = metadata !{metadata !13} -!13 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!13 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !14 = metadata !{i32 786478, i32 0, metadata !15, metadata !"printFV", metadata !"printFV", metadata !"", metadata !15, i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null, null, metadata !53, i32 0} ; [ DW_TAG_subprogram ] -!15 = metadata !{i32 786473, metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!16 = metadata !{i32 786453, metadata !15, metadata !"", metadata !15, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !17, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!15 = metadata !{i32 786473, metadata !55} ; [ DW_TAG_file_type ] +!16 = metadata !{i32 786453, metadata !55, metadata !15, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !17, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !17 = metadata !{null} !18 = metadata !{i32 786689, metadata !0, metadata !"a", metadata !1, i32 16777219, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] !19 = metadata !{i32 786689, metadata !10, metadata !"argc", metadata !1, i32 16777275, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ] !20 = metadata !{i32 786689, metadata !10, metadata !"argv", metadata !1, i32 33554491, metadata !21, i32 0, null} ; [ DW_TAG_arg_variable ] -!21 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ] -!22 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] -!23 = metadata !{i32 786468, metadata !2, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!21 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ] +!22 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] +!23 = metadata !{i32 786468, null, metadata !2, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] !24 = metadata !{i32 786688, metadata !25, metadata !"i", metadata !1, i32 60, metadata !13, i32 0, null} ; [ DW_TAG_auto_variable ] -!25 = metadata !{i32 786443, metadata !10, i32 59, i32 33, metadata !1, i32 14} ; [ DW_TAG_lexical_block ] +!25 = metadata !{i32 786443, metadata !1, metadata !10, i32 59, i32 33, i32 14} ; [ DW_TAG_lexical_block ] !26 = metadata !{i32 786688, metadata !25, metadata !"j", metadata !1, i32 60, metadata !13, i32 0, null} ; [ DW_TAG_auto_variable ] !27 = metadata !{i32 786688, metadata !25, metadata !"x", metadata !1, i32 61, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] !28 = metadata !{i32 786688, metadata !25, metadata !"y", metadata !1, i32 62, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] !29 = metadata !{i32 786688, metadata !25, metadata !"z", metadata !1, i32 63, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] !30 = metadata !{i32 786689, metadata !14, metadata !"F", metadata !15, i32 16777257, metadata !31, i32 0, null} ; [ DW_TAG_arg_variable ] -!31 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_pointer_type ] -!32 = metadata !{i32 786454, metadata !2, metadata !"FV", metadata !15, i32 25, i64 0, i64 0, i64 0, i32 0, metadata !33} ; [ DW_TAG_typedef ] -!33 = metadata !{i32 786455, metadata !2, metadata !"", metadata !15, i32 22, i64 128, i64 128, i64 0, i32 0, i32 0, metadata !34, i32 0, i32 0} ; [ DW_TAG_union_type ] +!31 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_pointer_type ] +!32 = metadata !{i32 786454, metadata !55, metadata !2, metadata !"FV", i32 25, i64 0, i64 0, i64 0, i32 0, metadata !33} ; [ DW_TAG_typedef ] +!33 = metadata !{i32 786455, metadata !55, metadata !2, metadata !"", i32 22, i64 128, i64 128, i64 0, i32 0, i32 0, metadata !34, i32 0, i32 0} ; [ DW_TAG_union_type ] !34 = metadata !{metadata !35, metadata !37} -!35 = metadata !{i32 786445, metadata !15, metadata !"V", metadata !15, i32 23, i64 128, i64 128, i64 0, i32 0, metadata !36} ; [ DW_TAG_member ] -!36 = metadata !{i32 786454, metadata !2, metadata !"v4sf", metadata !15, i32 3, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] -!37 = metadata !{i32 786445, metadata !15, metadata !"A", metadata !15, i32 24, i64 128, i64 32, i64 0, i32 0, metadata !38} ; [ DW_TAG_member ] -!38 = metadata !{i32 786433, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 32, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_array_type ] +!35 = metadata !{i32 786445, metadata !55, metadata !15, metadata !"V", i32 23, i64 128, i64 128, i64 0, i32 0, metadata !36} ; [ DW_TAG_member ] +!36 = metadata !{i32 786454, metadata !55, metadata !2, metadata !"v4sf", i32 3, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] +!37 = metadata !{i32 786445, metadata !55, metadata !15, metadata !"A", i32 24, i64 128, i64 32, i64 0, i32 0, metadata !38} ; [ DW_TAG_member ] +!38 = metadata !{i32 786433, null, metadata !2, metadata !"", i32 0, i64 128, i64 32, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_array_type ] !39 = metadata !{i32 79, i32 7, metadata !40, null} -!40 = metadata !{i32 786443, metadata !41, i32 75, i32 35, metadata !1, i32 18} ; [ DW_TAG_lexical_block ] -!41 = metadata !{i32 786443, metadata !42, i32 75, i32 5, metadata !1, i32 17} ; [ DW_TAG_lexical_block ] -!42 = metadata !{i32 786443, metadata !43, i32 71, i32 32, metadata !1, i32 16} ; [ DW_TAG_lexical_block ] -!43 = metadata !{i32 786443, metadata !25, i32 71, i32 3, metadata !1, i32 15} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 786443, metadata !1, metadata !41, i32 75, i32 35, i32 18} ; [ DW_TAG_lexical_block ] +!41 = metadata !{i32 786443, metadata !1, metadata !42, i32 75, i32 5, i32 17} ; [ DW_TAG_lexical_block ] +!42 = metadata !{i32 786443, metadata !1, metadata !43, i32 71, i32 32, i32 16} ; [ DW_TAG_lexical_block ] +!43 = metadata !{i32 786443, metadata !1, metadata !25, i32 71, i32 3, i32 15} ; [ DW_TAG_lexical_block ] !44 = metadata !{i32 75, i32 5, metadata !42, null} !45 = metadata !{i32 42, i32 2, metadata !46, metadata !48} -!46 = metadata !{i32 786443, metadata !47, i32 42, i32 2, metadata !15, i32 20} ; [ DW_TAG_lexical_block ] -!47 = metadata !{i32 786443, metadata !14, i32 41, i32 28, metadata !15, i32 19} ; [ DW_TAG_lexical_block ] +!46 = metadata !{i32 786443, metadata !15, metadata !47, i32 42, i32 2, i32 20} ; [ DW_TAG_lexical_block ] +!47 = metadata !{i32 786443, metadata !15, metadata !14, i32 41, i32 28, i32 19} ; [ DW_TAG_lexical_block ] !48 = metadata !{i32 95, i32 3, metadata !25, null} !49 = metadata !{i32 99, i32 3, metadata !25, null} +!50 = metadata !{metadata !0, metadata !10, metadata !14} +!51 = metadata !{metadata !18} +!52 = metadata !{metadata !19, metadata !20, metadata !24, metadata !26, metadata !27, metadata !28, metadata !29} +!53 = metadata !{metadata !30} +!54 = metadata !{metadata !"build2.c", metadata !"/private/tmp"} +!55 = metadata !{metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", metadata !"/private/tmp"} diff --git a/test/CodeGen/ARM/debug-info-d16-reg.ll b/test/CodeGen/ARM/debug-info-d16-reg.ll index 80096906e5..e3e4d06893 100644 --- a/test/CodeGen/ARM/debug-info-d16-reg.ll +++ b/test/CodeGen/ARM/debug-info-d16-reg.ll @@ -57,22 +57,18 @@ entry: declare i32 @puts(i8* nocapture) nounwind !llvm.dbg.cu = !{!2} -!42 = metadata !{metadata !0, metadata !9, metadata !10} -!43 = metadata !{metadata !16, metadata !17, metadata !18} -!44 = metadata !{metadata !19, metadata !20, metadata !21} -!45 = metadata !{metadata !22, metadata !23, metadata !24} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"printer", metadata !"printer", metadata !"printer", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @printer, null, null, metadata !43, i32 12} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"a.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 1, metadata !"/tmp/a.c", metadata !"/tmp", metadata !"(LLVM build 00)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !42, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786478, metadata !1, metadata !"printer", metadata !"printer", metadata !"printer", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @printer, null, null, metadata !43, i32 12} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !46} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"(LLVM build 00)", i1 true, metadata !"", i32 0, null, null, metadata !42, null, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5, metadata !6, metadata !7, metadata !8} !5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !6 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] !7 = metadata !{i32 786468, metadata !1, metadata !"double", metadata !1, i32 0, i64 64, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] !8 = metadata !{i32 786468, metadata !1, metadata !"unsigned char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] -!9 = metadata !{i32 786478, i32 0, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"inlineprinter", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @inlineprinter, null, null, metadata !44, i32 5} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 786478, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 18, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !45, i32 18} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 786478, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"inlineprinter", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @inlineprinter, null, null, metadata !44, i32 5} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 18, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !45, i32 18} ; [ DW_TAG_subprogram ] !11 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] !12 = metadata !{metadata !5, metadata !5, metadata !13} !13 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ] @@ -87,14 +83,14 @@ declare i32 @puts(i8* nocapture) nounwind !22 = metadata !{i32 786689, metadata !10, metadata !"argc", metadata !1, i32 17, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !23 = metadata !{i32 786689, metadata !10, metadata !"argv", metadata !1, i32 17, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ] !24 = metadata !{i32 786688, metadata !25, metadata !"dval", metadata !1, i32 19, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ] -!25 = metadata !{i32 786443, metadata !10, i32 18, i32 0, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!25 = metadata !{i32 786443, metadata !1, metadata !10, i32 18, i32 0, i32 2} ; [ DW_TAG_lexical_block ] !26 = metadata !{i32 4, i32 0, metadata !9, null} !27 = metadata !{i32 6, i32 0, metadata !28, null} -!28 = metadata !{i32 786443, metadata !9, i32 5, i32 0, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 786443, metadata !1, metadata !9, i32 5, i32 0, i32 1} ; [ DW_TAG_lexical_block ] !29 = metadata !{i32 7, i32 0, metadata !28, null} !30 = metadata !{i32 11, i32 0, metadata !0, null} !31 = metadata !{i32 13, i32 0, metadata !32, null} -!32 = metadata !{i32 786443, metadata !0, i32 12, i32 0, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!32 = metadata !{i32 786443, metadata !1, metadata !0, i32 12, i32 0, i32 0} ; [ DW_TAG_lexical_block ] !33 = metadata !{i32 14, i32 0, metadata !32, null} !34 = metadata !{i32 17, i32 0, metadata !10, null} !35 = metadata !{i32 19, i32 0, metadata !25, null} @@ -104,3 +100,8 @@ declare i32 @puts(i8* nocapture) nounwind !39 = metadata !{i32 6, i32 0, metadata !28, metadata !37} !40 = metadata !{i32 22, i32 0, metadata !25, null} !41 = metadata !{i32 23, i32 0, metadata !25, null} +!42 = metadata !{metadata !0, metadata !9, metadata !10} +!43 = metadata !{metadata !16, metadata !17, metadata !18} +!44 = metadata !{metadata !19, metadata !20, metadata !21} +!45 = metadata !{metadata !22, metadata !23, metadata !24} +!46 = metadata !{metadata !"a.c", metadata !"/tmp/"} diff --git a/test/CodeGen/ARM/debug-info-qreg.ll b/test/CodeGen/ARM/debug-info-qreg.ll index 89010dd364..038c2296cd 100644 --- a/test/CodeGen/ARM/debug-info-qreg.ll +++ b/test/CodeGen/ARM/debug-info-qreg.ll @@ -36,58 +36,60 @@ declare i32 @printf(i8* nocapture, ...) nounwind declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!2} -!50 = metadata !{metadata !0, metadata !10, metadata !14} -!51 = metadata !{metadata !18} -!52 = metadata !{metadata !19, metadata !20, metadata !24, metadata !26, metadata !27, metadata !28, metadata !29} -!53 = metadata !{metadata !30} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null, null, metadata !51, i32 3} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"build2.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"build2.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 129915)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !50, null, null} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null, null, metadata !51, i32 3} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !54} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !54, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, null, null, metadata !50, null, null} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 786454, metadata !2, metadata !"v4f32", metadata !1, i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] +!5 = metadata !{i32 786454, metadata !54, metadata !2, metadata !"v4f32", i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] !6 = metadata !{i32 786691, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_vector_type ] -!7 = metadata !{i32 786468, metadata !2, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 786468, null, metadata !2, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] !8 = metadata !{metadata !9} !9 = metadata !{i32 786465, i64 0, i64 4} ; [ DW_TAG_subrange_type ] -!10 = metadata !{i32 786478, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !52, i32 59} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!10 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !52, i32 59} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !12 = metadata !{metadata !13} -!13 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{i32 786478, i32 0, metadata !15, metadata !"printFV", metadata !"printFV", metadata !"", metadata !15, i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null, null, metadata !53, i32 41} ; [ DW_TAG_subprogram ] -!15 = metadata !{i32 786473, metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!16 = metadata !{i32 786453, metadata !15, metadata !"", metadata !15, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !17, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!13 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 786478, metadata !15, metadata !"printFV", metadata !"printFV", metadata !"", metadata !15, i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null, null, metadata !53, i32 41} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 786473, metadata !55} ; [ DW_TAG_file_type ] +!16 = metadata !{i32 786453, metadata !55, metadata !15, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !17, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !17 = metadata !{null} !18 = metadata !{i32 786689, metadata !0, metadata !"a", metadata !1, i32 16777219, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] !19 = metadata !{i32 786689, metadata !10, metadata !"argc", metadata !1, i32 16777275, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ] !20 = metadata !{i32 786689, metadata !10, metadata !"argv", metadata !1, i32 33554491, metadata !21, i32 0, null} ; [ DW_TAG_arg_variable ] -!21 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ] -!22 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] -!23 = metadata !{i32 786468, metadata !2, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!21 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ] +!22 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] +!23 = metadata !{i32 786468, null, metadata !2, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] !24 = metadata !{i32 786688, metadata !25, metadata !"i", metadata !1, i32 60, metadata !13, i32 0, null} ; [ DW_TAG_auto_variable ] -!25 = metadata !{i32 786443, metadata !10, i32 59, i32 33, metadata !1, i32 14} ; [ DW_TAG_lexical_block ] +!25 = metadata !{i32 786443, metadata !1, metadata !10, i32 59, i32 33, i32 14} ; [ DW_TAG_lexical_block ] !26 = metadata !{i32 786688, metadata !25, metadata !"j", metadata !1, i32 60, metadata !13, i32 0, null} ; [ DW_TAG_auto_variable ] !27 = metadata !{i32 786688, metadata !25, metadata !"x", metadata !1, i32 61, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] !28 = metadata !{i32 786688, metadata !25, metadata !"y", metadata !1, i32 62, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] !29 = metadata !{i32 786688, metadata !25, metadata !"z", metadata !1, i32 63, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] !30 = metadata !{i32 786689, metadata !14, metadata !"F", metadata !15, i32 16777257, metadata !31, i32 0, null} ; [ DW_TAG_arg_variable ] -!31 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_pointer_type ] -!32 = metadata !{i32 786454, metadata !2, metadata !"FV", metadata !15, i32 25, i64 0, i64 0, i64 0, i32 0, metadata !33} ; [ DW_TAG_typedef ] -!33 = metadata !{i32 786455, metadata !2, metadata !"", metadata !15, i32 22, i64 128, i64 128, i64 0, i32 0, i32 0, metadata !34, i32 0, i32 0} ; [ DW_TAG_union_type ] +!31 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_pointer_type ] +!32 = metadata !{i32 786454, metadata !55, metadata !2, metadata !"FV", i32 25, i64 0, i64 0, i64 0, i32 0, metadata !33} ; [ DW_TAG_typedef ] +!33 = metadata !{i32 786455, metadata !55, metadata !2, metadata !"", i32 22, i64 128, i64 128, i64 0, i32 0, i32 0, metadata !34, i32 0, i32 0} ; [ DW_TAG_union_type ] !34 = metadata !{metadata !35, metadata !37} -!35 = metadata !{i32 786445, metadata !15, metadata !"V", metadata !15, i32 23, i64 128, i64 128, i64 0, i32 0, metadata !36} ; [ DW_TAG_member ] -!36 = metadata !{i32 786454, metadata !2, metadata !"v4sf", metadata !15, i32 3, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] -!37 = metadata !{i32 786445, metadata !15, metadata !"A", metadata !15, i32 24, i64 128, i64 32, i64 0, i32 0, metadata !38} ; [ DW_TAG_member ] -!38 = metadata !{i32 786433, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 32, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_array_type ] +!35 = metadata !{i32 786445, metadata !55, metadata !15, metadata !"V", i32 23, i64 128, i64 128, i64 0, i32 0, metadata !36} ; [ DW_TAG_member ] +!36 = metadata !{i32 786454, metadata !55, metadata !2, metadata !"v4sf", i32 3, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] +!37 = metadata !{i32 786445, metadata !55, metadata !15, metadata !"A", i32 24, i64 128, i64 32, i64 0, i32 0, metadata !38} ; [ DW_TAG_member ] +!38 = metadata !{i32 786433, null, metadata !2, metadata !"", i32 0, i64 128, i64 32, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_array_type ] !39 = metadata !{i32 79, i32 7, metadata !40, null} -!40 = metadata !{i32 786443, metadata !41, i32 75, i32 35, metadata !1, i32 18} ; [ DW_TAG_lexical_block ] -!41 = metadata !{i32 786443, metadata !42, i32 75, i32 5, metadata !1, i32 17} ; [ DW_TAG_lexical_block ] -!42 = metadata !{i32 786443, metadata !43, i32 71, i32 32, metadata !1, i32 16} ; [ DW_TAG_lexical_block ] -!43 = metadata !{i32 786443, metadata !25, i32 71, i32 3, metadata !1, i32 15} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 786443, metadata !1, metadata !41, i32 75, i32 35, i32 18} ; [ DW_TAG_lexical_block ] +!41 = metadata !{i32 786443, metadata !1, metadata !42, i32 75, i32 5, i32 17} ; [ DW_TAG_lexical_block ] +!42 = metadata !{i32 786443, metadata !1, metadata !43, i32 71, i32 32, i32 16} ; [ DW_TAG_lexical_block ] +!43 = metadata !{i32 786443, metadata !1, metadata !25, i32 71, i32 3, i32 15} ; [ DW_TAG_lexical_block ] !44 = metadata !{i32 75, i32 5, metadata !42, null} !45 = metadata !{i32 42, i32 2, metadata !46, metadata !48} -!46 = metadata !{i32 786443, metadata !47, i32 42, i32 2, metadata !15, i32 20} ; [ DW_TAG_lexical_block ] -!47 = metadata !{i32 786443, metadata !14, i32 41, i32 28, metadata !15, i32 19} ; [ DW_TAG_lexical_block ] +!46 = metadata !{i32 786443, metadata !15, metadata !47, i32 42, i32 2, i32 20} ; [ DW_TAG_lexical_block ] +!47 = metadata !{i32 786443, metadata !15, metadata !14, i32 41, i32 28, i32 19} ; [ DW_TAG_lexical_block ] !48 = metadata !{i32 95, i32 3, metadata !25, null} !49 = metadata !{i32 99, i32 3, metadata !25, null} +!50 = metadata !{metadata !0, metadata !10, metadata !14} +!51 = metadata !{metadata !18} +!52 = metadata !{metadata !19, metadata !20, metadata !24, metadata !26, metadata !27, metadata !28, metadata !29} +!53 = metadata !{metadata !30} +!54 = metadata !{metadata !"build2.c", metadata !"/private/tmp"} +!55 = metadata !{metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", metadata !"/private/tmp"} diff --git a/test/CodeGen/ARM/debug-info-s16-reg.ll b/test/CodeGen/ARM/debug-info-s16-reg.ll index 68fabee15f..f3af0b93c6 100644 --- a/test/CodeGen/ARM/debug-info-s16-reg.ll +++ b/test/CodeGen/ARM/debug-info-s16-reg.ll @@ -62,19 +62,15 @@ declare i32 @puts(i8* nocapture) nounwind optsize declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!2} -!47 = metadata !{metadata !0, metadata !6, metadata !7} -!48 = metadata !{metadata !8, metadata !10, metadata !12} -!49 = metadata !{metadata !14, metadata !15, metadata !16} -!50 = metadata !{metadata !17, metadata !18, metadata !22} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @inlineprinter, null, null, metadata !48, i32 5} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"a.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"a.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 129915)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !47, null, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786478, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @inlineprinter, null, null, metadata !48, i32 5} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !51} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, null, null, metadata !47, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 786478, i32 0, metadata !1, metadata !"printer", metadata !"printer", metadata !"", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @printer, null, null, metadata !49, i32 12} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 786478, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !50, i32 18} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 786478, metadata !1, metadata !"printer", metadata !"printer", metadata !"", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @printer, null, null, metadata !49, i32 12} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !50, i32 18} ; [ DW_TAG_subprogram ] !8 = metadata !{i32 786689, metadata !0, metadata !"ptr", metadata !1, i32 16777220, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ] !9 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] !10 = metadata !{i32 786689, metadata !0, metadata !"val", metadata !1, i32 33554436, metadata !11, i32 0, null} ; [ DW_TAG_arg_variable ] @@ -90,18 +86,18 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !20 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !21} ; [ DW_TAG_pointer_type ] !21 = metadata !{i32 786468, metadata !2, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] !22 = metadata !{i32 786688, metadata !23, metadata !"dval", metadata !1, i32 19, metadata !11, i32 0, null} ; [ DW_TAG_auto_variable ] -!23 = metadata !{i32 786443, metadata !7, i32 18, i32 1, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!23 = metadata !{i32 786443, metadata !1, metadata !7, i32 18, i32 1, i32 2} ; [ DW_TAG_lexical_block ] !24 = metadata !{i32 4, i32 22, metadata !0, null} !25 = metadata !{i32 4, i32 33, metadata !0, null} !26 = metadata !{i32 4, i32 52, metadata !0, null} !27 = metadata !{i32 6, i32 3, metadata !28, null} -!28 = metadata !{i32 786443, metadata !0, i32 5, i32 1, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 786443, metadata !1, metadata !0, i32 5, i32 1, i32 0} ; [ DW_TAG_lexical_block ] !29 = metadata !{i32 7, i32 3, metadata !28, null} !30 = metadata !{i32 11, i32 42, metadata !6, null} !31 = metadata !{i32 11, i32 53, metadata !6, null} !32 = metadata !{i32 11, i32 72, metadata !6, null} !33 = metadata !{i32 13, i32 3, metadata !34, null} -!34 = metadata !{i32 786443, metadata !6, i32 12, i32 1, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!34 = metadata !{i32 786443, metadata !1, metadata !6, i32 12, i32 1, i32 1} ; [ DW_TAG_lexical_block ] !35 = metadata !{i32 14, i32 3, metadata !34, null} !36 = metadata !{i32 17, i32 15, metadata !7, null} !37 = metadata !{i32 17, i32 28, metadata !7, null} @@ -114,3 +110,8 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !44 = metadata !{i32 6, i32 3, metadata !28, metadata !40} !45 = metadata !{i32 22, i32 3, metadata !23, null} !46 = metadata !{i32 23, i32 1, metadata !23, null} +!47 = metadata !{metadata !0, metadata !6, metadata !7} +!48 = metadata !{metadata !8, metadata !10, metadata !12} +!49 = metadata !{metadata !14, metadata !15, metadata !16} +!50 = metadata !{metadata !17, metadata !18, metadata !22} +!51 = metadata !{metadata !"a.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/ARM/debug-info-sreg2.ll b/test/CodeGen/ARM/debug-info-sreg2.ll index e40d617619..ae02a245b4 100644 --- a/test/CodeGen/ARM/debug-info-sreg2.ll +++ b/test/CodeGen/ARM/debug-info-sreg2.ll @@ -40,22 +40,23 @@ declare float @_Z2f3f(float) optsize declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!16 = metadata !{metadata !1} -!17 = metadata !{metadata !5, metadata !8} -!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"k.cc", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 130845)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !16, null, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3foov", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @_Z3foov, null, null, metadata !17, i32 5} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 786473, metadata !"k.cc", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] +!0 = metadata !{i32 786449, i32 4, metadata !2, metadata !"clang version 3.0 (trunk 130845)", i1 true, metadata !"", i32 0, null, null, metadata !16, null, null} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3foov", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @_Z3foov, null, null, metadata !17, i32 5} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !18} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{null} !5 = metadata !{i32 786688, metadata !6, metadata !"k", metadata !2, i32 6, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ] -!6 = metadata !{i32 786443, metadata !1, i32 5, i32 12, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!6 = metadata !{i32 786443, metadata !2, metadata !1, i32 5, i32 12, i32 0} ; [ DW_TAG_lexical_block ] !7 = metadata !{i32 786468, metadata !0, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] !8 = metadata !{i32 786688, metadata !9, metadata !"y", metadata !2, i32 8, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ] -!9 = metadata !{i32 786443, metadata !10, i32 7, i32 25, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] -!10 = metadata !{i32 786443, metadata !6, i32 7, i32 3, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 786443, metadata !2, metadata !10, i32 7, i32 25, i32 2} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 786443, metadata !2, metadata !6, i32 7, i32 3, i32 1} ; [ DW_TAG_lexical_block ] !11 = metadata !{i32 6, i32 18, metadata !6, null} !12 = metadata !{i32 7, i32 3, metadata !6, null} !13 = metadata !{i32 8, i32 20, metadata !9, null} !14 = metadata !{i32 7, i32 20, metadata !10, null} !15 = metadata !{i32 10, i32 1, metadata !6, null} +!16 = metadata !{metadata !1} +!17 = metadata !{metadata !5, metadata !8} +!18 = metadata !{metadata !"k.cc", metadata !"/private/tmp"} diff --git a/test/CodeGen/ARM/fadds.ll b/test/CodeGen/ARM/fadds.ll index 48ef5ed88f..c7e2f5d094 100644 --- a/test/CodeGen/ARM/fadds.ll +++ b/test/CodeGen/ARM/fadds.ll @@ -1,6 +1,8 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CORTEXA8U +; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8U ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { @@ -18,6 +20,8 @@ entry: ; NFP0: vadd.f32 s ; CORTEXA8: test: -; CORTEXA8: vadd.f32 d +; CORTEXA8: vadd.f32 s +; CORTEXA8U: test: +; CORTEXA8U: vadd.f32 d ; CORTEXA9: test: -; CORTEXA9: vadd.f32 s{{.}}, s{{.}}, s{{.}} +; CORTEXA9: vadd.f32 s diff --git a/test/CodeGen/ARM/fmuls.ll b/test/CodeGen/ARM/fmuls.ll index 1566a9272d..f5245c9463 100644 --- a/test/CodeGen/ARM/fmuls.ll +++ b/test/CodeGen/ARM/fmuls.ll @@ -1,6 +1,8 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CORTEXA8U +; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8U ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { @@ -18,9 +20,11 @@ entry: ; NFP0: vmul.f32 s ; CORTEXA8: test: -; CORTEXA8: vmul.f32 d +; CORTEXA8: vmul.f32 s +; CORTEXA8U: test: +; CORTEXA8U: vmul.f32 d ; CORTEXA9: test: -; CORTEXA9: vmul.f32 s{{.}}, s{{.}}, s{{.}} +; CORTEXA9: vmul.f32 s ; VFP2: test2 define float @test2(float %a) nounwind { diff --git a/test/CodeGen/ARM/fnegs.ll b/test/CodeGen/ARM/fnegs.ll index 418b59803d..d84690ba4e 100644 --- a/test/CodeGen/ARM/fnegs.ll +++ b/test/CodeGen/ARM/fnegs.ll @@ -1,6 +1,8 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CORTEXA8U +; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8U ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test1(float* %a) { @@ -22,7 +24,10 @@ entry: ; NFP0: vneg.f32 s{{.*}}, s{{.*}} ; CORTEXA8: test1: -; CORTEXA8: vneg.f32 d{{.*}}, d{{.*}} +; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}} + +; CORTEXA8U: test1: +; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}} ; CORTEXA9: test1: ; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}} @@ -46,7 +51,10 @@ entry: ; NFP0: vneg.f32 s{{.*}}, s{{.*}} ; CORTEXA8: test2: -; CORTEXA8: vneg.f32 d{{.*}}, d{{.*}} +; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}} + +; CORTEXA8U: test2: +; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}} ; CORTEXA9: test2: ; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}} diff --git a/test/CodeGen/ARM/fnmscs.ll b/test/CodeGen/ARM/fnmscs.ll index 9ce9b7ae7d..c308061734 100644 --- a/test/CodeGen/ARM/fnmscs.ll +++ b/test/CodeGen/ARM/fnmscs.ll @@ -1,7 +1,9 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=A8 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=A8 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=A8U +; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8U define float @t1(float %acc, float %a, float %b) nounwind { entry: @@ -11,9 +13,13 @@ entry: ; NEON: t1: ; NEON: vnmla.f32 +; A8U: t1: +; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} +; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}} + ; A8: t1: ; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} -; A8: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}} +; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} %0 = fmul float %a, %b %1 = fsub float -0.0, %0 %2 = fsub float %1, %acc @@ -28,9 +34,13 @@ entry: ; NEON: t2: ; NEON: vnmla.f32 +; A8U: t2: +; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}} +; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}} + ; A8: t2: ; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}} -; A8: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}} +; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} %0 = fmul float %a, %b %1 = fmul float -1.0, %0 %2 = fsub float %1, %acc @@ -45,6 +55,10 @@ entry: ; NEON: t3: ; NEON: vnmla.f64 +; A8U: t3: +; A8U: vnmul.f64 d +; A8U: vsub.f64 d + ; A8: t3: ; A8: vnmul.f64 d ; A8: vsub.f64 d @@ -62,6 +76,10 @@ entry: ; NEON: t4: ; NEON: vnmla.f64 +; A8U: t4: +; A8U: vnmul.f64 d +; A8U: vsub.f64 d + ; A8: t4: ; A8: vnmul.f64 d ; A8: vsub.f64 d diff --git a/test/CodeGen/ARM/fp_convert.ll b/test/CodeGen/ARM/fp_convert.ll index 44298b9c5d..3c47eb580f 100644 --- a/test/CodeGen/ARM/fp_convert.ll +++ b/test/CodeGen/ARM/fp_convert.ll @@ -1,6 +1,8 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=NEON +; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2 define i32 @test1(float %a, float %b) { diff --git a/test/CodeGen/ARM/fsubs.ll b/test/CodeGen/ARM/fsubs.ll index f039e74c8e..617b01881a 100644 --- a/test/CodeGen/ARM/fsubs.ll +++ b/test/CodeGen/ARM/fsubs.ll @@ -1,5 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=NFP1U +; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=NFP1U ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 define float @test(float %a, float %b) { @@ -9,5 +11,6 @@ entry: } ; VFP2: vsub.f32 s -; NFP1: vsub.f32 d +; NFP1U: vsub.f32 d +; NFP1: vsub.f32 s ; NFP0: vsub.f32 s diff --git a/test/CodeGen/ARM/global-merge.ll b/test/CodeGen/ARM/global-merge.ll index 1732df3fa5..f88e927961 100644 --- a/test/CodeGen/ARM/global-merge.ll +++ b/test/CodeGen/ARM/global-merge.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumb-apple-darwin -global-merge-on-const=true | FileCheck %s ; Test the ARMGlobalMerge pass. Use -march=thumb because it has a small ; value for the maximum offset (127). @@ -6,6 +6,52 @@ ; CHECK: g0: @g0 = internal global [32 x i32] [ i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 1, i32 2 ] +; Global variables marked with "used" attribute must be kept +; CHECK: g8 +@g8 = internal global i32 0 +@llvm.used = appending global [1 x i8*] [i8* bitcast (i32* @g8 to i8*)], section "llvm.metadata" + +; Global used in landing pad instruction must be kept +; CHECK: ZTIi +@_ZTIi = internal global i8* null + +define i32 @_Z9exceptioni(i32 %arg) { +bb: + %tmp = invoke i32 @_Z14throwSomethingi(i32 %arg) + to label %bb9 unwind label %bb1 + +bb1: ; preds = %bb + %tmp2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* bitcast (i8** @_ZTIi to i8*) + %tmp3 = extractvalue { i8*, i32 } %tmp2, 1 + %tmp4 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) + %tmp5 = icmp eq i32 %tmp3, %tmp4 + br i1 %tmp5, label %bb6, label %bb10 + +bb6: ; preds = %bb1 + %tmp7 = extractvalue { i8*, i32 } %tmp2, 0 + %tmp8 = tail call i8* @__cxa_begin_catch(i8* %tmp7) + tail call void @__cxa_end_catch() + br label %bb9 + +bb9: ; preds = %bb6, %bb + %res.0 = phi i32 [ 0, %bb6 ], [ %tmp, %bb ] + ret i32 %res.0 + +bb10: ; preds = %bb1 + resume { i8*, i32 } %tmp2 +} + +declare i32 @_Z14throwSomethingi(i32) + +declare i32 @__gxx_personality_sj0(...) + +declare i32 @llvm.eh.typeid.for(i8*) + +declare i8* @__cxa_begin_catch(i8*) + +declare void @__cxa_end_catch() + ; CHECK: _MergedGlobals: @g1 = internal global i32 1 @g2 = internal global i32 2 @@ -21,3 +67,8 @@ ; CHECK: _MergedGlobals2 @g4 = internal global i32 0 @g5 = internal global i32 0 + +; Global variables that are constant can be merged together +; CHECK: _MergedGlobals3 +@g6 = internal constant [12 x i32] zeroinitializer, align 4 +@g7 = internal constant [12 x i32] zeroinitializer, align 4 diff --git a/test/CodeGen/ARM/lit.local.cfg b/test/CodeGen/ARM/lit.local.cfg index cb77b09ef4..4d75f581a1 100644 --- a/test/CodeGen/ARM/lit.local.cfg +++ b/test/CodeGen/ARM/lit.local.cfg @@ -1,4 +1,4 @@ -config.suffixes = ['.ll', '.c', '.cpp'] +config.suffixes = ['.ll', '.c', '.cpp', '.test'] targets = set(config.root.targets_to_build.split()) if not 'ARM' in targets: diff --git a/test/CodeGen/ARM/lsr-icmp-imm.ll b/test/CodeGen/ARM/lsr-icmp-imm.ll index 5283f5747d..248c4bd1be 100644 --- a/test/CodeGen/ARM/lsr-icmp-imm.ll +++ b/test/CodeGen/ARM/lsr-icmp-imm.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=thumbv7-apple-ios -disable-code-place < %s | FileCheck %s -; RUN: llc -mtriple=armv7-apple-ios -disable-code-place < %s | FileCheck %s +; RUN: llc -mtriple=thumbv7-apple-ios -disable-block-placement < %s | FileCheck %s +; RUN: llc -mtriple=armv7-apple-ios -disable-block-placement < %s | FileCheck %s ; LSR should compare against the post-incremented induction variable. ; In this case, the immediate value is -2 which requires a cmn instruction. diff --git a/test/CodeGen/ARM/neon-spfp.ll b/test/CodeGen/ARM/neon-spfp.ll new file mode 100644 index 0000000000..c00f0d17c9 --- /dev/null +++ b/test/CodeGen/ARM/neon-spfp.ll @@ -0,0 +1,76 @@ +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a5 | FileCheck %s -check-prefix=LINUXA5 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=LINUXA8 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a9 | FileCheck %s -check-prefix=LINUXA9 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a15 | FileCheck %s -check-prefix=LINUXA15 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=swift | FileCheck %s -check-prefix=LINUXSWIFT + +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a5 --enable-unsafe-fp-math | FileCheck %s -check-prefix=UNSAFEA5 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=UNSAFEA8 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a9 --enable-unsafe-fp-math | FileCheck %s -check-prefix=UNSAFEA9 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a15 --enable-unsafe-fp-math | FileCheck %s -check-prefix=UNSAFEA15 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=swift --enable-unsafe-fp-math | FileCheck %s -check-prefix=UNSAFESWIFT + +; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=cortex-a5 | FileCheck %s -check-prefix=DARWINA5 +; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=DARWINA8 +; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=cortex-a9 | FileCheck %s -check-prefix=DARWINA9 +; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=cortex-a15 | FileCheck %s -check-prefix=DARWINA15 +; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=swift | FileCheck %s -check-prefix=DARWINSWIFT + +; This test makes sure we're not lowering VMUL.f32 D* (aka. NEON) for single-prec. FP ops, since +; NEON is not fully IEEE 754 compliant, unless unsafe-math is selected. + +@.str = private unnamed_addr constant [12 x i8] c"S317\09%.5g \0A\00", align 1 + +; CHECK-LINUXA5: main: +; CHECK-LINUXA8: main: +; CHECK-LINUXA9: main: +; CHECK-LINUXA15: main: +; CHECK-LINUXSWIFT: main: +; CHECK-UNSAFEA5: main: +; CHECK-UNSAFEA8: main: +; CHECK-UNSAFEA9: main: +; CHECK-UNSAFEA15: main: +; CHECK-UNSAFESWIFT: main: +; CHECK-DARWINA5: main: +; CHECK-DARWINA8: main: +; CHECK-DARWINA9: main: +; CHECK-DARWINA15: main: +; CHECK-DARWINSWIFT: main: +define i32 @main() { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.04 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %q.03 = phi float [ 1.000000e+00, %entry ], [ %mul, %for.body ] + %mul = fmul float %q.03, 0x3FEFAE1480000000 +; CHECK-LINUXA5: vmul.f32 s{{[0-9]*}} +; CHECK-LINUXA8: vmul.f32 s{{[0-9]*}} +; CHECK-LINUXA9: vmul.f32 s{{[0-9]*}} +; CHECK-LINUXA15: vmul.f32 s{{[0-9]*}} +; Swift is *always* unsafe +; CHECK-LINUXSWIFT: vmul.f32 d{{[0-9]*}} + +; CHECK-UNSAFEA5: vmul.f32 d{{[0-9]*}} +; CHECK-UNSAFEA8: vmul.f32 d{{[0-9]*}} +; A9 and A15 don't need this +; CHECK-UNSAFEA9: vmul.f32 s{{[0-9]*}} +; CHECK-UNSAFEA15: vmul.f32 s{{[0-9]*}} +; CHECK-UNSAFESWIFT: vmul.f32 d{{[0-9]*}} + +; CHECK-DARWINA5: vmul.f32 d{{[0-9]*}} +; CHECK-DARWINA8: vmul.f32 d{{[0-9]*}} +; CHECK-DARWINA9: vmul.f32 s{{[0-9]*}} +; CHECK-DARWINA15: vmul.f32 s{{[0-9]*}} +; CHECK-DARWINSWIFT: vmul.f32 d{{[0-9]*}} + %conv = fpext float %mul to double + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), double %conv) #1 + %inc = add nsw i32 %i.04, 1 + %exitcond = icmp eq i32 %inc, 16000 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i32 0 +} + +declare i32 @printf(i8* nocapture, ...) diff --git a/test/CodeGen/ARM/neon_minmax.ll b/test/CodeGen/ARM/neon_minmax.ll index d301c6a4ca..0a7c8b2b6a 100644 --- a/test/CodeGen/ARM/neon_minmax.ll +++ b/test/CodeGen/ARM/neon_minmax.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s define float @fmin_ole(float %x) nounwind { ;CHECK: fmin_ole: diff --git a/test/CodeGen/ARM/vcvt.ll b/test/CodeGen/ARM/vcvt.ll index c078f49309..e67b4788a3 100644 --- a/test/CodeGen/ARM/vcvt.ll +++ b/test/CodeGen/ARM/vcvt.ll @@ -156,3 +156,175 @@ define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind { declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone + +; We currently estimate the cost of sext/zext/trunc v8(v16)i32 <-> v8(v16)i8 +; instructions as expensive. If lowering is improved the cost model needs to +; change. +; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST +%T0_5 = type <8 x i8> +%T1_5 = type <8 x i32> +; CHECK: func_cvt5: +define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) { +; CHECK: vmovl.s8 +; CHECK: vmovl.s16 +; CHECK: vmovl.s16 + %v0 = load %T0_5* %loadaddr +; COST: func_cvt5 +; COST: cost of 3 {{.*}} sext + %r = sext %T0_5 %v0 to %T1_5 + store %T1_5 %r, %T1_5* %storeaddr + ret void +} +;; We currently estimate the cost of this instruction as expensive. If lowering +;; is improved the cost needs to change. +%TA0_5 = type <8 x i8> +%TA1_5 = type <8 x i32> +; CHECK: func_cvt1: +define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) { +; CHECK: vmovl.u8 +; CHECK: vmovl.u16 +; CHECK: vmovl.u16 + %v0 = load %TA0_5* %loadaddr +; COST: func_cvt1 +; COST: cost of 3 {{.*}} zext + %r = zext %TA0_5 %v0 to %TA1_5 + store %TA1_5 %r, %TA1_5* %storeaddr + ret void +} +;; We currently estimate the cost of this instruction as expensive. If lowering +;; is improved the cost needs to change. +%T0_51 = type <8 x i32> +%T1_51 = type <8 x i8> +; CHECK: func_cvt51: +define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) { +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb + %v0 = load %T0_51* %loadaddr +; COST: func_cvt51 +; COST: cost of 19 {{.*}} trunc + %r = trunc %T0_51 %v0 to %T1_51 + store %T1_51 %r, %T1_51* %storeaddr + ret void +} +;; We currently estimate the cost of this instruction as expensive. If lowering +;; is improved the cost needs to change. +%TT0_5 = type <16 x i8> +%TT1_5 = type <16 x i32> +; CHECK: func_cvt52: +define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) { +; CHECK: vmovl.s16 +; CHECK: vmovl.s16 +; CHECK: vmovl.s16 +; CHECK: vmovl.s16 + %v0 = load %TT0_5* %loadaddr +; COST: func_cvt52 +; COST: cost of 6 {{.*}} sext + %r = sext %TT0_5 %v0 to %TT1_5 + store %TT1_5 %r, %TT1_5* %storeaddr + ret void +} +;; We currently estimate the cost of this instruction as expensive. If lowering +;; is improved the cost needs to change. +%TTA0_5 = type <16 x i8> +%TTA1_5 = type <16 x i32> +; CHECK: func_cvt12: +define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) { +; CHECK: vmovl.u16 +; CHECK: vmovl.u16 +; CHECK: vmovl.u16 +; CHECK: vmovl.u16 + %v0 = load %TTA0_5* %loadaddr +; COST: func_cvt12 +; COST: cost of 6 {{.*}} zext + %r = zext %TTA0_5 %v0 to %TTA1_5 + store %TTA1_5 %r, %TTA1_5* %storeaddr + ret void +} +;; We currently estimate the cost of this instruction as expensive. If lowering +;; is improved the cost needs to change. +%TT0_51 = type <16 x i32> +%TT1_51 = type <16 x i8> +; CHECK: func_cvt512: +define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) { +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb + %v0 = load %TT0_51* %loadaddr +; COST: func_cvt512 +; COST: cost of 38 {{.*}} trunc + %r = trunc %TT0_51 %v0 to %TT1_51 + store %TT1_51 %r, %TT1_51* %storeaddr + ret void +} + +; CHECK: sext_v4i16_v4i64: +define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { +; CHECK: vmovl.s32 +; CHECK: vmovl.s32 + %v0 = load <4 x i16>* %loadaddr +; COST: sext_v4i16_v4i64 +; COST: cost of 3 {{.*}} sext + %r = sext <4 x i16> %v0 to <4 x i64> + store <4 x i64> %r, <4 x i64>* %storeaddr + ret void +} + +; CHECK: zext_v4i16_v4i64: +define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { +; CHECK: vmovl.u32 +; CHECK: vmovl.u32 + %v0 = load <4 x i16>* %loadaddr +; COST: zext_v4i16_v4i64 +; COST: cost of 3 {{.*}} zext + %r = zext <4 x i16> %v0 to <4 x i64> + store <4 x i64> %r, <4 x i64>* %storeaddr + ret void +} + +; CHECK: sext_v8i16_v8i64: +define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) { +; CHECK: vmovl.s32 +; CHECK: vmovl.s32 +; CHECK: vmovl.s32 +; CHECK: vmovl.s32 + %v0 = load <8 x i16>* %loadaddr +; COST: sext_v8i16_v8i64 +; COST: cost of 6 {{.*}} sext + %r = sext <8 x i16> %v0 to <8 x i64> + store <8 x i64> %r, <8 x i64>* %storeaddr + ret void +} + +; CHECK: zext_v8i16_v8i64: +define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) { +; CHECK: vmovl.u32 +; CHECK: vmovl.u32 +; CHECK: vmovl.u32 +; CHECK: vmovl.u32 + %v0 = load <8 x i16>* %loadaddr +; COST: zext_v8i16_v8i64 +; COST: cost of 6 {{.*}} zext + %r = zext <8 x i16> %v0 to <8 x i64> + store <8 x i64> %r, <8 x i64>* %storeaddr + ret void +} + diff --git a/test/CodeGen/ARM/vselect_imax.ll b/test/CodeGen/ARM/vselect_imax.ll index f5994046de..7e79d6c68c 100644 --- a/test/CodeGen/ARM/vselect_imax.ll +++ b/test/CodeGen/ARM/vselect_imax.ll @@ -10,3 +10,114 @@ define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) { ret void } +; We adjusted the cost model of the following selects. When we improve code +; lowering we also need to adjust the cost. +%T0_10 = type <16 x i16> +%T1_10 = type <16 x i1> +; CHECK: func_blend10: +define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2, + %T1_10* %blend, %T0_10* %storeaddr) { + %v0 = load %T0_10* %loadaddr + %v1 = load %T0_10* %loadaddr2 + %c = icmp slt %T0_10 %v0, %v1 +; CHECK: vst1 +; CHECK: vst1 +; CHECK: vst1 +; CHECK: vst1 +; CHECK: vld +; COST: func_blend10 +; COST: cost of 40 {{.*}} select + %r = select %T1_10 %c, %T0_10 %v0, %T0_10 %v1 + store %T0_10 %r, %T0_10* %storeaddr + ret void +} +%T0_14 = type <8 x i32> +%T1_14 = type <8 x i1> +; CHECK: func_blend14: +define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2, + %T1_14* %blend, %T0_14* %storeaddr) { + %v0 = load %T0_14* %loadaddr + %v1 = load %T0_14* %loadaddr2 + %c = icmp slt %T0_14 %v0, %v1 +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; COST: func_blend14 +; COST: cost of 41 {{.*}} select + %r = select %T1_14 %c, %T0_14 %v0, %T0_14 %v1 + store %T0_14 %r, %T0_14* %storeaddr + ret void +} +%T0_15 = type <16 x i32> +%T1_15 = type <16 x i1> +; CHECK: func_blend15: +define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2, + %T1_15* %blend, %T0_15* %storeaddr) { + %v0 = load %T0_15* %loadaddr + %v1 = load %T0_15* %loadaddr2 + %c = icmp slt %T0_15 %v0, %v1 +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; COST: func_blend15 +; COST: cost of 82 {{.*}} select + %r = select %T1_15 %c, %T0_15 %v0, %T0_15 %v1 + store %T0_15 %r, %T0_15* %storeaddr + ret void +} +%T0_18 = type <4 x i64> +%T1_18 = type <4 x i1> +; CHECK: func_blend18: +define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2, + %T1_18* %blend, %T0_18* %storeaddr) { + %v0 = load %T0_18* %loadaddr + %v1 = load %T0_18* %loadaddr2 + %c = icmp slt %T0_18 %v0, %v1 +; CHECK: strh +; CHECK: strh +; CHECK: strh +; CHECK: strh +; COST: func_blend18 +; COST: cost of 19 {{.*}} select + %r = select %T1_18 %c, %T0_18 %v0, %T0_18 %v1 + store %T0_18 %r, %T0_18* %storeaddr + ret void +} +%T0_19 = type <8 x i64> +%T1_19 = type <8 x i1> +; CHECK: func_blend19: +define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2, + %T1_19* %blend, %T0_19* %storeaddr) { + %v0 = load %T0_19* %loadaddr + %v1 = load %T0_19* %loadaddr2 + %c = icmp slt %T0_19 %v0, %v1 +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; COST: func_blend19 +; COST: cost of 50 {{.*}} select + %r = select %T1_19 %c, %T0_19 %v0, %T0_19 %v1 + store %T0_19 %r, %T0_19* %storeaddr + ret void +} +%T0_20 = type <16 x i64> +%T1_20 = type <16 x i1> +; CHECK: func_blend20: +define void @func_blend20(%T0_20* %loadaddr, %T0_20* %loadaddr2, + %T1_20* %blend, %T0_20* %storeaddr) { + %v0 = load %T0_20* %loadaddr + %v1 = load %T0_20* %loadaddr2 + %c = icmp slt %T0_20 %v0, %v1 +; CHECK: strb +; CHECK: strb +; CHECK: strb +; CHECK: strb +; COST: func_blend20 +; COST: cost of 100 {{.*}} select + %r = select %T1_20 %c, %T0_20 %v0, %T0_20 %v1 + store %T0_20 %r, %T0_20* %storeaddr + ret void +} diff --git a/test/CodeGen/ARM/widen-vmovs.ll b/test/CodeGen/ARM/widen-vmovs.ll index 679e3f4347..1efbc73650 100644 --- a/test/CodeGen/ARM/widen-vmovs.ll +++ b/test/CodeGen/ARM/widen-vmovs.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -widen-vmovs -mcpu=cortex-a8 -verify-machineinstrs -disable-code-place | FileCheck %s +; RUN: llc < %s -widen-vmovs -mcpu=cortex-a8 -verify-machineinstrs -disable-block-placement | FileCheck %s target triple = "thumbv7-apple-ios" ; The 1.0e+10 constant is loaded from the constant pool and kept in a register. diff --git a/test/CodeGen/ARM/zextload_demandedbits.ll b/test/CodeGen/ARM/zextload_demandedbits.ll new file mode 100644 index 0000000000..3d3269cae2 --- /dev/null +++ b/test/CodeGen/ARM/zextload_demandedbits.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -march=arm -mtriple="thumbv7-apple-ios3.0.0" | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" + +%struct.eggs = type { %struct.spam, i16 } +%struct.spam = type { [3 x i32] } +%struct.barney = type { [2 x i32], [2 x i32] } + +; Make sure that the sext op does not get lost due to ComputeMaskedBits. +; CHECK: quux +; CHECK: lsl +; CHECK: asr +; CHECK: bl +; CHECK: pop +define void @quux(%struct.eggs* %arg) { +bb: + %tmp1 = getelementptr inbounds %struct.eggs* %arg, i32 0, i32 1 + %0 = load i16* %tmp1, align 2 + %tobool = icmp eq i16 %0, 0 + br i1 %tobool, label %bb16, label %bb3 + +bb3: ; preds = %bb + %tmp4 = bitcast i16* %tmp1 to i8* + %tmp5 = ptrtoint i16* %tmp1 to i32 + %tmp6 = shl i32 %tmp5, 20 + %tmp7 = ashr exact i32 %tmp6, 20 + %tmp14 = getelementptr inbounds %struct.barney* undef, i32 %tmp7 + %tmp15 = tail call i32 @widget(%struct.barney* %tmp14, i8* %tmp4, i32 %tmp7) + br label %bb16 + +bb16: ; preds = %bb3, %bb + ret void +} + +declare i32 @widget(%struct.barney*, i8*, i32) diff --git a/test/CodeGen/CPP/2007-06-16-Funcname.ll b/test/CodeGen/CPP/2007-06-16-Funcname.ll index 16e9798481..71fea12d9c 100644 --- a/test/CodeGen/CPP/2007-06-16-Funcname.ll +++ b/test/CodeGen/CPP/2007-06-16-Funcname.ll @@ -5,4 +5,3 @@ define void @foo() { ret void } - diff --git a/test/CodeGen/Generic/2008-02-20-MatchingMem.ll b/test/CodeGen/Generic/2008-02-20-MatchingMem.ll index da1aeb556a..7ffb734c71 100644 --- a/test/CodeGen/Generic/2008-02-20-MatchingMem.ll +++ b/test/CodeGen/Generic/2008-02-20-MatchingMem.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s ; PR1133 +; XFAIL: hexagon define void @test(i32* %X) nounwind { entry: %tmp1 = getelementptr i32* %X, i32 10 ; <i32*> [#uses=2] diff --git a/test/CodeGen/Generic/2013-03-20-APFloatCrash.ll b/test/CodeGen/Generic/2013-03-20-APFloatCrash.ll new file mode 100644 index 0000000000..a1aed0e3a4 --- /dev/null +++ b/test/CodeGen/Generic/2013-03-20-APFloatCrash.ll @@ -0,0 +1,7 @@ +; RUN: llc < %s + +define internal i1 @f(float %s) { +entry: + %c = fcmp ogt float %s, 0x41EFFFFFE0000000 + ret i1 %c +} diff --git a/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll b/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll index e709080bfc..a135c625fc 100644 --- a/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll +++ b/test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s - +; XFAIL: hexagon declare { i64, double } @wild() define void @foo(i64* %p, double* %q) nounwind { diff --git a/test/CodeGen/Generic/select-cc.ll b/test/CodeGen/Generic/select-cc.ll index b653e2a46d..7510f701b1 100644 --- a/test/CodeGen/Generic/select-cc.ll +++ b/test/CodeGen/Generic/select-cc.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s ; PR2504 - +; XFAIL: hexagon define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind { %x.lo = extractelement <2 x double> %x, i32 0 ; <double> [#uses=1] %x.lo.ge = fcmp oge double %x.lo, 0.000000e+00 ; <i1> [#uses=1] diff --git a/test/CodeGen/Generic/vector.ll b/test/CodeGen/Generic/vector.ll index 84814a1c12..bc7c7d00a1 100644 --- a/test/CodeGen/Generic/vector.ll +++ b/test/CodeGen/Generic/vector.ll @@ -1,6 +1,6 @@ ; Test that vectors are scalarized/lowered correctly. ; RUN: llc < %s - +; XFAIL: hexagon %d8 = type <8 x double> %f1 = type <1 x float> diff --git a/test/CodeGen/Hexagon/ashift-left-right.ll b/test/CodeGen/Hexagon/ashift-left-right.ll new file mode 100644 index 0000000000..7c41bc7bbf --- /dev/null +++ b/test/CodeGen/Hexagon/ashift-left-right.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s + +define i32 @foo(i32 %a, i32 %b) nounwind readnone { +; CHECK: lsl +; CHECK: aslh +entry: + %shl1 = shl i32 16, %a + %shl2 = shl i32 %b, 16 + %ret = mul i32 %shl1, %shl2 + ret i32 %ret +} + +define i32 @bar(i32 %a, i32 %b) nounwind readnone { +; CHECK: asrh +; CHECK: lsr +entry: + %shl1 = ashr i32 16, %a + %shl2 = ashr i32 %b, 16 + %ret = mul i32 %shl1, %shl2 + ret i32 %ret +} diff --git a/test/CodeGen/Hexagon/gp-rel.ll b/test/CodeGen/Hexagon/gp-rel.ll new file mode 100644 index 0000000000..561869e8ef --- /dev/null +++ b/test/CodeGen/Hexagon/gp-rel.ll @@ -0,0 +1,33 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; Check that gp-relative instructions are being generated. + +@a = common global i32 0, align 4 +@b = common global i32 0, align 4 +@c = common global i32 0, align 4 + +define i32 @foo(i32 %p) #0 { +entry: +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#a) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#b) +; CHECK: if{{ *}}(p{{[0-3]}}) memw(##c){{ *}}={{ *}}r{{[0-9]+}} + %0 = load i32* @a, align 4 + %1 = load i32* @b, align 4 + %add = add nsw i32 %1, %0 + %cmp = icmp eq i32 %0, %1 + br i1 %cmp, label %if.then, label %entry.if.end_crit_edge + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %add1 = add nsw i32 %add, %0 + store i32 %add1, i32* @c, align 4 + br label %if.end + +if.end: + %2 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %add1, %if.then ] + %cmp2 = icmp eq i32 %add, %2 + %sel1 = select i1 %cmp2, i32 %2, i32 %1 + ret i32 %sel1 +} diff --git a/test/CodeGen/Hexagon/hwloop-dbg.ll b/test/CodeGen/Hexagon/hwloop-dbg.ll index eaffa0797a..c2e8153b7d 100644 --- a/test/CodeGen/Hexagon/hwloop-dbg.ll +++ b/test/CodeGen/Hexagon/hwloop-dbg.ll @@ -33,7 +33,6 @@ for.end: ; preds = %for.body declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone -!llvm.dbg.cu = !{!0} !0 = metadata !{i32 786449, i32 0, i32 12, metadata !"hwloop-dbg.c", metadata !"/usr2/kparzysz/s.hex/t", metadata !"QuIC LLVM Hexagon Clang version 6.1-pre-unknown, (git://git-hexagon-aus.quicinc.com/llvm/clang-mainline.git e9382867661454cdf44addb39430741578e9765c) (llvm/llvm-mainline.git 36412bb1fcf03ed426d4437b41198bae066675ac)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c] [DW_LANG_C99] !1 = metadata !{metadata !2} diff --git a/test/CodeGen/Hexagon/memops.ll b/test/CodeGen/Hexagon/memops.ll new file mode 100644 index 0000000000..5498848d85 --- /dev/null +++ b/test/CodeGen/Hexagon/memops.ll @@ -0,0 +1,1369 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; Generate MemOps for V4 and above. + +define void @memop_unsigned_char_add5(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 + %0 = load i8* %p, align 1, !tbaa !0 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 5 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_add(i8* nocapture %p, i8 zeroext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} + %conv = zext i8 %x to i32 + %0 = load i8* %p, align 1, !tbaa !0 + %conv1 = zext i8 %0 to i32 + %add = add nsw i32 %conv1, %conv + %conv2 = trunc i32 %add to i8 + store i8 %conv2, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_sub(i8* nocapture %p, i8 zeroext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} + %conv = zext i8 %x to i32 + %0 = load i8* %p, align 1, !tbaa !0 + %conv1 = zext i8 %0 to i32 + %sub = sub nsw i32 %conv1, %conv + %conv2 = trunc i32 %sub to i8 + store i8 %conv2, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_or(i8* nocapture %p, i8 zeroext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} + %0 = load i8* %p, align 1, !tbaa !0 + %or3 = or i8 %0, %x + store i8 %or3, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_and(i8* nocapture %p, i8 zeroext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} + %0 = load i8* %p, align 1, !tbaa !0 + %and3 = and i8 %0, %x + store i8 %and3, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_clrbit(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %0 = load i8* %p, align 1, !tbaa !0 + %conv = zext i8 %0 to i32 + %and = and i32 %conv, 223 + %conv1 = trunc i32 %and to i8 + store i8 %conv1, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_setbit(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %0 = load i8* %p, align 1, !tbaa !0 + %conv = zext i8 %0 to i32 + %or = or i32 %conv, 128 + %conv1 = trunc i32 %or to i8 + store i8 %conv1, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_add5_index(i8* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 5 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_add_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} + %conv = zext i8 %x to i32 + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv1 = zext i8 %0 to i32 + %add = add nsw i32 %conv1, %conv + %conv2 = trunc i32 %add to i8 + store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_sub_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} + %conv = zext i8 %x to i32 + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv1 = zext i8 %0 to i32 + %sub = sub nsw i32 %conv1, %conv + %conv2 = trunc i32 %sub to i8 + store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_or_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %or3 = or i8 %0, %x + store i8 %or3, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_and_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %and3 = and i8 %0, %x + store i8 %and3, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv = zext i8 %0 to i32 + %and = and i32 %conv, 223 + %conv1 = trunc i32 %and to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv = zext i8 %0 to i32 + %or = or i32 %conv, 128 + %conv1 = trunc i32 %or to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_add5_index5(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %conv, 5 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_add_index5(i8* nocapture %p, i8 zeroext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} + %conv = zext i8 %x to i32 + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv1 = zext i8 %0 to i32 + %add = add nsw i32 %conv1, %conv + %conv2 = trunc i32 %add to i8 + store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_sub_index5(i8* nocapture %p, i8 zeroext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} + %conv = zext i8 %x to i32 + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv1 = zext i8 %0 to i32 + %sub = sub nsw i32 %conv1, %conv + %conv2 = trunc i32 %sub to i8 + store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_or_index5(i8* nocapture %p, i8 zeroext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %or3 = or i8 %0, %x + store i8 %or3, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_and_index5(i8* nocapture %p, i8 zeroext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %and3 = and i8 %0, %x + store i8 %and3, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_clrbit_index5(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv = zext i8 %0 to i32 + %and = and i32 %conv, 223 + %conv1 = trunc i32 %and to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_char_setbit_index5(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv = zext i8 %0 to i32 + %or = or i32 %conv, 128 + %conv1 = trunc i32 %or to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_add5(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 + %0 = load i8* %p, align 1, !tbaa !0 + %conv2 = zext i8 %0 to i32 + %add = add nsw i32 %conv2, 5 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_add(i8* nocapture %p, i8 signext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} + %conv4 = zext i8 %x to i32 + %0 = load i8* %p, align 1, !tbaa !0 + %conv13 = zext i8 %0 to i32 + %add = add nsw i32 %conv13, %conv4 + %conv2 = trunc i32 %add to i8 + store i8 %conv2, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_sub(i8* nocapture %p, i8 signext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} + %conv4 = zext i8 %x to i32 + %0 = load i8* %p, align 1, !tbaa !0 + %conv13 = zext i8 %0 to i32 + %sub = sub nsw i32 %conv13, %conv4 + %conv2 = trunc i32 %sub to i8 + store i8 %conv2, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_or(i8* nocapture %p, i8 signext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} + %0 = load i8* %p, align 1, !tbaa !0 + %or3 = or i8 %0, %x + store i8 %or3, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_and(i8* nocapture %p, i8 signext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} + %0 = load i8* %p, align 1, !tbaa !0 + %and3 = and i8 %0, %x + store i8 %and3, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_clrbit(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %0 = load i8* %p, align 1, !tbaa !0 + %conv2 = zext i8 %0 to i32 + %and = and i32 %conv2, 223 + %conv1 = trunc i32 %and to i8 + store i8 %conv1, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_setbit(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %0 = load i8* %p, align 1, !tbaa !0 + %conv2 = zext i8 %0 to i32 + %or = or i32 %conv2, 128 + %conv1 = trunc i32 %or to i8 + store i8 %conv1, i8* %p, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_add5_index(i8* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv2 = zext i8 %0 to i32 + %add = add nsw i32 %conv2, 5 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_add_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} + %conv4 = zext i8 %x to i32 + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv13 = zext i8 %0 to i32 + %add = add nsw i32 %conv13, %conv4 + %conv2 = trunc i32 %add to i8 + store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_sub_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} + %conv4 = zext i8 %x to i32 + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv13 = zext i8 %0 to i32 + %sub = sub nsw i32 %conv13, %conv4 + %conv2 = trunc i32 %sub to i8 + store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_or_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %or3 = or i8 %0, %x + store i8 %or3, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_and_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %and3 = and i8 %0, %x + store i8 %and3, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv2 = zext i8 %0 to i32 + %and = and i32 %conv2, 223 + %conv1 = trunc i32 %and to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %add.ptr = getelementptr inbounds i8* %p, i32 %i + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv2 = zext i8 %0 to i32 + %or = or i32 %conv2, 128 + %conv1 = trunc i32 %or to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_add5_index5(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv2 = zext i8 %0 to i32 + %add = add nsw i32 %conv2, 5 + %conv1 = trunc i32 %add to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_add_index5(i8* nocapture %p, i8 signext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} + %conv4 = zext i8 %x to i32 + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv13 = zext i8 %0 to i32 + %add = add nsw i32 %conv13, %conv4 + %conv2 = trunc i32 %add to i8 + store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_sub_index5(i8* nocapture %p, i8 signext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} + %conv4 = zext i8 %x to i32 + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv13 = zext i8 %0 to i32 + %sub = sub nsw i32 %conv13, %conv4 + %conv2 = trunc i32 %sub to i8 + store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_or_index5(i8* nocapture %p, i8 signext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %or3 = or i8 %0, %x + store i8 %or3, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_and_index5(i8* nocapture %p, i8 signext %x) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %and3 = and i8 %0, %x + store i8 %and3, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_clrbit_index5(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv2 = zext i8 %0 to i32 + %and = and i32 %conv2, 223 + %conv1 = trunc i32 %and to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_signed_char_setbit_index5(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %add.ptr = getelementptr inbounds i8* %p, i32 5 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv2 = zext i8 %0 to i32 + %or = or i32 %conv2, 128 + %conv1 = trunc i32 %or to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @memop_unsigned_short_add5(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 + %0 = load i16* %p, align 2, !tbaa !2 + %conv = zext i16 %0 to i32 + %add = add nsw i32 %conv, 5 + %conv1 = trunc i32 %add to i16 + store i16 %conv1, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_add(i16* nocapture %p, i16 zeroext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} + %conv = zext i16 %x to i32 + %0 = load i16* %p, align 2, !tbaa !2 + %conv1 = zext i16 %0 to i32 + %add = add nsw i32 %conv1, %conv + %conv2 = trunc i32 %add to i16 + store i16 %conv2, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_sub(i16* nocapture %p, i16 zeroext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} + %conv = zext i16 %x to i32 + %0 = load i16* %p, align 2, !tbaa !2 + %conv1 = zext i16 %0 to i32 + %sub = sub nsw i32 %conv1, %conv + %conv2 = trunc i32 %sub to i16 + store i16 %conv2, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_or(i16* nocapture %p, i16 zeroext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} + %0 = load i16* %p, align 2, !tbaa !2 + %or3 = or i16 %0, %x + store i16 %or3, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_and(i16* nocapture %p, i16 zeroext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} + %0 = load i16* %p, align 2, !tbaa !2 + %and3 = and i16 %0, %x + store i16 %and3, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_clrbit(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %0 = load i16* %p, align 2, !tbaa !2 + %conv = zext i16 %0 to i32 + %and = and i32 %conv, 65503 + %conv1 = trunc i32 %and to i16 + store i16 %conv1, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_setbit(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %0 = load i16* %p, align 2, !tbaa !2 + %conv = zext i16 %0 to i32 + %or = or i32 %conv, 128 + %conv1 = trunc i32 %or to i16 + store i16 %conv1, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_add5_index(i16* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv = zext i16 %0 to i32 + %add = add nsw i32 %conv, 5 + %conv1 = trunc i32 %add to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_add_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} + %conv = zext i16 %x to i32 + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv1 = zext i16 %0 to i32 + %add = add nsw i32 %conv1, %conv + %conv2 = trunc i32 %add to i16 + store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_sub_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} + %conv = zext i16 %x to i32 + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv1 = zext i16 %0 to i32 + %sub = sub nsw i32 %conv1, %conv + %conv2 = trunc i32 %sub to i16 + store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_or_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %or3 = or i16 %0, %x + store i16 %or3, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_and_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %and3 = and i16 %0, %x + store i16 %and3, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv = zext i16 %0 to i32 + %and = and i32 %conv, 65503 + %conv1 = trunc i32 %and to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv = zext i16 %0 to i32 + %or = or i32 %conv, 128 + %conv1 = trunc i32 %or to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_add5_index5(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv = zext i16 %0 to i32 + %add = add nsw i32 %conv, 5 + %conv1 = trunc i32 %add to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_add_index5(i16* nocapture %p, i16 zeroext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} + %conv = zext i16 %x to i32 + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv1 = zext i16 %0 to i32 + %add = add nsw i32 %conv1, %conv + %conv2 = trunc i32 %add to i16 + store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_sub_index5(i16* nocapture %p, i16 zeroext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} + %conv = zext i16 %x to i32 + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv1 = zext i16 %0 to i32 + %sub = sub nsw i32 %conv1, %conv + %conv2 = trunc i32 %sub to i16 + store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_or_index5(i16* nocapture %p, i16 zeroext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %or3 = or i16 %0, %x + store i16 %or3, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_and_index5(i16* nocapture %p, i16 zeroext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %and3 = and i16 %0, %x + store i16 %and3, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_clrbit_index5(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv = zext i16 %0 to i32 + %and = and i32 %conv, 65503 + %conv1 = trunc i32 %and to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_unsigned_short_setbit_index5(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv = zext i16 %0 to i32 + %or = or i32 %conv, 128 + %conv1 = trunc i32 %or to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_add5(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 + %0 = load i16* %p, align 2, !tbaa !2 + %conv2 = zext i16 %0 to i32 + %add = add nsw i32 %conv2, 5 + %conv1 = trunc i32 %add to i16 + store i16 %conv1, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_add(i16* nocapture %p, i16 signext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} + %conv4 = zext i16 %x to i32 + %0 = load i16* %p, align 2, !tbaa !2 + %conv13 = zext i16 %0 to i32 + %add = add nsw i32 %conv13, %conv4 + %conv2 = trunc i32 %add to i16 + store i16 %conv2, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_sub(i16* nocapture %p, i16 signext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} + %conv4 = zext i16 %x to i32 + %0 = load i16* %p, align 2, !tbaa !2 + %conv13 = zext i16 %0 to i32 + %sub = sub nsw i32 %conv13, %conv4 + %conv2 = trunc i32 %sub to i16 + store i16 %conv2, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_or(i16* nocapture %p, i16 signext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} + %0 = load i16* %p, align 2, !tbaa !2 + %or3 = or i16 %0, %x + store i16 %or3, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_and(i16* nocapture %p, i16 signext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} + %0 = load i16* %p, align 2, !tbaa !2 + %and3 = and i16 %0, %x + store i16 %and3, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_clrbit(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %0 = load i16* %p, align 2, !tbaa !2 + %conv2 = zext i16 %0 to i32 + %and = and i32 %conv2, 65503 + %conv1 = trunc i32 %and to i16 + store i16 %conv1, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_setbit(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %0 = load i16* %p, align 2, !tbaa !2 + %conv2 = zext i16 %0 to i32 + %or = or i32 %conv2, 128 + %conv1 = trunc i32 %or to i16 + store i16 %conv1, i16* %p, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_add5_index(i16* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv2 = zext i16 %0 to i32 + %add = add nsw i32 %conv2, 5 + %conv1 = trunc i32 %add to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_add_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} + %conv4 = zext i16 %x to i32 + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv13 = zext i16 %0 to i32 + %add = add nsw i32 %conv13, %conv4 + %conv2 = trunc i32 %add to i16 + store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_sub_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} + %conv4 = zext i16 %x to i32 + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv13 = zext i16 %0 to i32 + %sub = sub nsw i32 %conv13, %conv4 + %conv2 = trunc i32 %sub to i16 + store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_or_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %or3 = or i16 %0, %x + store i16 %or3, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_and_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %and3 = and i16 %0, %x + store i16 %and3, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv2 = zext i16 %0 to i32 + %and = and i32 %conv2, 65503 + %conv1 = trunc i32 %and to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %add.ptr = getelementptr inbounds i16* %p, i32 %i + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv2 = zext i16 %0 to i32 + %or = or i32 %conv2, 128 + %conv1 = trunc i32 %or to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_add5_index5(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv2 = zext i16 %0 to i32 + %add = add nsw i32 %conv2, 5 + %conv1 = trunc i32 %add to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_add_index5(i16* nocapture %p, i16 signext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} + %conv4 = zext i16 %x to i32 + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv13 = zext i16 %0 to i32 + %add = add nsw i32 %conv13, %conv4 + %conv2 = trunc i32 %add to i16 + store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_sub_index5(i16* nocapture %p, i16 signext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} + %conv4 = zext i16 %x to i32 + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv13 = zext i16 %0 to i32 + %sub = sub nsw i32 %conv13, %conv4 + %conv2 = trunc i32 %sub to i16 + store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_or_index5(i16* nocapture %p, i16 signext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %or3 = or i16 %0, %x + store i16 %or3, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_and_index5(i16* nocapture %p, i16 signext %x) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %and3 = and i16 %0, %x + store i16 %and3, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_clrbit_index5(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv2 = zext i16 %0 to i32 + %and = and i32 %conv2, 65503 + %conv1 = trunc i32 %and to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_short_setbit_index5(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %add.ptr = getelementptr inbounds i16* %p, i32 5 + %0 = load i16* %add.ptr, align 2, !tbaa !2 + %conv2 = zext i16 %0 to i32 + %or = or i32 %conv2, 128 + %conv1 = trunc i32 %or to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 + ret void +} + +define void @memop_signed_int_add5(i32* nocapture %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 + %0 = load i32* %p, align 4, !tbaa !3 + %add = add i32 %0, 5 + store i32 %add, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_add(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} + %0 = load i32* %p, align 4, !tbaa !3 + %add = add i32 %0, %x + store i32 %add, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_sub(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} + %0 = load i32* %p, align 4, !tbaa !3 + %sub = sub i32 %0, %x + store i32 %sub, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_or(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} + %0 = load i32* %p, align 4, !tbaa !3 + %or = or i32 %0, %x + store i32 %or, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_and(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} + %0 = load i32* %p, align 4, !tbaa !3 + %and = and i32 %0, %x + store i32 %and, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_clrbit(i32* nocapture %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %0 = load i32* %p, align 4, !tbaa !3 + %and = and i32 %0, -33 + store i32 %and, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_setbit(i32* nocapture %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %0 = load i32* %p, align 4, !tbaa !3 + %or = or i32 %0, 128 + store i32 %or, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_add5_index(i32* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %add = add i32 %0, 5 + store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %add = add i32 %0, %x + store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %sub = sub i32 %0, %x + store i32 %sub, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %or = or i32 %0, %x + store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %and = and i32 %0, %x + store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %and = and i32 %0, -33 + store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %or = or i32 %0, 128 + store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_add5_index5(i32* nocapture %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %add = add i32 %0, 5 + store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_add_index5(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %add = add i32 %0, %x + store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %sub = sub i32 %0, %x + store i32 %sub, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_or_index5(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %or = or i32 %0, %x + store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_and_index5(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %and = and i32 %0, %x + store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_clrbit_index5(i32* nocapture %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %and = and i32 %0, -33 + store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_signed_int_setbit_index5(i32* nocapture %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %or = or i32 %0, 128 + store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_add5(i32* nocapture %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 + %0 = load i32* %p, align 4, !tbaa !3 + %add = add nsw i32 %0, 5 + store i32 %add, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_add(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} + %0 = load i32* %p, align 4, !tbaa !3 + %add = add nsw i32 %0, %x + store i32 %add, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_sub(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} + %0 = load i32* %p, align 4, !tbaa !3 + %sub = sub nsw i32 %0, %x + store i32 %sub, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_or(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} + %0 = load i32* %p, align 4, !tbaa !3 + %or = or i32 %0, %x + store i32 %or, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_and(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} + %0 = load i32* %p, align 4, !tbaa !3 + %and = and i32 %0, %x + store i32 %and, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_clrbit(i32* nocapture %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %0 = load i32* %p, align 4, !tbaa !3 + %and = and i32 %0, -33 + store i32 %and, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_setbit(i32* nocapture %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %0 = load i32* %p, align 4, !tbaa !3 + %or = or i32 %0, 128 + store i32 %or, i32* %p, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_add5_index(i32* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %add = add nsw i32 %0, 5 + store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %add = add nsw i32 %0, %x + store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %sub = sub nsw i32 %0, %x + store i32 %sub, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %or = or i32 %0, %x + store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %and = and i32 %0, %x + store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %and = and i32 %0, -33 + store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %add.ptr = getelementptr inbounds i32* %p, i32 %i + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %or = or i32 %0, 128 + store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_add5_index5(i32* nocapture %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %add = add nsw i32 %0, 5 + store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_add_index5(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %add = add nsw i32 %0, %x + store i32 %add, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %sub = sub nsw i32 %0, %x + store i32 %sub, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_or_index5(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %or = or i32 %0, %x + store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_and_index5(i32* nocapture %p, i32 %x) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %and = and i32 %0, %x + store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_clrbit_index5(i32* nocapture %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %and = and i32 %0, -33 + store i32 %and, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +define void @memop_unsigned_int_setbit_index5(i32* nocapture %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) + %add.ptr = getelementptr inbounds i32* %p, i32 5 + %0 = load i32* %add.ptr, align 4, !tbaa !3 + %or = or i32 %0, 128 + store i32 %or, i32* %add.ptr, align 4, !tbaa !3 + ret void +} + +!0 = metadata !{metadata !"omnipotent char", metadata !1} +!1 = metadata !{metadata !"Simple C/C++ TBAA"} +!2 = metadata !{metadata !"short", metadata !0} +!3 = metadata !{metadata !"int", metadata !0} diff --git a/test/CodeGen/Hexagon/memops1.ll b/test/CodeGen/Hexagon/memops1.ll new file mode 100644 index 0000000000..2babdc848d --- /dev/null +++ b/test/CodeGen/Hexagon/memops1.ll @@ -0,0 +1,33 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; Generate MemOps for V4 and above. + + +define void @f(i32* %p) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#40){{ *}}-={{ *}}#1 + %p.addr = alloca i32*, align 4 + store i32* %p, i32** %p.addr, align 4 + %0 = load i32** %p.addr, align 4 + %add.ptr = getelementptr inbounds i32* %0, i32 10 + %1 = load i32* %add.ptr, align 4 + %sub = sub nsw i32 %1, 1 + store i32 %sub, i32* %add.ptr, align 4 + ret void +} + +define void @g(i32* %p, i32 %i) nounwind { +entry: +; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#40){{ *}}-={{ *}}#1 + %p.addr = alloca i32*, align 4 + %i.addr = alloca i32, align 4 + store i32* %p, i32** %p.addr, align 4 + store i32 %i, i32* %i.addr, align 4 + %0 = load i32** %p.addr, align 4 + %1 = load i32* %i.addr, align 4 + %add.ptr = getelementptr inbounds i32* %0, i32 %1 + %add.ptr1 = getelementptr inbounds i32* %add.ptr, i32 10 + %2 = load i32* %add.ptr1, align 4 + %sub = sub nsw i32 %2, 1 + store i32 %sub, i32* %add.ptr1, align 4 + ret void +} diff --git a/test/CodeGen/Hexagon/memops2.ll b/test/CodeGen/Hexagon/memops2.ll new file mode 100644 index 0000000000..b1b25445c0 --- /dev/null +++ b/test/CodeGen/Hexagon/memops2.ll @@ -0,0 +1,32 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; Generate MemOps for V4 and above. + + +define void @f(i16* nocapture %p) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}#1 + %add.ptr = getelementptr inbounds i16* %p, i32 10 + %0 = load i16* %add.ptr, align 2, !tbaa !0 + %conv2 = zext i16 %0 to i32 + %sub = add nsw i32 %conv2, 65535 + %conv1 = trunc i32 %sub to i16 + store i16 %conv1, i16* %add.ptr, align 2, !tbaa !0 + ret void +} + +define void @g(i16* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}#1 + %add.ptr.sum = add i32 %i, 10 + %add.ptr1 = getelementptr inbounds i16* %p, i32 %add.ptr.sum + %0 = load i16* %add.ptr1, align 2, !tbaa !0 + %conv3 = zext i16 %0 to i32 + %sub = add nsw i32 %conv3, 65535 + %conv2 = trunc i32 %sub to i16 + store i16 %conv2, i16* %add.ptr1, align 2, !tbaa !0 + ret void +} + +!0 = metadata !{metadata !"short", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/memops3.ll b/test/CodeGen/Hexagon/memops3.ll new file mode 100644 index 0000000000..5b8bd6c87b --- /dev/null +++ b/test/CodeGen/Hexagon/memops3.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; Generate MemOps for V4 and above. + + +define void @f(i8* nocapture %p) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}#1 + %add.ptr = getelementptr inbounds i8* %p, i32 10 + %0 = load i8* %add.ptr, align 1, !tbaa !0 + %conv = zext i8 %0 to i32 + %sub = add nsw i32 %conv, 255 + %conv1 = trunc i32 %sub to i8 + store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + ret void +} + +define void @g(i8* nocapture %p, i32 %i) nounwind { +entry: +; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}#1 + %add.ptr.sum = add i32 %i, 10 + %add.ptr1 = getelementptr inbounds i8* %p, i32 %add.ptr.sum + %0 = load i8* %add.ptr1, align 1, !tbaa !0 + %conv = zext i8 %0 to i32 + %sub = add nsw i32 %conv, 255 + %conv2 = trunc i32 %sub to i8 + store i8 %conv2, i8* %add.ptr1, align 1, !tbaa !0 + ret void +} + +!0 = metadata !{metadata !"omnipotent char", metadata !1} +!1 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/misaligned-access.ll b/test/CodeGen/Hexagon/misaligned-access.ll new file mode 100644 index 0000000000..4dafb44cc3 --- /dev/null +++ b/test/CodeGen/Hexagon/misaligned-access.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s +; Check that the mis-aligned load doesn't cause compiler to assert. + +declare i32 @_hi(i64) #1 +@temp1 = common global i32 0, align 4 + +define i32 @CSDRSEARCH_executeSearchManager() #0 { +entry: + %temp = alloca i32, align 4 + %0 = load i32* @temp1, align 4 + store i32 %0, i32* %temp, align 4 + %1 = bitcast i32* %temp to i64* + %2 = load i64* %1, align 8 + %call = call i32 @_hi(i64 %2) + ret i32 %call +} diff --git a/test/CodeGen/Inputs/DbgValueOtherTargets.ll b/test/CodeGen/Inputs/DbgValueOtherTargets.ll index 3f244f6891..d5162b964a 100644 --- a/test/CodeGen/Inputs/DbgValueOtherTargets.ll +++ b/test/CodeGen/Inputs/DbgValueOtherTargets.ll @@ -12,11 +12,10 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!2} -!11 = metadata !{metadata !0} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !11, null, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !12} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 120996)", i1 false, metadata !"", i32 0, null, null, metadata !11, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] @@ -25,3 +24,5 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !8 = metadata !{i32 786443, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] !9 = metadata !{i32 3, i32 11, metadata !8, null} !10 = metadata !{i32 4, i32 2, metadata !8, null} +!11 = metadata !{metadata !0} +!12 = metadata !{metadata !"/tmp/x.c", metadata !"/Users/manav"} diff --git a/test/CodeGen/MBlaze/DbgValueOtherTargets.test b/test/CodeGen/MBlaze/DbgValueOtherTargets.test index 4032d7b81c..8b850f5110 100644 --- a/test/CodeGen/MBlaze/DbgValueOtherTargets.test +++ b/test/CodeGen/MBlaze/DbgValueOtherTargets.test @@ -1 +1 @@ -; RUN: llc -O0 -march=mblaze -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -march=mblaze -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/MBlaze/lit.local.cfg b/test/CodeGen/MBlaze/lit.local.cfg index e236200d75..ff4928de4b 100644 --- a/test/CodeGen/MBlaze/lit.local.cfg +++ b/test/CodeGen/MBlaze/lit.local.cfg @@ -1,4 +1,4 @@ -config.suffixes = ['.ll', '.c', '.cpp'] +config.suffixes = ['.ll', '.c', '.cpp', '.test'] targets = set(config.root.targets_to_build.split()) if not 'MBlaze' in targets: diff --git a/test/CodeGen/MSP430/DbgValueOtherTargets.test b/test/CodeGen/MSP430/DbgValueOtherTargets.test index f8c747ec92..7adfbcafa3 100644 --- a/test/CodeGen/MSP430/DbgValueOtherTargets.test +++ b/test/CodeGen/MSP430/DbgValueOtherTargets.test @@ -1 +1 @@ -; RUN: llc -O0 -march=msp430 -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -march=msp430 -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/MSP430/lit.local.cfg b/test/CodeGen/MSP430/lit.local.cfg index 972732ebad..0ca9fc9c69 100644 --- a/test/CodeGen/MSP430/lit.local.cfg +++ b/test/CodeGen/MSP430/lit.local.cfg @@ -1,4 +1,4 @@ -config.suffixes = ['.ll', '.c', '.cpp'] +config.suffixes = ['.ll', '.c', '.cpp', '.test'] targets = set(config.root.targets_to_build.split()) if not 'MSP430' in targets: diff --git a/test/CodeGen/Mips/DbgValueOtherTargets.test b/test/CodeGen/Mips/DbgValueOtherTargets.test index 9c351ace68..da20e7ef52 100644 --- a/test/CodeGen/Mips/DbgValueOtherTargets.test +++ b/test/CodeGen/Mips/DbgValueOtherTargets.test @@ -1 +1 @@ -; RUN: llc -O0 -march=mips -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -march=mips -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/Mips/dsp-patterns.ll b/test/CodeGen/Mips/dsp-patterns.ll new file mode 100644 index 0000000000..0752f69c3e --- /dev/null +++ b/test/CodeGen/Mips/dsp-patterns.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s + +; CHECK: test_lbux: +; CHECK: lbux ${{[0-9]+}} + +define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) { +entry: + %add.ptr = getelementptr inbounds i8* %b, i32 %i + %0 = load i8* %add.ptr, align 1 + ret i8 %0 +} + +; CHECK: test_lhx: +; CHECK: lhx ${{[0-9]+}} + +define signext i16 @test_lhx(i16* nocapture %b, i32 %i) { +entry: + %add.ptr = getelementptr inbounds i16* %b, i32 %i + %0 = load i16* %add.ptr, align 2 + ret i16 %0 +} + +; CHECK: test_lwx: +; CHECK: lwx ${{[0-9]+}} + +define i32 @test_lwx(i32* nocapture %b, i32 %i) { +entry: + %add.ptr = getelementptr inbounds i32* %b, i32 %i + %0 = load i32* %add.ptr, align 4 + ret i32 %0 +} diff --git a/test/CodeGen/Mips/lit.local.cfg b/test/CodeGen/Mips/lit.local.cfg index 0587d3243e..e157c540b5 100644 --- a/test/CodeGen/Mips/lit.local.cfg +++ b/test/CodeGen/Mips/lit.local.cfg @@ -1,4 +1,4 @@ -config.suffixes = ['.ll', '.c', '.cpp'] +config.suffixes = ['.ll', '.c', '.cpp', '.test'] targets = set(config.root.targets_to_build.split()) if not 'Mips' in targets: diff --git a/test/CodeGen/Mips/madd-msub.ll b/test/CodeGen/Mips/madd-msub.ll index 0aeabb30e2..0dbb2c27b8 100644 --- a/test/CodeGen/Mips/madd-msub.ll +++ b/test/CodeGen/Mips/madd-msub.ll @@ -1,6 +1,9 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=32 +; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=DSP +; RUN: llc -march=mips -mcpu=mips16 < %s -; CHECK: madd +; 32: madd ${{[0-9]+}} +; DSP: madd $ac define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = sext i32 %a to i64 @@ -11,7 +14,8 @@ entry: ret i64 %add } -; CHECK: maddu +; 32: maddu ${{[0-9]+}} +; DSP: maddu $ac define i64 @madd2(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = zext i32 %a to i64 @@ -22,7 +26,8 @@ entry: ret i64 %add } -; CHECK: madd +; 32: madd ${{[0-9]+}} +; DSP: madd $ac define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone { entry: %conv = sext i32 %a to i64 @@ -32,7 +37,8 @@ entry: ret i64 %add } -; CHECK: msub +; 32: msub ${{[0-9]+}} +; DSP: msub $ac define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = sext i32 %c to i64 @@ -43,7 +49,8 @@ entry: ret i64 %sub } -; CHECK: msubu +; 32: msubu ${{[0-9]+}} +; DSP: msubu $ac define i64 @msub2(i32 %a, i32 %b, i32 %c) nounwind readnone { entry: %conv = zext i32 %c to i64 @@ -54,7 +61,8 @@ entry: ret i64 %sub } -; CHECK: msub +; 32: msub ${{[0-9]+}} +; DSP: msub $ac define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone { entry: %conv = sext i32 %a to i64 diff --git a/test/CodeGen/NVPTX/annotations.ll b/test/CodeGen/NVPTX/annotations.ll index d93f688ef1..39d52d3826 100644 --- a/test/CodeGen/NVPTX/annotations.ll +++ b/test/CodeGen/NVPTX/annotations.ll @@ -1,5 +1,3 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s diff --git a/test/CodeGen/NVPTX/arithmetic-fp-sm10.ll b/test/CodeGen/NVPTX/arithmetic-fp-sm10.ll deleted file mode 100644 index 73c77f56bc..0000000000 --- a/test/CodeGen/NVPTX/arithmetic-fp-sm10.ll +++ /dev/null @@ -1,72 +0,0 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s - -;; These tests should run for all targets - -;;===-- Basic instruction selection tests ---------------------------------===;; - - -;;; f64 - -define double @fadd_f64(double %a, double %b) { -; CHECK: add.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}} -; CHECK: ret - %ret = fadd double %a, %b - ret double %ret -} - -define double @fsub_f64(double %a, double %b) { -; CHECK: sub.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}} -; CHECK: ret - %ret = fsub double %a, %b - ret double %ret -} - -define double @fmul_f64(double %a, double %b) { -; CHECK: mul.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}} -; CHECK: ret - %ret = fmul double %a, %b - ret double %ret -} - -define double @fdiv_f64(double %a, double %b) { -; CHECK: div.rn.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, %fl{{[0-9]+}} -; CHECK: ret - %ret = fdiv double %a, %b - ret double %ret -} - -;; PTX does not have a floating-point rem instruction - - -;;; f32 - -define float @fadd_f32(float %a, float %b) { -; CHECK: add.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}} -; CHECK: ret - %ret = fadd float %a, %b - ret float %ret -} - -define float @fsub_f32(float %a, float %b) { -; CHECK: sub.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}} -; CHECK: ret - %ret = fsub float %a, %b - ret float %ret -} - -define float @fmul_f32(float %a, float %b) { -; CHECK: mul.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}} -; CHECK: ret - %ret = fmul float %a, %b - ret float %ret -} - -define float @fdiv_f32(float %a, float %b) { -; CHECK: div.full.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}} -; CHECK: ret - %ret = fdiv float %a, %b - ret float %ret -} - -;; PTX does not have a floating-point rem instruction diff --git a/test/CodeGen/NVPTX/arithmetic-int.ll b/test/CodeGen/NVPTX/arithmetic-int.ll index 529f84900a..8d73b7e6c4 100644 --- a/test/CodeGen/NVPTX/arithmetic-int.ll +++ b/test/CodeGen/NVPTX/arithmetic-int.ll @@ -1,5 +1,3 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s diff --git a/test/CodeGen/NVPTX/calling-conv.ll b/test/CodeGen/NVPTX/calling-conv.ll index 968203e5f7..190a1462ad 100644 --- a/test/CodeGen/NVPTX/calling-conv.ll +++ b/test/CodeGen/NVPTX/calling-conv.ll @@ -1,5 +1,3 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s diff --git a/test/CodeGen/NVPTX/compare-int.ll b/test/CodeGen/NVPTX/compare-int.ll index 12fc754821..16af0a336d 100644 --- a/test/CodeGen/NVPTX/compare-int.ll +++ b/test/CodeGen/NVPTX/compare-int.ll @@ -1,5 +1,3 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s diff --git a/test/CodeGen/NVPTX/convert-fp.ll b/test/CodeGen/NVPTX/convert-fp.ll index 21c84379b0..1882121fa7 100644 --- a/test/CodeGen/NVPTX/convert-fp.ll +++ b/test/CodeGen/NVPTX/convert-fp.ll @@ -1,5 +1,3 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s diff --git a/test/CodeGen/NVPTX/convert-int-sm10.ll b/test/CodeGen/NVPTX/convert-int-sm10.ll deleted file mode 100644 index 20716f982e..0000000000 --- a/test/CodeGen/NVPTX/convert-int-sm10.ll +++ /dev/null @@ -1,55 +0,0 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s - - -; i16 - -define i16 @cvt_i16_i32(i32 %x) { -; CHECK: cvt.u16.u32 %rs{{[0-9]+}}, %r{{[0-9]+}} -; CHECK: ret - %a = trunc i32 %x to i16 - ret i16 %a -} - -define i16 @cvt_i16_i64(i64 %x) { -; CHECK: cvt.u16.u64 %rs{{[0-9]+}}, %rl{{[0-9]+}} -; CHECK: ret - %a = trunc i64 %x to i16 - ret i16 %a -} - - - -; i32 - -define i32 @cvt_i32_i16(i16 %x) { -; CHECK: cvt.u32.u16 %r{{[0-9]+}}, %rs{{[0-9]+}} -; CHECK: ret - %a = zext i16 %x to i32 - ret i32 %a -} - -define i32 @cvt_i32_i64(i64 %x) { -; CHECK: cvt.u32.u64 %r{{[0-9]+}}, %rl{{[0-9]+}} -; CHECK: ret - %a = trunc i64 %x to i32 - ret i32 %a -} - - - -; i64 - -define i64 @cvt_i64_i16(i16 %x) { -; CHECK: cvt.u64.u16 %rl{{[0-9]+}}, %rs{{[0-9]+}} -; CHECK: ret - %a = zext i16 %x to i64 - ret i64 %a -} - -define i64 @cvt_i64_i32(i32 %x) { -; CHECK: cvt.u64.u32 %rl{{[0-9]+}}, %r{{[0-9]+}} -; CHECK: ret - %a = zext i32 %x to i64 - ret i64 %a -} diff --git a/test/CodeGen/NVPTX/intrinsic-old.ll b/test/CodeGen/NVPTX/intrinsic-old.ll index 1c9879c417..53a28f3337 100644 --- a/test/CodeGen/NVPTX/intrinsic-old.ll +++ b/test/CodeGen/NVPTX/intrinsic-old.ll @@ -1,5 +1,3 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s diff --git a/test/CodeGen/NVPTX/intrinsics.ll b/test/CodeGen/NVPTX/intrinsics.ll index afab60ca96..8b0357be87 100644 --- a/test/CodeGen/NVPTX/intrinsics.ll +++ b/test/CodeGen/NVPTX/intrinsics.ll @@ -1,5 +1,3 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s diff --git a/test/CodeGen/NVPTX/ld-addrspace.ll b/test/CodeGen/NVPTX/ld-addrspace.ll index d1f5093df2..3265868d3c 100644 --- a/test/CodeGen/NVPTX/ld-addrspace.ll +++ b/test/CodeGen/NVPTX/ld-addrspace.ll @@ -1,6 +1,4 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s --check-prefix=PTX32 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32 -; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s --check-prefix=PTX64 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64 diff --git a/test/CodeGen/NVPTX/nvvm-reflect.ll b/test/CodeGen/NVPTX/nvvm-reflect.ll new file mode 100644 index 0000000000..0d02194651 --- /dev/null +++ b/test/CodeGen/NVPTX/nvvm-reflect.ll @@ -0,0 +1,34 @@ +; RUN: opt < %s -S -nvvm-reflect -nvvm-reflect-list USE_MUL=0 -O2 | FileCheck %s --check-prefix=USE_MUL_0 +; RUN: opt < %s -S -nvvm-reflect -nvvm-reflect-list USE_MUL=1 -O2 | FileCheck %s --check-prefix=USE_MUL_1 + +@str = private addrspace(4) unnamed_addr constant [8 x i8] c"USE_MUL\00" + +declare i32 @__nvvm_reflect(i8*) +declare i8* @llvm.nvvm.ptr.constant.to.gen.p0i8.p4i8(i8 addrspace(4)*) + +define float @foo(float %a, float %b) { +; USE_MUL_0: define float @foo +; USE_MUL_0-NOT: call i32 @__nvvm_reflect +; USE_MUL_1: define float @foo +; USE_MUL_1-NOT: call i32 @__nvvm_reflect + %ptr = tail call i8* @llvm.nvvm.ptr.constant.to.gen.p0i8.p4i8(i8 addrspace(4)* getelementptr inbounds ([8 x i8] addrspace(4)* @str, i32 0, i32 0)) + %reflect = tail call i32 @__nvvm_reflect(i8* %ptr) + %cmp = icmp ugt i32 %reflect, 0 + br i1 %cmp, label %use_mul, label %use_add + +use_mul: +; USE_MUL_1: fmul float %a, %b +; USE_MUL_0-NOT: fadd float %a, %b + %ret1 = fmul float %a, %b + br label %exit + +use_add: +; USE_MUL_0: fadd float %a, %b +; USE_MUL_1-NOT: fmul float %a, %b + %ret2 = fadd float %a, %b + br label %exit + +exit: + %ret = phi float [%ret1, %use_mul], [%ret2, %use_add] + ret float %ret +} diff --git a/test/CodeGen/NVPTX/sched1.ll b/test/CodeGen/NVPTX/sched1.ll new file mode 100644 index 0000000000..03ab635e73 --- /dev/null +++ b/test/CodeGen/NVPTX/sched1.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s + +; Ensure source scheduling is working + +define void @foo(i32* %a) { +; CHECK: .func foo +; CHECK: ld.u32 +; CHECK-NEXT: ld.u32 +; CHECK-NEXT: ld.u32 +; CHECK-NEXT: ld.u32 +; CHECK-NEXT: add.s32 +; CHECK-NEXT: add.s32 +; CHECK-NEXT: add.s32 + %ptr0 = getelementptr i32* %a, i32 0 + %val0 = load i32* %ptr0 + %ptr1 = getelementptr i32* %a, i32 1 + %val1 = load i32* %ptr1 + %ptr2 = getelementptr i32* %a, i32 2 + %val2 = load i32* %ptr2 + %ptr3 = getelementptr i32* %a, i32 3 + %val3 = load i32* %ptr3 + + %t0 = add i32 %val0, %val1 + %t1 = add i32 %t0, %val2 + %t2 = add i32 %t1, %val3 + + store i32 %t2, i32* %a + + ret void +} + diff --git a/test/CodeGen/NVPTX/sched2.ll b/test/CodeGen/NVPTX/sched2.ll new file mode 100644 index 0000000000..71a9a4963f --- /dev/null +++ b/test/CodeGen/NVPTX/sched2.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s + +define void @foo(<2 x i32>* %a) { +; CHECK: .func foo +; CHECK: ld.v2.u32 +; CHECK-NEXT: ld.v2.u32 +; CHECK-NEXT: ld.v2.u32 +; CHECK-NEXT: ld.v2.u32 +; CHECK-NEXT: add.s32 +; CHECK-NEXT: add.s32 +; CHECK-NEXT: add.s32 +; CHECK-NEXT: add.s32 +; CHECK-NEXT: add.s32 +; CHECK-NEXT: add.s32 + %ptr0 = getelementptr <2 x i32>* %a, i32 0 + %val0 = load <2 x i32>* %ptr0 + %ptr1 = getelementptr <2 x i32>* %a, i32 1 + %val1 = load <2 x i32>* %ptr1 + %ptr2 = getelementptr <2 x i32>* %a, i32 2 + %val2 = load <2 x i32>* %ptr2 + %ptr3 = getelementptr <2 x i32>* %a, i32 3 + %val3 = load <2 x i32>* %ptr3 + + %t0 = add <2 x i32> %val0, %val1 + %t1 = add <2 x i32> %t0, %val2 + %t2 = add <2 x i32> %t1, %val3 + + store <2 x i32> %t2, <2 x i32>* %a + + ret void +} + diff --git a/test/CodeGen/NVPTX/sm-version-10.ll b/test/CodeGen/NVPTX/sm-version-10.ll deleted file mode 100644 index 9324a37809..0000000000 --- a/test/CodeGen/NVPTX/sm-version-10.ll +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s - - -; CHECK: .target sm_10 - diff --git a/test/CodeGen/NVPTX/sm-version-11.ll b/test/CodeGen/NVPTX/sm-version-11.ll deleted file mode 100644 index 9033a4eba5..0000000000 --- a/test/CodeGen/NVPTX/sm-version-11.ll +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_11 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_11 | FileCheck %s - - -; CHECK: .target sm_11 - diff --git a/test/CodeGen/NVPTX/sm-version-12.ll b/test/CodeGen/NVPTX/sm-version-12.ll deleted file mode 100644 index d8ee85c901..0000000000 --- a/test/CodeGen/NVPTX/sm-version-12.ll +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_12 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_12 | FileCheck %s - - -; CHECK: .target sm_12 - diff --git a/test/CodeGen/NVPTX/sm-version-13.ll b/test/CodeGen/NVPTX/sm-version-13.ll deleted file mode 100644 index ad67d642ce..0000000000 --- a/test/CodeGen/NVPTX/sm-version-13.ll +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_13 | FileCheck %s -; RUN: llc < %s -march=nvptx64 -mcpu=sm_13 | FileCheck %s - - -; CHECK: .target sm_13 - diff --git a/test/CodeGen/NVPTX/st-addrspace.ll b/test/CodeGen/NVPTX/st-addrspace.ll index 54e04ae610..0b26d802df 100644 --- a/test/CodeGen/NVPTX/st-addrspace.ll +++ b/test/CodeGen/NVPTX/st-addrspace.ll @@ -1,6 +1,4 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s --check-prefix=PTX32 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32 -; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s --check-prefix=PTX64 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64 diff --git a/test/CodeGen/NVPTX/tuple-literal.ll b/test/CodeGen/NVPTX/tuple-literal.ll index 5c0cb2c15c..2b1f2c4b66 100644 --- a/test/CodeGen/NVPTX/tuple-literal.ll +++ b/test/CodeGen/NVPTX/tuple-literal.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_13 +; RUN: llc < %s -march=nvptx -mcpu=sm_20 define ptx_device void @test_function({i8, i8}*) { ret void diff --git a/test/CodeGen/NVPTX/vector-args.ll b/test/CodeGen/NVPTX/vector-args.ll new file mode 100644 index 0000000000..80deae4693 --- /dev/null +++ b/test/CodeGen/NVPTX/vector-args.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s + + +define float @foo(<2 x float> %a) { +; CHECK: .func (.param .b32 func_retval0) foo +; CHECK: .param .align 8 .b8 foo_param_0[8] +; CHECK: ld.param.f32 %f{{[0-9]+}} +; CHECK: ld.param.f32 %f{{[0-9]+}} + %t1 = fmul <2 x float> %a, %a + %t2 = extractelement <2 x float> %t1, i32 0 + %t3 = extractelement <2 x float> %t1, i32 1 + %t4 = fadd float %t2, %t3 + ret float %t4 +} + + +define float @bar(<4 x float> %a) { +; CHECK: .func (.param .b32 func_retval0) bar +; CHECK: .param .align 16 .b8 bar_param_0[16] +; CHECK: ld.param.f32 %f{{[0-9]+}} +; CHECK: ld.param.f32 %f{{[0-9]+}} + %t1 = fmul <4 x float> %a, %a + %t2 = extractelement <4 x float> %t1, i32 0 + %t3 = extractelement <4 x float> %t1, i32 1 + %t4 = fadd float %t2, %t3 + ret float %t4 +} diff --git a/test/CodeGen/NVPTX/vector-loads.ll b/test/CodeGen/NVPTX/vector-loads.ll index f5a1795e3c..58882bf166 100644 --- a/test/CodeGen/NVPTX/vector-loads.ll +++ b/test/CodeGen/NVPTX/vector-loads.ll @@ -9,7 +9,7 @@ define void @foo(<2 x float>* %a) { ; CHECK: .func foo -; CHECK: ld.v2.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}}, [%r{{[0-9]+}}]; +; CHECK: ld.v2.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}} %t1 = load <2 x float>* %a %t2 = fmul <2 x float> %t1, %t1 store <2 x float> %t2, <2 x float>* %a @@ -18,7 +18,7 @@ define void @foo(<2 x float>* %a) { define void @foo2(<4 x float>* %a) { ; CHECK: .func foo2 -; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [%r{{[0-9]+}}]; +; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}} %t1 = load <4 x float>* %a %t2 = fmul <4 x float> %t1, %t1 store <4 x float> %t2, <4 x float>* %a @@ -27,8 +27,8 @@ define void @foo2(<4 x float>* %a) { define void @foo3(<8 x float>* %a) { ; CHECK: .func foo3 -; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [%r{{[0-9]+}}]; -; CHECK-NEXT: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [%r{{[0-9]+}}+16]; +; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}} +; CHECK-NEXT: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}} %t1 = load <8 x float>* %a %t2 = fmul <8 x float> %t1, %t1 store <8 x float> %t2, <8 x float>* %a @@ -39,7 +39,7 @@ define void @foo3(<8 x float>* %a) { define void @foo4(<2 x i32>* %a) { ; CHECK: .func foo4 -; CHECK: ld.v2.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}}, [%r{{[0-9]+}}]; +; CHECK: ld.v2.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}} %t1 = load <2 x i32>* %a %t2 = mul <2 x i32> %t1, %t1 store <2 x i32> %t2, <2 x i32>* %a @@ -48,7 +48,7 @@ define void @foo4(<2 x i32>* %a) { define void @foo5(<4 x i32>* %a) { ; CHECK: .func foo5 -; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}, [%r{{[0-9]+}}]; +; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}} %t1 = load <4 x i32>* %a %t2 = mul <4 x i32> %t1, %t1 store <4 x i32> %t2, <4 x i32>* %a @@ -57,8 +57,8 @@ define void @foo5(<4 x i32>* %a) { define void @foo6(<8 x i32>* %a) { ; CHECK: .func foo6 -; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}, [%r{{[0-9]+}}]; -; CHECK-NEXT: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}, [%r{{[0-9]+}}+16]; +; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}} +; CHECK-NEXT: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}} %t1 = load <8 x i32>* %a %t2 = mul <8 x i32> %t1, %t1 store <8 x i32> %t2, <8 x i32>* %a diff --git a/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll b/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll index 82ef2b82cb..b6feb5abbc 100644 --- a/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll +++ b/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc64 | grep dst | count 4 +; RUN: llc < %s -march=ppc64 -mattr=+altivec | grep dst | count 4 define hidden void @_Z4borkPc(i8* %image) { entry: diff --git a/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll index 84aa40c4b5..91253daae3 100644 --- a/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll +++ b/test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll @@ -10,8 +10,8 @@ target triple = "powerpc-apple-darwin10.0" define void @foo(i32 %y) nounwind ssp { entry: ; CHECK: foo -; CHECK: add r3 -; CHECK: 0(r3) +; CHECK: add r2 +; CHECK: 0(r2) %y_addr = alloca i32 ; <i32*> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] store i32 %y, i32* %y_addr diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index 974a99a52c..097611a761 100644 --- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -2,21 +2,21 @@ ; ModuleID = 'hh.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" target triple = "powerpc-apple-darwin9.6" -; This formerly used R0 for both the stack address and CR. define void @foo() nounwind { entry: -;CHECK: mfcr r2 -;CHECK: lis r3, 1 -;CHECK: rlwinm r2, r2, 8, 0, 31 -;CHECK: ori r3, r3, 34524 -;CHECK: stwx r2, r1, r3 -; Make sure that the register scavenger returns the same temporary register. -;CHECK: mfcr r2 -;CHECK: lis r3, 1 -;CHECK: rlwinm r2, r2, 12, 0, 31 -;CHECK: ori r3, r3, 34520 -;CHECK: stwx r2, r1, r3 +; Note that part of what is being checked here is proper register reuse. +; CHECK: mfcr [[T1:r[0-9]+]] ; cr2 +; CHECK: lis [[T2:r[0-9]+]], 1 +; CHECK: addi r3, r1, 72 +; CHECK: rlwinm [[T1]], [[T1]], 8, 0, 31 +; CHECK: ori [[T2]], [[T2]], 34540 +; CHECK: stwx [[T1]], r1, [[T2]] +; CHECK: lis [[T3:r[0-9]+]], 1 +; CHECK: mfcr [[T4:r[0-9]+]] ; cr3 +; CHECK: ori [[T3]], [[T3]], 34536 +; CHECK: rlwinm [[T4]], [[T4]], 12, 0, 31 +; CHECK: stwx [[T4]], r1, [[T3]] %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1] @@ -25,11 +25,16 @@ entry: br label %return return: ; preds = %entry -;CHECK: lis r3, 1 -;CHECK: ori r3, r3, 34524 -;CHECK: lwzx r2, r1, r3 -;CHECK: rlwinm r2, r2, 24, 0, 31 -;CHECK: mtcrf 32, r2 +; CHECK: lis [[T1:r[0-9]+]], 1 +; CHECK: ori [[T1]], [[T1]], 34536 +; CHECK: lwzx [[T1]], r1, [[T1]] +; CHECK: rlwinm [[T1]], [[T1]], 20, 0, 31 +; CHECK: mtcrf 16, [[T1]] +; CHECK: lis [[T1]], 1 +; CHECK: ori [[T1]], [[T1]], 34540 +; CHECK: lwzx [[T1]], r1, [[T1]] +; CHECK: rlwinm [[T1]], [[T1]], 24, 0, 31 +; CHECK: mtcrf 32, [[T1]] ret void } diff --git a/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll b/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll index 72ae9d6c73..0dbc2d0180 100644 --- a/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll +++ b/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll @@ -18,8 +18,8 @@ entry: ; CHECK: _g: ; CHECK: mflr r0 ; CHECK: stw r0, 8(r1) -; CHECK: lwz r3, 0(r1) -; CHECK: lwz r3, 8(r3) +; CHECK: lwz r2, 0(r1) +; CHECK: lwz r3, 8(r2) %0 = tail call i8* @llvm.returnaddress(i32 1) ; <i8*> [#uses=1] ret i8* %0 } diff --git a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll index bf3d577a36..d1a3c9f46b 100644 --- a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll +++ b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll @@ -7,7 +7,7 @@ define i32 @main() nounwind { entry: ; Make sure we're generating references using the red zone ; CHECK: main: -; CHECK: stw r3, -12(r1) +; CHECK: stw r2, -12(r1) %retval = alloca i32 %0 = alloca i32 %"alloca point" = bitcast i32 0 to i32 diff --git a/test/CodeGen/PowerPC/DbgValueOtherTargets.test b/test/CodeGen/PowerPC/DbgValueOtherTargets.test index b1b338776b..9702934f7e 100644 --- a/test/CodeGen/PowerPC/DbgValueOtherTargets.test +++ b/test/CodeGen/PowerPC/DbgValueOtherTargets.test @@ -1 +1 @@ -; RUN: llc -O0 -march=ppc32 -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -march=ppc32 -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll b/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll index 6f985c819f..e8765deab0 100644 --- a/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll +++ b/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll @@ -1,9 +1,9 @@ ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \ -; RUN: grep "stw r4, 32751" +; RUN: grep "stw r3, 32751" ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \ -; RUN: grep "stw r4, 32751" +; RUN: grep "stw r3, 32751" ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \ -; RUN: grep "std r4, 9024" +; RUN: grep "std r3, 9024" define void @test() nounwind { store i32 0, i32* inttoptr (i64 48725999 to i32*) diff --git a/test/CodeGen/PowerPC/Stats/lit.local.cfg b/test/CodeGen/PowerPC/Stats/lit.local.cfg deleted file mode 100644 index 2608e139e9..0000000000 --- a/test/CodeGen/PowerPC/Stats/lit.local.cfg +++ /dev/null @@ -1,8 +0,0 @@ -config.suffixes = ['.ll', '.c', '.cpp'] - -targets = set(config.root.targets_to_build.split()) -if not 'PowerPC' in targets: - config.unsupported = True - -if not config.root.enable_assertions: - config.unsupported = True diff --git a/test/CodeGen/PowerPC/allocate-r0.ll b/test/CodeGen/PowerPC/allocate-r0.ll new file mode 100644 index 0000000000..1cf4cec076 --- /dev/null +++ b/test/CodeGen/PowerPC/allocate-r0.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i64 @foo(i64 %a) nounwind { +entry: + call void asm sideeffect "", "~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12}"() nounwind + br label %return + +; CHECK: @foo +; Because r0 is allocatable, we can use it to hold r3 without spilling. +; CHECK: mr 0, 3 +; CHECK: mr 3, 0 + +return: ; preds = %entry + ret i64 %a +} + diff --git a/test/CodeGen/PowerPC/asym-regclass-copy.ll b/test/CodeGen/PowerPC/asym-regclass-copy.ll new file mode 100644 index 0000000000..d04a6c98ee --- /dev/null +++ b/test/CodeGen/PowerPC/asym-regclass-copy.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; This tests that the GPRC/GPRC_NOR0 intersection subclass relationship with +; GPRC is handled correctly. When it was not, this test would assert. + +@gen_random.last = external unnamed_addr global i64, align 8 +@.str = external unnamed_addr constant [4 x i8], align 1 + +declare double @gen_random(double) #0 + +declare void @benchmark_heapsort(i32 signext, double* nocapture) #0 + +define signext i32 @main(i32 signext %argc, i8** nocapture %argv) #0 { +entry: + br i1 undef, label %cond.true, label %cond.end + +cond.true: ; preds = %entry + br label %cond.end + +cond.end: ; preds = %cond.true, %entry + %cond = phi i32 [ 0, %cond.true ], [ 8000000, %entry ] + %add = add i32 %cond, 1 + %conv = sext i32 %add to i64 + %mul = shl nsw i64 %conv, 3 + %call1 = tail call noalias i8* @malloc(i64 %mul) #1 + br i1 undef, label %for.end, label %for.body.lr.ph + +for.body.lr.ph: ; preds = %cond.end + br label %for.body + +for.body: ; preds = %for.body, %for.body.lr.ph + %indvars.iv = phi i64 [ 1, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ] + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %add + br i1 %exitcond, label %for.cond.for.end_crit_edge, label %for.body + +for.cond.for.end_crit_edge: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.cond.for.end_crit_edge, %cond.end + ret i32 0 +} + +declare noalias i8* @malloc(i64) #0 + +declare signext i32 @printf(i8* nocapture, ...) #0 + +declare void @free(i8* nocapture) #0 + +declare i64 @strtol(i8*, i8** nocapture, i32 signext) #0 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind } diff --git a/test/CodeGen/PowerPC/atomic-1.ll b/test/CodeGen/PowerPC/atomic-1.ll index cbfa4094fb..838db20ddd 100644 --- a/test/CodeGen/PowerPC/atomic-1.ll +++ b/test/CodeGen/PowerPC/atomic-1.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=ppc32 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 | FileCheck %s define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { ; CHECK: exchange_and_add: -; CHECK: lwarx +; CHECK: lwarx {{r[0-9]+}}, 0, {{r[0-9]+}} %tmp = atomicrmw add i32* %mem, i32 %val monotonic -; CHECK: stwcx. +; CHECK: stwcx. {{r[0-9]+}}, 0, {{r[0-9]+}} ret i32 %tmp } diff --git a/test/CodeGen/PowerPC/bswap-load-store.ll b/test/CodeGen/PowerPC/bswap-load-store.ll index 4f6bfc7299..53bbc52167 100644 --- a/test/CodeGen/PowerPC/bswap-load-store.ll +++ b/test/CodeGen/PowerPC/bswap-load-store.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=ppc32 | FileCheck %s -check-prefix=X32 -; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -march=ppc32 -mcpu=ppc32 | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -march=ppc64 -mcpu=ppc64 | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s -check-prefix=PWR7 +; RUN: llc < %s -march=ppc32 -mcpu=pwr7 | FileCheck %s -check-prefix=X32 define void @STWBRX(i32 %i, i8* %ptr, i32 %off) { @@ -34,18 +36,47 @@ define i16 @LHBRX(i8* %ptr, i32 %off) { ret i16 %tmp6 } +define void @STDBRX(i64 %i, i8* %ptr, i64 %off) { + %tmp1 = getelementptr i8* %ptr, i64 %off ; <i8*> [#uses=1] + %tmp1.upgrd.1 = bitcast i8* %tmp1 to i64* ; <i64*> [#uses=1] + %tmp13 = tail call i64 @llvm.bswap.i64( i64 %i ) ; <i64> [#uses=1] + store i64 %tmp13, i64* %tmp1.upgrd.1 + ret void +} + +define i64 @LDBRX(i8* %ptr, i64 %off) { + %tmp1 = getelementptr i8* %ptr, i64 %off ; <i8*> [#uses=1] + %tmp1.upgrd.2 = bitcast i8* %tmp1 to i64* ; <i64*> [#uses=1] + %tmp = load i64* %tmp1.upgrd.2 ; <i64> [#uses=1] + %tmp14 = tail call i64 @llvm.bswap.i64( i64 %tmp ) ; <i64> [#uses=1] + ret i64 %tmp14 +} + declare i32 @llvm.bswap.i32(i32) declare i16 @llvm.bswap.i16(i16) +declare i64 @llvm.bswap.i64(i64) + ; X32: stwbrx ; X32: lwbrx ; X32: sthbrx ; X32: lhbrx +; X32-NOT: ldbrx +; X32-NOT: stdbrx ; X64: stwbrx ; X64: lwbrx ; X64: sthbrx ; X64: lhbrx +; X64-NOT: ldbrx +; X64-NOT: stdbrx + +; PWR7: stwbrx +; PWR7: lwbrx +; PWR7: sthbrx +; PWR7: lhbrx +; PWR7: stdbrx +; PWR7: ldbrx diff --git a/test/CodeGen/PowerPC/cr-spills.ll b/test/CodeGen/PowerPC/cr-spills.ll new file mode 100644 index 0000000000..d6df7a2376 --- /dev/null +++ b/test/CodeGen/PowerPC/cr-spills.ll @@ -0,0 +1,409 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; This test case triggers several functions related to cr spilling, both in +; frame lowering and to handle cr register pressure. When the register kill +; flags were not being set correctly, this would cause the register scavenger to +; assert. + +@SetupFastFullPelSearch.orig_pels = external unnamed_addr global [768 x i16], align 2 +@weight_luma = external global i32 +@offset_luma = external global i32 +@wp_luma_round = external global i32, align 4 +@luma_log_weight_denom = external global i32, align 4 + +define void @SetupFastFullPelSearch() #0 { +entry: + %mul10 = mul nsw i32 undef, undef + br i1 undef, label %land.end, label %land.lhs.true + +land.lhs.true: ; preds = %entry + switch i32 0, label %land.end [ + i32 0, label %land.rhs + i32 3, label %land.rhs + ] + +land.rhs: ; preds = %land.lhs.true, %land.lhs.true + %tobool21 = icmp ne i32 undef, 0 + br label %land.end + +land.end: ; preds = %land.rhs, %land.lhs.true, %entry + %0 = phi i1 [ %tobool21, %land.rhs ], [ false, %land.lhs.true ], [ false, %entry ] + %cond = load i32** undef, align 8 + br i1 undef, label %if.then95, label %for.body.lr.ph + +if.then95: ; preds = %land.end + %cmp.i4.i1427 = icmp slt i32 undef, undef + br label %for.body.lr.ph + +for.body.lr.ph: ; preds = %if.then95, %land.end + br label %for.body + +for.body: ; preds = %for.body, %for.body.lr.ph + br i1 undef, label %for.body, label %for.body252 + +for.body252: ; preds = %for.inc997, %for.body + %shl263 = add i32 undef, 80 + br i1 %0, label %for.cond286.preheader, label %for.cond713.preheader + +for.cond286.preheader: ; preds = %for.body252 + br label %for.cond290.preheader + +for.cond290.preheader: ; preds = %for.end520, %for.cond286.preheader + %srcptr.31595 = phi i16* [ getelementptr inbounds ([768 x i16]* @SetupFastFullPelSearch.orig_pels, i64 0, i64 0), %for.cond286.preheader ], [ null, %for.end520 ] + %1 = load i32* undef, align 4, !tbaa !0 + %2 = load i32* @weight_luma, align 4, !tbaa !0 + %3 = load i32* @wp_luma_round, align 4, !tbaa !0 + %4 = load i32* @luma_log_weight_denom, align 4, !tbaa !0 + %5 = load i32* @offset_luma, align 4, !tbaa !0 + %incdec.ptr502.sum = add i64 undef, 16 + br label %for.body293 + +for.body293: ; preds = %for.body293, %for.cond290.preheader + %srcptr.41591 = phi i16* [ %srcptr.31595, %for.cond290.preheader ], [ undef, %for.body293 ] + %refptr.11590 = phi i16* [ undef, %for.cond290.preheader ], [ %add.ptr517, %for.body293 ] + %LineSadBlk0.01588 = phi i32 [ 0, %for.cond290.preheader ], [ %add346, %for.body293 ] + %LineSadBlk1.01587 = phi i32 [ 0, %for.cond290.preheader ], [ %add402, %for.body293 ] + %LineSadBlk3.01586 = phi i32 [ 0, %for.cond290.preheader ], [ %add514, %for.body293 ] + %LineSadBlk2.01585 = phi i32 [ 0, %for.cond290.preheader ], [ %add458, %for.body293 ] + %6 = load i16* %refptr.11590, align 2, !tbaa !3 + %conv294 = zext i16 %6 to i32 + %mul295 = mul nsw i32 %conv294, %2 + %add296 = add nsw i32 %mul295, %3 + %shr = ashr i32 %add296, %4 + %add297 = add nsw i32 %shr, %5 + %cmp.i.i1513 = icmp sgt i32 %add297, 0 + %cond.i.i1514 = select i1 %cmp.i.i1513, i32 %add297, i32 0 + %cmp.i4.i1515 = icmp slt i32 %cond.i.i1514, %1 + %cond.i5.i1516 = select i1 %cmp.i4.i1515, i32 %cond.i.i1514, i32 %1 + %7 = load i16* %srcptr.41591, align 2, !tbaa !3 + %conv300 = zext i16 %7 to i32 + %sub301 = sub nsw i32 %cond.i5.i1516, %conv300 + %idxprom302 = sext i32 %sub301 to i64 + %arrayidx303 = getelementptr inbounds i32* %cond, i64 %idxprom302 + %8 = load i32* %arrayidx303, align 4, !tbaa !0 + %add304 = add nsw i32 %8, %LineSadBlk0.01588 + %9 = load i32* undef, align 4, !tbaa !0 + %add318 = add nsw i32 %add304, %9 + %10 = load i16* undef, align 2, !tbaa !3 + %conv321 = zext i16 %10 to i32 + %mul322 = mul nsw i32 %conv321, %2 + %add323 = add nsw i32 %mul322, %3 + %shr324 = ashr i32 %add323, %4 + %add325 = add nsw i32 %shr324, %5 + %cmp.i.i1505 = icmp sgt i32 %add325, 0 + %cond.i.i1506 = select i1 %cmp.i.i1505, i32 %add325, i32 0 + %cmp.i4.i1507 = icmp slt i32 %cond.i.i1506, %1 + %cond.i5.i1508 = select i1 %cmp.i4.i1507, i32 %cond.i.i1506, i32 %1 + %sub329 = sub nsw i32 %cond.i5.i1508, 0 + %idxprom330 = sext i32 %sub329 to i64 + %arrayidx331 = getelementptr inbounds i32* %cond, i64 %idxprom330 + %11 = load i32* %arrayidx331, align 4, !tbaa !0 + %add332 = add nsw i32 %add318, %11 + %cmp.i.i1501 = icmp sgt i32 undef, 0 + %cond.i.i1502 = select i1 %cmp.i.i1501, i32 undef, i32 0 + %cmp.i4.i1503 = icmp slt i32 %cond.i.i1502, %1 + %cond.i5.i1504 = select i1 %cmp.i4.i1503, i32 %cond.i.i1502, i32 %1 + %incdec.ptr341 = getelementptr inbounds i16* %srcptr.41591, i64 4 + %12 = load i16* null, align 2, !tbaa !3 + %conv342 = zext i16 %12 to i32 + %sub343 = sub nsw i32 %cond.i5.i1504, %conv342 + %idxprom344 = sext i32 %sub343 to i64 + %arrayidx345 = getelementptr inbounds i32* %cond, i64 %idxprom344 + %13 = load i32* %arrayidx345, align 4, !tbaa !0 + %add346 = add nsw i32 %add332, %13 + %incdec.ptr348 = getelementptr inbounds i16* %refptr.11590, i64 5 + %14 = load i16* null, align 2, !tbaa !3 + %conv349 = zext i16 %14 to i32 + %mul350 = mul nsw i32 %conv349, %2 + %add351 = add nsw i32 %mul350, %3 + %shr352 = ashr i32 %add351, %4 + %add353 = add nsw i32 %shr352, %5 + %cmp.i.i1497 = icmp sgt i32 %add353, 0 + %cond.i.i1498 = select i1 %cmp.i.i1497, i32 %add353, i32 0 + %cmp.i4.i1499 = icmp slt i32 %cond.i.i1498, %1 + %cond.i5.i1500 = select i1 %cmp.i4.i1499, i32 %cond.i.i1498, i32 %1 + %incdec.ptr355 = getelementptr inbounds i16* %srcptr.41591, i64 5 + %15 = load i16* %incdec.ptr341, align 2, !tbaa !3 + %conv356 = zext i16 %15 to i32 + %sub357 = sub nsw i32 %cond.i5.i1500, %conv356 + %idxprom358 = sext i32 %sub357 to i64 + %arrayidx359 = getelementptr inbounds i32* %cond, i64 %idxprom358 + %16 = load i32* %arrayidx359, align 4, !tbaa !0 + %add360 = add nsw i32 %16, %LineSadBlk1.01587 + %incdec.ptr362 = getelementptr inbounds i16* %refptr.11590, i64 6 + %17 = load i16* %incdec.ptr348, align 2, !tbaa !3 + %conv363 = zext i16 %17 to i32 + %mul364 = mul nsw i32 %conv363, %2 + %add365 = add nsw i32 %mul364, %3 + %shr366 = ashr i32 %add365, %4 + %add367 = add nsw i32 %shr366, %5 + %cmp.i.i1493 = icmp sgt i32 %add367, 0 + %cond.i.i1494 = select i1 %cmp.i.i1493, i32 %add367, i32 0 + %cmp.i4.i1495 = icmp slt i32 %cond.i.i1494, %1 + %cond.i5.i1496 = select i1 %cmp.i4.i1495, i32 %cond.i.i1494, i32 %1 + %incdec.ptr369 = getelementptr inbounds i16* %srcptr.41591, i64 6 + %18 = load i16* %incdec.ptr355, align 2, !tbaa !3 + %conv370 = zext i16 %18 to i32 + %sub371 = sub nsw i32 %cond.i5.i1496, %conv370 + %idxprom372 = sext i32 %sub371 to i64 + %arrayidx373 = getelementptr inbounds i32* %cond, i64 %idxprom372 + %19 = load i32* %arrayidx373, align 4, !tbaa !0 + %add374 = add nsw i32 %add360, %19 + %incdec.ptr376 = getelementptr inbounds i16* %refptr.11590, i64 7 + %20 = load i16* %incdec.ptr362, align 2, !tbaa !3 + %conv377 = zext i16 %20 to i32 + %mul378 = mul nsw i32 %conv377, %2 + %add379 = add nsw i32 %mul378, %3 + %shr380 = ashr i32 %add379, %4 + %add381 = add nsw i32 %shr380, %5 + %cmp.i.i1489 = icmp sgt i32 %add381, 0 + %cond.i.i1490 = select i1 %cmp.i.i1489, i32 %add381, i32 0 + %cmp.i4.i1491 = icmp slt i32 %cond.i.i1490, %1 + %cond.i5.i1492 = select i1 %cmp.i4.i1491, i32 %cond.i.i1490, i32 %1 + %incdec.ptr383 = getelementptr inbounds i16* %srcptr.41591, i64 7 + %21 = load i16* %incdec.ptr369, align 2, !tbaa !3 + %conv384 = zext i16 %21 to i32 + %sub385 = sub nsw i32 %cond.i5.i1492, %conv384 + %idxprom386 = sext i32 %sub385 to i64 + %arrayidx387 = getelementptr inbounds i32* %cond, i64 %idxprom386 + %22 = load i32* %arrayidx387, align 4, !tbaa !0 + %add388 = add nsw i32 %add374, %22 + %23 = load i16* %incdec.ptr376, align 2, !tbaa !3 + %conv391 = zext i16 %23 to i32 + %mul392 = mul nsw i32 %conv391, %2 + %add395 = add nsw i32 0, %5 + %cmp.i.i1485 = icmp sgt i32 %add395, 0 + %cond.i.i1486 = select i1 %cmp.i.i1485, i32 %add395, i32 0 + %cmp.i4.i1487 = icmp slt i32 %cond.i.i1486, %1 + %cond.i5.i1488 = select i1 %cmp.i4.i1487, i32 %cond.i.i1486, i32 %1 + %incdec.ptr397 = getelementptr inbounds i16* %srcptr.41591, i64 8 + %24 = load i16* %incdec.ptr383, align 2, !tbaa !3 + %conv398 = zext i16 %24 to i32 + %sub399 = sub nsw i32 %cond.i5.i1488, %conv398 + %idxprom400 = sext i32 %sub399 to i64 + %arrayidx401 = getelementptr inbounds i32* %cond, i64 %idxprom400 + %25 = load i32* %arrayidx401, align 4, !tbaa !0 + %add402 = add nsw i32 %add388, %25 + %incdec.ptr404 = getelementptr inbounds i16* %refptr.11590, i64 9 + %cmp.i4.i1483 = icmp slt i32 undef, %1 + %cond.i5.i1484 = select i1 %cmp.i4.i1483, i32 undef, i32 %1 + %26 = load i16* %incdec.ptr397, align 2, !tbaa !3 + %conv412 = zext i16 %26 to i32 + %sub413 = sub nsw i32 %cond.i5.i1484, %conv412 + %idxprom414 = sext i32 %sub413 to i64 + %arrayidx415 = getelementptr inbounds i32* %cond, i64 %idxprom414 + %27 = load i32* %arrayidx415, align 4, !tbaa !0 + %add416 = add nsw i32 %27, %LineSadBlk2.01585 + %incdec.ptr418 = getelementptr inbounds i16* %refptr.11590, i64 10 + %28 = load i16* %incdec.ptr404, align 2, !tbaa !3 + %conv419 = zext i16 %28 to i32 + %mul420 = mul nsw i32 %conv419, %2 + %add421 = add nsw i32 %mul420, %3 + %shr422 = ashr i32 %add421, %4 + %add423 = add nsw i32 %shr422, %5 + %cmp.i.i1477 = icmp sgt i32 %add423, 0 + %cond.i.i1478 = select i1 %cmp.i.i1477, i32 %add423, i32 0 + %cmp.i4.i1479 = icmp slt i32 %cond.i.i1478, %1 + %cond.i5.i1480 = select i1 %cmp.i4.i1479, i32 %cond.i.i1478, i32 %1 + %incdec.ptr425 = getelementptr inbounds i16* %srcptr.41591, i64 10 + %sub427 = sub nsw i32 %cond.i5.i1480, 0 + %idxprom428 = sext i32 %sub427 to i64 + %arrayidx429 = getelementptr inbounds i32* %cond, i64 %idxprom428 + %29 = load i32* %arrayidx429, align 4, !tbaa !0 + %add430 = add nsw i32 %add416, %29 + %incdec.ptr432 = getelementptr inbounds i16* %refptr.11590, i64 11 + %30 = load i16* %incdec.ptr418, align 2, !tbaa !3 + %conv433 = zext i16 %30 to i32 + %mul434 = mul nsw i32 %conv433, %2 + %add435 = add nsw i32 %mul434, %3 + %shr436 = ashr i32 %add435, %4 + %add437 = add nsw i32 %shr436, %5 + %cmp.i.i1473 = icmp sgt i32 %add437, 0 + %cond.i.i1474 = select i1 %cmp.i.i1473, i32 %add437, i32 0 + %cmp.i4.i1475 = icmp slt i32 %cond.i.i1474, %1 + %cond.i5.i1476 = select i1 %cmp.i4.i1475, i32 %cond.i.i1474, i32 %1 + %31 = load i16* %incdec.ptr425, align 2, !tbaa !3 + %conv440 = zext i16 %31 to i32 + %sub441 = sub nsw i32 %cond.i5.i1476, %conv440 + %idxprom442 = sext i32 %sub441 to i64 + %arrayidx443 = getelementptr inbounds i32* %cond, i64 %idxprom442 + %32 = load i32* %arrayidx443, align 4, !tbaa !0 + %add444 = add nsw i32 %add430, %32 + %incdec.ptr446 = getelementptr inbounds i16* %refptr.11590, i64 12 + %33 = load i16* %incdec.ptr432, align 2, !tbaa !3 + %conv447 = zext i16 %33 to i32 + %mul448 = mul nsw i32 %conv447, %2 + %add449 = add nsw i32 %mul448, %3 + %shr450 = ashr i32 %add449, %4 + %add451 = add nsw i32 %shr450, %5 + %cmp.i.i1469 = icmp sgt i32 %add451, 0 + %cond.i.i1470 = select i1 %cmp.i.i1469, i32 %add451, i32 0 + %cmp.i4.i1471 = icmp slt i32 %cond.i.i1470, %1 + %cond.i5.i1472 = select i1 %cmp.i4.i1471, i32 %cond.i.i1470, i32 %1 + %incdec.ptr453 = getelementptr inbounds i16* %srcptr.41591, i64 12 + %34 = load i16* undef, align 2, !tbaa !3 + %conv454 = zext i16 %34 to i32 + %sub455 = sub nsw i32 %cond.i5.i1472, %conv454 + %idxprom456 = sext i32 %sub455 to i64 + %arrayidx457 = getelementptr inbounds i32* %cond, i64 %idxprom456 + %35 = load i32* %arrayidx457, align 4, !tbaa !0 + %add458 = add nsw i32 %add444, %35 + %incdec.ptr460 = getelementptr inbounds i16* %refptr.11590, i64 13 + %36 = load i16* %incdec.ptr446, align 2, !tbaa !3 + %conv461 = zext i16 %36 to i32 + %mul462 = mul nsw i32 %conv461, %2 + %add463 = add nsw i32 %mul462, %3 + %shr464 = ashr i32 %add463, %4 + %add465 = add nsw i32 %shr464, %5 + %cmp.i.i1465 = icmp sgt i32 %add465, 0 + %cond.i.i1466 = select i1 %cmp.i.i1465, i32 %add465, i32 0 + %cmp.i4.i1467 = icmp slt i32 %cond.i.i1466, %1 + %cond.i5.i1468 = select i1 %cmp.i4.i1467, i32 %cond.i.i1466, i32 %1 + %incdec.ptr467 = getelementptr inbounds i16* %srcptr.41591, i64 13 + %37 = load i16* %incdec.ptr453, align 2, !tbaa !3 + %conv468 = zext i16 %37 to i32 + %sub469 = sub nsw i32 %cond.i5.i1468, %conv468 + %idxprom470 = sext i32 %sub469 to i64 + %arrayidx471 = getelementptr inbounds i32* %cond, i64 %idxprom470 + %38 = load i32* %arrayidx471, align 4, !tbaa !0 + %add472 = add nsw i32 %38, %LineSadBlk3.01586 + %incdec.ptr474 = getelementptr inbounds i16* %refptr.11590, i64 14 + %add477 = add nsw i32 0, %3 + %shr478 = ashr i32 %add477, %4 + %add479 = add nsw i32 %shr478, %5 + %cmp.i.i1461 = icmp sgt i32 %add479, 0 + %cond.i.i1462 = select i1 %cmp.i.i1461, i32 %add479, i32 0 + %cmp.i4.i1463 = icmp slt i32 %cond.i.i1462, %1 + %cond.i5.i1464 = select i1 %cmp.i4.i1463, i32 %cond.i.i1462, i32 %1 + %incdec.ptr481 = getelementptr inbounds i16* %srcptr.41591, i64 14 + %39 = load i16* %incdec.ptr467, align 2, !tbaa !3 + %conv482 = zext i16 %39 to i32 + %sub483 = sub nsw i32 %cond.i5.i1464, %conv482 + %idxprom484 = sext i32 %sub483 to i64 + %arrayidx485 = getelementptr inbounds i32* %cond, i64 %idxprom484 + %40 = load i32* %arrayidx485, align 4, !tbaa !0 + %add486 = add nsw i32 %add472, %40 + %incdec.ptr488 = getelementptr inbounds i16* %refptr.11590, i64 15 + %41 = load i16* %incdec.ptr474, align 2, !tbaa !3 + %conv489 = zext i16 %41 to i32 + %mul490 = mul nsw i32 %conv489, %2 + %add491 = add nsw i32 %mul490, %3 + %shr492 = ashr i32 %add491, %4 + %add493 = add nsw i32 %shr492, %5 + %cmp.i.i1457 = icmp sgt i32 %add493, 0 + %cond.i.i1458 = select i1 %cmp.i.i1457, i32 %add493, i32 0 + %cmp.i4.i1459 = icmp slt i32 %cond.i.i1458, %1 + %cond.i5.i1460 = select i1 %cmp.i4.i1459, i32 %cond.i.i1458, i32 %1 + %incdec.ptr495 = getelementptr inbounds i16* %srcptr.41591, i64 15 + %42 = load i16* %incdec.ptr481, align 2, !tbaa !3 + %conv496 = zext i16 %42 to i32 + %sub497 = sub nsw i32 %cond.i5.i1460, %conv496 + %idxprom498 = sext i32 %sub497 to i64 + %arrayidx499 = getelementptr inbounds i32* %cond, i64 %idxprom498 + %43 = load i32* %arrayidx499, align 4, !tbaa !0 + %add500 = add nsw i32 %add486, %43 + %44 = load i16* %incdec.ptr488, align 2, !tbaa !3 + %conv503 = zext i16 %44 to i32 + %mul504 = mul nsw i32 %conv503, %2 + %add505 = add nsw i32 %mul504, %3 + %shr506 = ashr i32 %add505, %4 + %add507 = add nsw i32 %shr506, %5 + %cmp.i.i1453 = icmp sgt i32 %add507, 0 + %cond.i.i1454 = select i1 %cmp.i.i1453, i32 %add507, i32 0 + %cmp.i4.i1455 = icmp slt i32 %cond.i.i1454, %1 + %cond.i5.i1456 = select i1 %cmp.i4.i1455, i32 %cond.i.i1454, i32 %1 + %45 = load i16* %incdec.ptr495, align 2, !tbaa !3 + %conv510 = zext i16 %45 to i32 + %sub511 = sub nsw i32 %cond.i5.i1456, %conv510 + %idxprom512 = sext i32 %sub511 to i64 + %arrayidx513 = getelementptr inbounds i32* %cond, i64 %idxprom512 + %46 = load i32* %arrayidx513, align 4, !tbaa !0 + %add514 = add nsw i32 %add500, %46 + %add.ptr517 = getelementptr inbounds i16* %refptr.11590, i64 %incdec.ptr502.sum + %exitcond1692 = icmp eq i32 undef, 4 + br i1 %exitcond1692, label %for.end520, label %for.body293 + +for.end520: ; preds = %for.body293 + store i32 %add346, i32* undef, align 4, !tbaa !0 + store i32 %add402, i32* undef, align 4, !tbaa !0 + store i32 %add458, i32* undef, align 4, !tbaa !0 + store i32 %add514, i32* null, align 4, !tbaa !0 + br i1 undef, label %for.end543, label %for.cond290.preheader + +for.end543: ; preds = %for.end520 + br i1 undef, label %for.inc997, label %for.body549 + +for.body549: ; preds = %for.inc701, %for.end543 + %call554 = call i16* null(i16**** null, i32 signext undef, i32 signext %shl263) #1 + br label %for.cond559.preheader + +for.cond559.preheader: ; preds = %for.cond559.preheader, %for.body549 + br i1 undef, label %for.inc701, label %for.cond559.preheader + +for.inc701: ; preds = %for.cond559.preheader + br i1 undef, label %for.inc997, label %for.body549 + +for.cond713.preheader: ; preds = %for.end850, %for.body252 + br label %for.body716 + +for.body716: ; preds = %for.body716, %for.cond713.preheader + br i1 undef, label %for.end850, label %for.body716 + +for.end850: ; preds = %for.body716 + br i1 undef, label %for.end873, label %for.cond713.preheader + +for.end873: ; preds = %for.end850 + br i1 undef, label %for.inc997, label %for.body879 + +for.body879: ; preds = %for.inc992, %for.end873 + br label %for.cond889.preheader + +for.cond889.preheader: ; preds = %for.end964, %for.body879 + br i1 undef, label %for.cond894.preheader.lr.ph, label %for.end964 + +for.cond894.preheader.lr.ph: ; preds = %for.cond889.preheader + br label %for.body898.lr.ph.us + +for.end957.us: ; preds = %for.body946.us + br i1 undef, label %for.body898.lr.ph.us, label %for.end964 + +for.body946.us: ; preds = %for.body930.us, %for.body946.us + br i1 false, label %for.body946.us, label %for.end957.us + +for.body930.us: ; preds = %for.body914.us, %for.body930.us + br i1 undef, label %for.body930.us, label %for.body946.us + +for.body914.us: ; preds = %for.body898.us, %for.body914.us + br i1 undef, label %for.body914.us, label %for.body930.us + +for.body898.us: ; preds = %for.body898.lr.ph.us, %for.body898.us + br i1 undef, label %for.body898.us, label %for.body914.us + +for.body898.lr.ph.us: ; preds = %for.end957.us, %for.cond894.preheader.lr.ph + br label %for.body898.us + +for.end964: ; preds = %for.end957.us, %for.cond889.preheader + %inc990 = add nsw i32 undef, 1 + br i1 false, label %for.inc992, label %for.cond889.preheader + +for.inc992: ; preds = %for.end964 + br i1 false, label %for.inc997, label %for.body879 + +for.inc997: ; preds = %for.inc992, %for.end873, %for.inc701, %for.end543 + %cmp250 = icmp slt i32 undef, %mul10 + br i1 %cmp250, label %for.body252, label %for.end999 + +for.end999: ; preds = %for.inc997 + ret void +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind } + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} +!3 = metadata !{metadata !"short", metadata !1} diff --git a/test/CodeGen/PowerPC/ctr-cleanup.ll b/test/CodeGen/PowerPC/ctr-cleanup.ll new file mode 100644 index 0000000000..04e4ffb0d4 --- /dev/null +++ b/test/CodeGen/PowerPC/ctr-cleanup.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -mcpu=a2 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define void @main() #0 { +entry: + br i1 undef, label %for.end, label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ] + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 5 + br i1 %exitcond, label %for.end, label %for.body + +; CHECK: @main +; CHECK: li {{[0-9]+}}, 4 +; CHECK-NOT: li {{[0-9]+}}, 4 +; CHECK: bdnz + +for.end: ; preds = %for.body, %entry + ret void +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/cttz.ll b/test/CodeGen/PowerPC/cttz.ll index 1d365d47a8..3757fa3e2f 100644 --- a/test/CodeGen/PowerPC/cttz.ll +++ b/test/CodeGen/PowerPC/cttz.ll @@ -1,10 +1,12 @@ ; Make sure this testcase does not use ctpop -; RUN: llc < %s -march=ppc32 | grep -i cntlzw +; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s declare i32 @llvm.cttz.i32(i32, i1) define i32 @bar(i32 %x) { entry: +; CHECK: @bar +; CHECK: cntlzw %tmp.1 = call i32 @llvm.cttz.i32( i32 %x, i1 true ) ; <i32> [#uses=1] ret i32 %tmp.1 } diff --git a/test/CodeGen/PowerPC/dbg.ll b/test/CodeGen/PowerPC/dbg.ll index 8d87cf793d..21e36618c5 100644 --- a/test/CodeGen/PowerPC/dbg.ll +++ b/test/CodeGen/PowerPC/dbg.ll @@ -16,10 +16,10 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"dbg.c", metadata !"/src", metadata !"clang version 3.1", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 720913, i32 12, metadata !6, metadata !"clang version 3.1", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} -!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !13} ; [ DW_TAG_subprogram ] +!5 = metadata !{i32 720942, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !13} ; [ DW_TAG_subprogram ] !6 = metadata !{i32 720937, metadata !"dbg.c", metadata !"/src", null} ; [ DW_TAG_file_type ] !7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !8 = metadata !{metadata !9, metadata !9, metadata !10} diff --git a/test/CodeGen/PowerPC/float-to-int.ll b/test/CodeGen/PowerPC/float-to-int.ll new file mode 100644 index 0000000000..39cd4f929f --- /dev/null +++ b/test/CodeGen/PowerPC/float-to-int.ll @@ -0,0 +1,93 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i64 @foo(float %a) nounwind { + %x = fptosi float %a to i64 + ret i64 %x + +; CHECK: @foo +; CHECK: fctidz [[REG:[0-9]+]], 1 +; CHECK: stfd [[REG]], +; CHECK: ld 3, +; CHECK: blr +} + +define i64 @foo2(double %a) nounwind { + %x = fptosi double %a to i64 + ret i64 %x + +; CHECK: @foo2 +; CHECK: fctidz [[REG:[0-9]+]], 1 +; CHECK: stfd [[REG]], +; CHECK: ld 3, +; CHECK: blr +} + +define i64 @foo3(float %a) nounwind { + %x = fptoui float %a to i64 + ret i64 %x + +; CHECK: @foo3 +; CHECK: fctiduz [[REG:[0-9]+]], 1 +; CHECK: stfd [[REG]], +; CHECK: ld 3, +; CHECK: blr +} + +define i64 @foo4(double %a) nounwind { + %x = fptoui double %a to i64 + ret i64 %x + +; CHECK: @foo4 +; CHECK: fctiduz [[REG:[0-9]+]], 1 +; CHECK: stfd [[REG]], +; CHECK: ld 3, +; CHECK: blr +} + +define i32 @goo(float %a) nounwind { + %x = fptosi float %a to i32 + ret i32 %x + +; CHECK: @goo +; CHECK: fctiwz [[REG:[0-9]+]], 1 +; CHECK: stfiwx [[REG]], +; CHECK: lwz 3, +; CHECK: blr +} + +define i32 @goo2(double %a) nounwind { + %x = fptosi double %a to i32 + ret i32 %x + +; CHECK: @goo2 +; CHECK: fctiwz [[REG:[0-9]+]], 1 +; CHECK: stfiwx [[REG]], +; CHECK: lwz 3, +; CHECK: blr +} + +define i32 @goo3(float %a) nounwind { + %x = fptoui float %a to i32 + ret i32 %x + +; CHECK: @goo3 +; CHECK: fctiwuz [[REG:[0-9]+]], 1 +; CHECK: stfiwx [[REG]], +; CHECK: lwz 3, +; CHECK: blr +} + +define i32 @goo4(double %a) nounwind { + %x = fptoui double %a to i32 + ret i32 %x + +; CHECK: @goo4 +; CHECK: fctiwuz [[REG:[0-9]+]], 1 +; CHECK: stfiwx [[REG]], +; CHECK: lwz 3, +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/frame-size.ll b/test/CodeGen/PowerPC/frame-size.ll new file mode 100644 index 0000000000..0e569a4602 --- /dev/null +++ b/test/CodeGen/PowerPC/frame-size.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" + +define i64 @foo() nounwind { +entry: + %x = alloca [32568 x i8] + %"alloca point" = bitcast i32 0 to i32 + %x1 = bitcast [32568 x i8]* %x to i8* + +; Check that the RS spill slot has been allocated (because the estimate +; will fail the small-frame-size check and the function has spills). +; CHECK: @foo +; CHECK: stdu 1, -32768(1) + + %s1 = call i64 @bar(i8* %x1) nounwind + %s2 = call i64 @bar(i8* %x1) nounwind + %s3 = call i64 @bar(i8* %x1) nounwind + %s4 = call i64 @bar(i8* %x1) nounwind + %s5 = call i64 @bar(i8* %x1) nounwind + %s6 = call i64 @bar(i8* %x1) nounwind + %s7 = call i64 @bar(i8* %x1) nounwind + %s8 = call i64 @bar(i8* %x1) nounwind + %r = call i64 @can(i64 %s1, i64 %s2, i64 %s3, i64 %s4, i64 %s5, i64 %s6, i64 %s7, i64 %s8) nounwind + br label %return + +return: + ret i64 %r +} + +declare i64 @bar(i8*) +declare i64 @can(i64, i64, i64, i64, i64, i64, i64, i64) + diff --git a/test/CodeGen/PowerPC/frameaddr.ll b/test/CodeGen/PowerPC/frameaddr.ll new file mode 100644 index 0000000000..eabd4a68aa --- /dev/null +++ b/test/CodeGen/PowerPC/frameaddr.ll @@ -0,0 +1,47 @@ +; RUN: llc < %s -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +declare void @llvm.eh.sjlj.longjmp(i8*) #1 + +define i8* @main() #0 { +entry: + %0 = call i8* @llvm.frameaddress(i32 0) + ret i8* %0 + +; CHECK: @main +; CHECK: mr 3, 1 +} + +define i8* @foo() #3 { ; naked +entry: + %0 = call i8* @llvm.frameaddress(i32 0) + ret i8* %0 + +; CHECK: @foo +; CHECK: mr 3, 1 +} + +define i8* @bar() #0 { +entry: + %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] + %x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1] + call void @use(i8* %x1) nounwind + %0 = call i8* @llvm.frameaddress(i32 0) + ret i8* %0 + +; Note that if we start eliminating non-leaf frame pointers by default, this +; will need to be updated. +; CHECK: @bar +; CHECK: mr 3, 31 +} + +declare void @use(i8*) + +declare i8* @llvm.frameaddress(i32) #2 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { noreturn nounwind } +attributes #2 = { nounwind readnone } +attributes #3 = { nounwind naked "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } + diff --git a/test/CodeGen/PowerPC/i32-to-float.ll b/test/CodeGen/PowerPC/i32-to-float.ll new file mode 100644 index 0000000000..2707d0352d --- /dev/null +++ b/test/CodeGen/PowerPC/i32-to-float.ll @@ -0,0 +1,82 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 | FileCheck -check-prefix=CHECK-PWR6 %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define float @foo(i32 %a) nounwind { +entry: + %x = sitofp i32 %a to float + ret float %x + +; CHECK: @foo +; CHECK: extsw [[REG:[0-9]+]], 3 +; CHECK: std [[REG]], +; CHECK: lfd [[REG2:[0-9]+]], +; CHECK: fcfid [[REG3:[0-9]+]], [[REG2]] +; CHECK: frsp 1, [[REG3]] +; CHECK: blr + +; CHECK-PWR6: @foo +; CHECK-PWR6: stw 3, +; CHECK-PWR6: lfiwax [[REG:[0-9]+]], +; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]] +; CHECK-PWR6: frsp 1, [[REG2]] +; CHECK-PWR6: blr + +; CHECK-A2: @foo +; CHECK-A2: stw 3, +; CHECK-A2: lfiwax [[REG:[0-9]+]], +; CHECK-A2: fcfids 1, [[REG]] +; CHECK-A2: blr +} + +define double @goo(i32 %a) nounwind { +entry: + %x = sitofp i32 %a to double + ret double %x + +; CHECK: @goo +; CHECK: extsw [[REG:[0-9]+]], 3 +; CHECK: std [[REG]], +; CHECK: lfd [[REG2:[0-9]+]], +; CHECK: fcfid 1, [[REG2]] +; CHECK: blr + +; CHECK-PWR6: @goo +; CHECK-PWR6: stw 3, +; CHECK-PWR6: lfiwax [[REG:[0-9]+]], +; CHECK-PWR6: fcfid 1, [[REG]] +; CHECK-PWR6: blr + +; CHECK-A2: @goo +; CHECK-A2: stw 3, +; CHECK-A2: lfiwax [[REG:[0-9]+]], +; CHECK-A2: fcfid 1, [[REG]] +; CHECK-A2: blr +} + +define float @foou(i32 %a) nounwind { +entry: + %x = uitofp i32 %a to float + ret float %x + +; CHECK-A2: @foou +; CHECK-A2: stw 3, +; CHECK-A2: lfiwzx [[REG:[0-9]+]], +; CHECK-A2: fcfidus 1, [[REG]] +; CHECK-A2: blr +} + +define double @goou(i32 %a) nounwind { +entry: + %x = uitofp i32 %a to double + ret double %x + +; CHECK-A2: @goou +; CHECK-A2: stw 3, +; CHECK-A2: lfiwzx [[REG:[0-9]+]], +; CHECK-A2: fcfidu 1, [[REG]] +; CHECK-A2: blr +} + diff --git a/test/CodeGen/PowerPC/i64-to-float.ll b/test/CodeGen/PowerPC/i64-to-float.ll new file mode 100644 index 0000000000..b81d109e7f --- /dev/null +++ b/test/CodeGen/PowerPC/i64-to-float.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define float @foo(i64 %a) nounwind { +entry: + %x = sitofp i64 %a to float + ret float %x + +; CHECK: @foo +; CHECK: std 3, +; CHECK: lfd [[REG:[0-9]+]], +; CHECK: fcfids 1, [[REG]] +; CHECK: blr +} + +define double @goo(i64 %a) nounwind { +entry: + %x = sitofp i64 %a to double + ret double %x + +; CHECK: @goo +; CHECK: std 3, +; CHECK: lfd [[REG:[0-9]+]], +; CHECK: fcfid 1, [[REG]] +; CHECK: blr +} + +define float @foou(i64 %a) nounwind { +entry: + %x = uitofp i64 %a to float + ret float %x + +; CHECK: @foou +; CHECK: std 3, +; CHECK: lfd [[REG:[0-9]+]], +; CHECK: fcfidus 1, [[REG]] +; CHECK: blr +} + +define double @goou(i64 %a) nounwind { +entry: + %x = uitofp i64 %a to double + ret double %x + +; CHECK: @goou +; CHECK: std 3, +; CHECK: lfd [[REG:[0-9]+]], +; CHECK: fcfidu 1, [[REG]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/i64_fp_round.ll b/test/CodeGen/PowerPC/i64_fp_round.ll index 5ae1be8953..d2a3239ab8 100644 --- a/test/CodeGen/PowerPC/i64_fp_round.ll +++ b/test/CodeGen/PowerPC/i64_fp_round.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -22,6 +22,6 @@ entry: ; Also check that with -enable-unsafe-fp-math we do not get that extra ; code sequence. Simply verify that there is no "isel" present. -; RUN: llc -mcpu=pwr7 -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=UNSAFE +; RUN: llc -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=UNSAFE ; CHECK-UNSAFE-NOT: isel diff --git a/test/CodeGen/PowerPC/Stats/iabs.ll b/test/CodeGen/PowerPC/iabs.ll index 7d089bbd65..f683238de2 100644 --- a/test/CodeGen/PowerPC/Stats/iabs.ll +++ b/test/CodeGen/PowerPC/iabs.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=ppc32 -stats 2>&1 | \ ; RUN: grep "4 .*Number of machine instrs printed" diff --git a/test/CodeGen/PowerPC/jaggedstructs.ll b/test/CodeGen/PowerPC/jaggedstructs.ll index 62aa7cf929..a10c5ddb36 100644 --- a/test/CodeGen/PowerPC/jaggedstructs.ll +++ b/test/CodeGen/PowerPC/jaggedstructs.ll @@ -23,22 +23,22 @@ entry: ; CHECK: std 4, 200(1) ; CHECK: std 3, 192(1) ; CHECK: lbz {{[0-9]+}}, 199(1) -; CHECK: stb {{[0-9]+}}, 55(1) ; CHECK: lhz {{[0-9]+}}, 197(1) +; CHECK: stb {{[0-9]+}}, 55(1) ; CHECK: sth {{[0-9]+}}, 53(1) ; CHECK: lbz {{[0-9]+}}, 207(1) -; CHECK: stb {{[0-9]+}}, 63(1) ; CHECK: lwz {{[0-9]+}}, 203(1) +; CHECK: stb {{[0-9]+}}, 63(1) ; CHECK: stw {{[0-9]+}}, 59(1) ; CHECK: lhz {{[0-9]+}}, 214(1) -; CHECK: sth {{[0-9]+}}, 70(1) ; CHECK: lwz {{[0-9]+}}, 210(1) +; CHECK: sth {{[0-9]+}}, 70(1) ; CHECK: stw {{[0-9]+}}, 66(1) ; CHECK: lbz {{[0-9]+}}, 223(1) -; CHECK: stb {{[0-9]+}}, 79(1) ; CHECK: lhz {{[0-9]+}}, 221(1) -; CHECK: sth {{[0-9]+}}, 77(1) ; CHECK: lwz {{[0-9]+}}, 217(1) +; CHECK: stb {{[0-9]+}}, 79(1) +; CHECK: sth {{[0-9]+}}, 77(1) ; CHECK: stw {{[0-9]+}}, 73(1) ; CHECK: ld 6, 72(1) ; CHECK: ld 5, 64(1) diff --git a/test/CodeGen/PowerPC/lbzux.ll b/test/CodeGen/PowerPC/lbzux.ll index 12f1d1f130..98951306fd 100644 --- a/test/CodeGen/PowerPC/lbzux.ll +++ b/test/CodeGen/PowerPC/lbzux.ll @@ -1,6 +1,6 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; RUN: llc < %s | FileCheck %s +; RUN: llc -disable-ppc-unaligned < %s | FileCheck %s define fastcc void @allocateSpace(i1 %cond1, i1 %cond2) nounwind { entry: diff --git a/test/CodeGen/PowerPC/lit.local.cfg b/test/CodeGen/PowerPC/lit.local.cfg index 4019eca0bb..aaa31d93d5 100644 --- a/test/CodeGen/PowerPC/lit.local.cfg +++ b/test/CodeGen/PowerPC/lit.local.cfg @@ -1,4 +1,4 @@ -config.suffixes = ['.ll', '.c', '.cpp'] +config.suffixes = ['.ll', '.c', '.cpp', '.test'] targets = set(config.root.targets_to_build.split()) if not 'PowerPC' in targets: diff --git a/test/CodeGen/PowerPC/negctr.ll b/test/CodeGen/PowerPC/negctr.ll new file mode 100644 index 0000000000..2f6995c65d --- /dev/null +++ b/test/CodeGen/PowerPC/negctr.ll @@ -0,0 +1,83 @@ +; RUN: llc < %s -mcpu=a2 | FileCheck %s +; RUN: llc < %s -mcpu=a2 -disable-lsr | FileCheck -check-prefix=NOLSR %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define void @main() #0 { +entry: + br i1 undef, label %for.end, label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ] + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 0 + br i1 %exitcond, label %for.end, label %for.body + +; FIXME: We currently can't form the 32-bit unsigned trip count necessary here! +; CHECK: @main +; CHECK-NOT: bdnz + +for.end: ; preds = %for.body, %entry + ret void +} + +define void @main1() #0 { +entry: + br i1 undef, label %for.end, label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ] + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 0 + br i1 %exitcond, label %for.end, label %for.body + +; CHECK: @main1 +; CHECK: li [[REG:[0-9]+]], -1 +; CHECK: mtctr [[REG]] +; CHECK: bdnz + +for.end: ; preds = %for.body, %entry + ret void +} + +define void @main2() #0 { +entry: + br i1 undef, label %for.end, label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ] + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, -100000 + br i1 %exitcond, label %for.end, label %for.body + +; CHECK: @main2 +; CHECK: lis [[REG:[0-9]+]], -2 +; CHECK: ori [[REG2:[0-9]+]], [[REG]], 31071 +; CHECK: mtctr [[REG2]] +; CHECK: bdnz + +for.end: ; preds = %for.body, %entry + ret void +} + +define void @main3() #0 { +entry: + br i1 undef, label %for.end, label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 127984, %entry ] + %indvars.iv.next = add i64 %indvars.iv, -16 + %exitcond = icmp eq i64 %indvars.iv.next, -16 + br i1 %exitcond, label %for.end, label %for.body + +; NOLSR: @main3 +; NOLSR: li [[REG:[0-9]+]], 8000 +; NOLSR: mtctr [[REG]] +; NOLSR: bdnz + +for.end: ; preds = %for.body, %entry + ret void +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/popcnt.ll b/test/CodeGen/PowerPC/popcnt.ll new file mode 100644 index 0000000000..b304d72aed --- /dev/null +++ b/test/CodeGen/PowerPC/popcnt.ll @@ -0,0 +1,40 @@ +; RUN: llc -march=ppc64 -mattr=+popcntd < %s | FileCheck %s + +define i8 @cnt8(i8 %x) nounwind readnone { + %cnt = tail call i8 @llvm.ctpop.i8(i8 %x) + ret i8 %cnt +; CHECK: @cnt8 +; CHECK: rlwinm +; CHECK: popcntw +; CHECK: blr +} + +define i16 @cnt16(i16 %x) nounwind readnone { + %cnt = tail call i16 @llvm.ctpop.i16(i16 %x) + ret i16 %cnt +; CHECK: @cnt16 +; CHECK: rlwinm +; CHECK: popcntw +; CHECK: blr +} + +define i32 @cnt32(i32 %x) nounwind readnone { + %cnt = tail call i32 @llvm.ctpop.i32(i32 %x) + ret i32 %cnt +; CHECK: @cnt32 +; CHECK: popcntw +; CHECK: blr +} + +define i64 @cnt64(i64 %x) nounwind readnone { + %cnt = tail call i64 @llvm.ctpop.i64(i64 %x) + ret i64 %cnt +; CHECK: @cnt64 +; CHECK: popcntd +; CHECK: blr +} + +declare i8 @llvm.ctpop.i8(i8) nounwind readnone +declare i16 @llvm.ctpop.i16(i16) nounwind readnone +declare i32 @llvm.ctpop.i32(i32) nounwind readnone +declare i64 @llvm.ctpop.i64(i64) nounwind readnone diff --git a/test/CodeGen/PowerPC/r31.ll b/test/CodeGen/PowerPC/r31.ll new file mode 100644 index 0000000000..7ce12f600b --- /dev/null +++ b/test/CodeGen/PowerPC/r31.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g4 | FileCheck %s +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" + +define i64 @foo(i64 %a) nounwind { +entry: + call void asm sideeffect "", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30}"() nounwind + br label %return + +; CHECK: @foo +; CHECK: mr 31, 3 + +return: ; preds = %entry + ret i64 %a +} + diff --git a/test/CodeGen/PowerPC/Stats/rlwimi3.ll b/test/CodeGen/PowerPC/rlwimi3.ll index 7efdbe9634..31b6d4aa03 100644 --- a/test/CodeGen/PowerPC/Stats/rlwimi3.ll +++ b/test/CodeGen/PowerPC/rlwimi3.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=ppc32 -stats 2>&1 | \ ; RUN: grep "Number of machine instrs printed" | grep 12 diff --git a/test/CodeGen/PowerPC/rounding-ops.ll b/test/CodeGen/PowerPC/rounding-ops.ll new file mode 100644 index 0000000000..b210a6bda8 --- /dev/null +++ b/test/CodeGen/PowerPC/rounding-ops.ll @@ -0,0 +1,145 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math | FileCheck -check-prefix=CHECK-FM %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define float @test1(float %x) nounwind { + %call = tail call float @floorf(float %x) nounwind readnone + ret float %call + +; CHECK: test1: +; CHECK: frim 1, 1 + +; CHECK-FM: test1: +; CHECK-FM: frim 1, 1 +} + +declare float @floorf(float) nounwind readnone + +define double @test2(double %x) nounwind { + %call = tail call double @floor(double %x) nounwind readnone + ret double %call + +; CHECK: test2: +; CHECK: frim 1, 1 + +; CHECK-FM: test2: +; CHECK-FM: frim 1, 1 +} + +declare double @floor(double) nounwind readnone + +define float @test3(float %x) nounwind { + %call = tail call float @nearbyintf(float %x) nounwind readnone + ret float %call + +; CHECK: test3: +; CHECK-NOT: frin + +; CHECK-FM: test3: +; CHECK-FM: frin 1, 1 +} + +declare float @nearbyintf(float) nounwind readnone + +define double @test4(double %x) nounwind { + %call = tail call double @nearbyint(double %x) nounwind readnone + ret double %call + +; CHECK: test4: +; CHECK-NOT: frin + +; CHECK-FM: test4: +; CHECK-FM: frin 1, 1 +} + +declare double @nearbyint(double) nounwind readnone + +define float @test5(float %x) nounwind { + %call = tail call float @ceilf(float %x) nounwind readnone + ret float %call + +; CHECK: test5: +; CHECK: frip 1, 1 + +; CHECK-FM: test5: +; CHECK-FM: frip 1, 1 +} + +declare float @ceilf(float) nounwind readnone + +define double @test6(double %x) nounwind { + %call = tail call double @ceil(double %x) nounwind readnone + ret double %call + +; CHECK: test6: +; CHECK: frip 1, 1 + +; CHECK-FM: test6: +; CHECK-FM: frip 1, 1 +} + +declare double @ceil(double) nounwind readnone + +define float @test9(float %x) nounwind { + %call = tail call float @truncf(float %x) nounwind readnone + ret float %call + +; CHECK: test9: +; CHECK: friz 1, 1 + +; CHECK-FM: test9: +; CHECK-FM: friz 1, 1 +} + +declare float @truncf(float) nounwind readnone + +define double @test10(double %x) nounwind { + %call = tail call double @trunc(double %x) nounwind readnone + ret double %call + +; CHECK: test10: +; CHECK: friz 1, 1 + +; CHECK-FM: test10: +; CHECK-FM: friz 1, 1 +} + +declare double @trunc(double) nounwind readnone + +define float @test11(float %x) nounwind { + %call = tail call float @rintf(float %x) nounwind readnone + ret float %call + +; CHECK: test11: +; CHECK-NOT: frin + +; CHECK-FM: test11: +; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]] +; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]] +; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2 +; CHECK-FM: mtfsb1 6 +; CHECK-FM: .LBB[[BB]]_2: +; CHECK-FM: blr +} + +declare float @rintf(float) nounwind readnone + +define double @test12(double %x) nounwind { + %call = tail call double @rint(double %x) nounwind readnone + ret double %call + +; CHECK: test12: +; CHECK-NOT: frin + +; CHECK-FM: test12: +; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]] +; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]] +; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2 +; CHECK-FM: mtfsb1 6 +; CHECK-FM: .LBB[[BB]]_2: +; CHECK-FM: blr +} + +declare double @rint(double) nounwind readnone + diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll new file mode 100644 index 0000000000..7ea35dafc3 --- /dev/null +++ b/test/CodeGen/PowerPC/sjlj.ll @@ -0,0 +1,112 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-NOAV %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.__jmp_buf_tag = type { [64 x i64], i32, %struct.__sigset_t, [8 x i8] } +%struct.__sigset_t = type { [16 x i64] } + +@env_sigill = internal global [1 x %struct.__jmp_buf_tag] zeroinitializer, align 16 + +define void @foo() #0 { +entry: + call void @llvm.eh.sjlj.longjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8*)) + unreachable + +; CHECK: @foo +; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha +; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l +; CHECK: ld 31, 0([[REG]]) +; CHECK: ld [[REG2:[0-9]+]], 8([[REG]]) +; CHECK: ld 1, 16([[REG]]) +; CHECK: mtctr [[REG2]] +; CHECK: ld 2, 24([[REG]]) +; CHECK: bctr + +return: ; No predecessors! + ret void +} + +declare void @llvm.eh.sjlj.longjmp(i8*) #1 + +define signext i32 @main() #0 { +entry: + %retval = alloca i32, align 4 + store i32 0, i32* %retval + %0 = call i8* @llvm.frameaddress(i32 0) + store i8* %0, i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**) + %1 = call i8* @llvm.stacksave() + store i8* %1, i8** getelementptr (i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**), i32 2) + %2 = call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8*)) + %tobool = icmp ne i32 %2, 0 + br i1 %tobool, label %if.then, label %if.else + +if.then: ; preds = %entry + store i32 1, i32* %retval + br label %return + +if.else: ; preds = %entry + call void @foo() + br label %if.end + +if.end: ; preds = %if.else + store i32 0, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %3 = load i32* %retval + ret i32 %3 + +; FIXME: We should be saving VRSAVE on Darwin, but we're not! + +; CHECK: @main +; CHECK: std +; Make sure that we're not saving VRSAVE on non-Darwin: +; CHECK-NOT: mfspr +; CHECK: stfd +; CHECK: stvx + +; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha +; CHECK: std 31, env_sigill@toc@l([[REG]]) +; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l +; CHECK: std [[REG]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill +; CHECK: std 1, 16([[REG]]) +; CHECK: std 2, 24([[REG]]) +; CHECK: bcl 20, 31, .LBB1_1 +; CHECK: li 3, 1 +; CHECK: #EH_SjLj_Setup .LBB1_1 +; CHECK: b .LBB1_2 + +; CHECK: .LBB1_1: +; CHECK: mflr [[REGL:[0-9]+]] +; CHECK: ld [[REG2:[0-9]+]], [[OFF]](31) # 8-byte Folded Reload +; CHECK: std [[REGL]], 8([[REG2]]) +; CHECK: li 3, 0 + +; CHECK: .LBB1_2: + +; CHECK: lfd +; CHECK: lvx +; CHECK: ld +; CHECK: blr + +; CHECK-NOAV: @main +; CHECK-NOAV-NOT: stvx +; CHECK-NOAV: bcl +; CHECK-NOAV: mflr +; CHECK-NOAV: bl foo +; CHECK-NOAV-NOT: lvx +; CHECK-NOAV: blr +} + +declare i8* @llvm.frameaddress(i32) #2 + +declare i8* @llvm.stacksave() #3 + +declare i32 @llvm.eh.sjlj.setjmp(i8*) #3 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { noreturn nounwind } +attributes #2 = { nounwind readnone } +attributes #3 = { nounwind } + diff --git a/test/CodeGen/PowerPC/stfiwx-2.ll b/test/CodeGen/PowerPC/stfiwx-2.ll index c49b25cc23..7786fc17ea 100644 --- a/test/CodeGen/PowerPC/stfiwx-2.ll +++ b/test/CodeGen/PowerPC/stfiwx-2.ll @@ -1,11 +1,14 @@ -; This cannot be a stfiwx -; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep stb -; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep stfiwx +; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 | FileCheck %s define void @test(float %F, i8* %P) { %I = fptosi float %F to i32 %X = trunc i32 %I to i8 store i8 %X, i8* %P ret void +; CHECK: fctiwz 0, 1 +; CHECK: stfiwx 0, 0, 4 +; CHECK: lwz 4, 12(1) +; CHECK: stb 4, 0(3) +; CHECK: blr } diff --git a/test/CodeGen/PowerPC/store-update.ll b/test/CodeGen/PowerPC/store-update.ll new file mode 100644 index 0000000000..538ed24fbc --- /dev/null +++ b/test/CodeGen/PowerPC/store-update.ll @@ -0,0 +1,170 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i8* @stbu(i8* %base, i8 zeroext %val) nounwind { +entry: + %arrayidx = getelementptr inbounds i8* %base, i64 16 + store i8 %val, i8* %arrayidx, align 1 + ret i8* %arrayidx +} +; CHECK: @stbu +; CHECK: %entry +; CHECK-NEXT: stbu +; CHECK-NEXT: blr + +define i8* @stbux(i8* %base, i8 zeroext %val, i64 %offset) nounwind { +entry: + %arrayidx = getelementptr inbounds i8* %base, i64 %offset + store i8 %val, i8* %arrayidx, align 1 + ret i8* %arrayidx +} +; CHECK: @stbux +; CHECK: %entry +; CHECK-NEXT: stbux +; CHECK-NEXT: blr + +define i16* @sthu(i16* %base, i16 zeroext %val) nounwind { +entry: + %arrayidx = getelementptr inbounds i16* %base, i64 16 + store i16 %val, i16* %arrayidx, align 2 + ret i16* %arrayidx +} +; CHECK: @sthu +; CHECK: %entry +; CHECK-NEXT: sthu +; CHECK-NEXT: blr + +define i16* @sthux(i16* %base, i16 zeroext %val, i64 %offset) nounwind { +entry: + %arrayidx = getelementptr inbounds i16* %base, i64 %offset + store i16 %val, i16* %arrayidx, align 2 + ret i16* %arrayidx +} +; CHECK: @sthux +; CHECK: %entry +; CHECK-NEXT: sldi +; CHECK-NEXT: sthux +; CHECK-NEXT: blr + +define i32* @stwu(i32* %base, i32 zeroext %val) nounwind { +entry: + %arrayidx = getelementptr inbounds i32* %base, i64 16 + store i32 %val, i32* %arrayidx, align 4 + ret i32* %arrayidx +} +; CHECK: @stwu +; CHECK: %entry +; CHECK-NEXT: stwu +; CHECK-NEXT: blr + +define i32* @stwux(i32* %base, i32 zeroext %val, i64 %offset) nounwind { +entry: + %arrayidx = getelementptr inbounds i32* %base, i64 %offset + store i32 %val, i32* %arrayidx, align 4 + ret i32* %arrayidx +} +; CHECK: @stwux +; CHECK: %entry +; CHECK-NEXT: sldi +; CHECK-NEXT: stwux +; CHECK-NEXT: blr + +define i8* @stbu8(i8* %base, i64 %val) nounwind { +entry: + %conv = trunc i64 %val to i8 + %arrayidx = getelementptr inbounds i8* %base, i64 16 + store i8 %conv, i8* %arrayidx, align 1 + ret i8* %arrayidx +} +; CHECK: @stbu +; CHECK: %entry +; CHECK-NEXT: stbu +; CHECK-NEXT: blr + +define i8* @stbux8(i8* %base, i64 %val, i64 %offset) nounwind { +entry: + %conv = trunc i64 %val to i8 + %arrayidx = getelementptr inbounds i8* %base, i64 %offset + store i8 %conv, i8* %arrayidx, align 1 + ret i8* %arrayidx +} +; CHECK: @stbux +; CHECK: %entry +; CHECK-NEXT: stbux +; CHECK-NEXT: blr + +define i16* @sthu8(i16* %base, i64 %val) nounwind { +entry: + %conv = trunc i64 %val to i16 + %arrayidx = getelementptr inbounds i16* %base, i64 16 + store i16 %conv, i16* %arrayidx, align 2 + ret i16* %arrayidx +} +; CHECK: @sthu +; CHECK: %entry +; CHECK-NEXT: sthu +; CHECK-NEXT: blr + +define i16* @sthux8(i16* %base, i64 %val, i64 %offset) nounwind { +entry: + %conv = trunc i64 %val to i16 + %arrayidx = getelementptr inbounds i16* %base, i64 %offset + store i16 %conv, i16* %arrayidx, align 2 + ret i16* %arrayidx +} +; CHECK: @sthux +; CHECK: %entry +; CHECK-NEXT: sldi +; CHECK-NEXT: sthux +; CHECK-NEXT: blr + +define i32* @stwu8(i32* %base, i64 %val) nounwind { +entry: + %conv = trunc i64 %val to i32 + %arrayidx = getelementptr inbounds i32* %base, i64 16 + store i32 %conv, i32* %arrayidx, align 4 + ret i32* %arrayidx +} +; CHECK: @stwu +; CHECK: %entry +; CHECK-NEXT: stwu +; CHECK-NEXT: blr + +define i32* @stwux8(i32* %base, i64 %val, i64 %offset) nounwind { +entry: + %conv = trunc i64 %val to i32 + %arrayidx = getelementptr inbounds i32* %base, i64 %offset + store i32 %conv, i32* %arrayidx, align 4 + ret i32* %arrayidx +} +; CHECK: @stwux +; CHECK: %entry +; CHECK-NEXT: sldi +; CHECK-NEXT: stwux +; CHECK-NEXT: blr + +define i64* @stdu(i64* %base, i64 %val) nounwind { +entry: + %arrayidx = getelementptr inbounds i64* %base, i64 16 + store i64 %val, i64* %arrayidx, align 8 + ret i64* %arrayidx +} +; CHECK: @stdu +; CHECK: %entry +; CHECK-NEXT: stdu +; CHECK-NEXT: blr + +define i64* @stdux(i64* %base, i64 %val, i64 %offset) nounwind { +entry: + %arrayidx = getelementptr inbounds i64* %base, i64 %offset + store i64 %val, i64* %arrayidx, align 8 + ret i64* %arrayidx +} +; CHECK: @stdux +; CHECK: %entry +; CHECK-NEXT: sldi +; CHECK-NEXT: stdux +; CHECK-NEXT: blr + diff --git a/test/CodeGen/PowerPC/structsinmem.ll b/test/CodeGen/PowerPC/structsinmem.ll index 884d3a89d1..2a17e740ea 100644 --- a/test/CodeGen/PowerPC/structsinmem.ll +++ b/test/CodeGen/PowerPC/structsinmem.ll @@ -1,9 +1,5 @@ ; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s -; FIXME: The code generation for packed structs is very poor because the -; PowerPC target wrongly rejects all unaligned loads. This test case will -; need to be revised when that is fixed. - target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -118,8 +114,8 @@ entry: ret i32 %add13 ; CHECK: lha {{[0-9]+}}, 126(1) -; CHECK: lbz {{[0-9]+}}, 119(1) ; CHECK: lha {{[0-9]+}}, 132(1) +; CHECK: lbz {{[0-9]+}}, 119(1) ; CHECK: lwz {{[0-9]+}}, 140(1) ; CHECK: lwz {{[0-9]+}}, 144(1) ; CHECK: lwz {{[0-9]+}}, 152(1) @@ -209,19 +205,11 @@ entry: %add13 = add nsw i32 %add11, %6 ret i32 %add13 -; CHECK: lbz {{[0-9]+}}, 149(1) -; CHECK: lbz {{[0-9]+}}, 150(1) -; CHECK: lbz {{[0-9]+}}, 147(1) -; CHECK: lbz {{[0-9]+}}, 148(1) -; CHECK: lbz {{[0-9]+}}, 133(1) -; CHECK: lbz {{[0-9]+}}, 134(1) ; CHECK: lha {{[0-9]+}}, 126(1) +; CHECK: lha {{[0-9]+}}, 133(1) ; CHECK: lbz {{[0-9]+}}, 119(1) ; CHECK: lwz {{[0-9]+}}, 140(1) -; CHECK: lhz {{[0-9]+}}, 154(1) -; CHECK: lhz {{[0-9]+}}, 156(1) -; CHECK: lbz {{[0-9]+}}, 163(1) -; CHECK: lbz {{[0-9]+}}, 164(1) -; CHECK: lbz {{[0-9]+}}, 161(1) -; CHECK: lbz {{[0-9]+}}, 162(1) +; CHECK: lwz {{[0-9]+}}, 147(1) +; CHECK: lwz {{[0-9]+}}, 154(1) +; CHECK: lwz {{[0-9]+}}, 161(1) } diff --git a/test/CodeGen/PowerPC/structsinregs.ll b/test/CodeGen/PowerPC/structsinregs.ll index ef706af95d..54de6060d0 100644 --- a/test/CodeGen/PowerPC/structsinregs.ll +++ b/test/CodeGen/PowerPC/structsinregs.ll @@ -1,9 +1,5 @@ ; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s -; FIXME: The code generation for packed structs is very poor because the -; PowerPC target wrongly rejects all unaligned loads. This test case will -; need to be revised when that is fixed. - target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -63,13 +59,13 @@ entry: %call = call i32 @callee1(%struct.s1* byval %p1, %struct.s2* byval %p2, %struct.s3* byval %p3, %struct.s4* byval %p4, %struct.s5* byval %p5, %struct.s6* byval %p6, %struct.s7* byval %p7) ret i32 %call -; CHECK: ld 9, 128(31) -; CHECK: ld 8, 136(31) -; CHECK: ld 7, 144(31) -; CHECK: lwz 6, 152(31) -; CHECK: lwz 5, 160(31) -; CHECK: lhz 4, 168(31) -; CHECK: lbz 3, 176(31) +; CHECK: ld 9, 112(31) +; CHECK: ld 8, 120(31) +; CHECK: ld 7, 128(31) +; CHECK: lwz 6, 136(31) +; CHECK: lwz 5, 144(31) +; CHECK: lhz 4, 152(31) +; CHECK: lbz 3, 160(31) } declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind @@ -109,8 +105,8 @@ entry: ; CHECK: sth 4, 62(1) ; CHECK: stb 3, 55(1) ; CHECK: lha {{[0-9]+}}, 62(1) -; CHECK: lbz {{[0-9]+}}, 55(1) ; CHECK: lha {{[0-9]+}}, 68(1) +; CHECK: lbz {{[0-9]+}}, 55(1) ; CHECK: lwz {{[0-9]+}}, 76(1) ; CHECK: lwz {{[0-9]+}}, 80(1) ; CHECK: lwz {{[0-9]+}}, 88(1) @@ -155,10 +151,10 @@ entry: ; CHECK: ld 9, 96(1) ; CHECK: ld 8, 88(1) ; CHECK: ld 7, 80(1) -; CHECK: lwz 6, 152(31) +; CHECK: lwz 6, 136(31) ; CHECK: ld 5, 64(1) -; CHECK: lhz 4, 168(31) -; CHECK: lbz 3, 176(31) +; CHECK: lhz 4, 152(31) +; CHECK: lbz 3, 160(31) } define internal i32 @callee2(%struct.t1* byval %v1, %struct.t2* byval %v2, %struct.t3* byval %v3, %struct.t4* byval %v4, %struct.t5* byval %v5, %struct.t6* byval %v6, %struct.t7* byval %v7) nounwind { @@ -195,19 +191,11 @@ entry: ; CHECK: std 5, 64(1) ; CHECK: sth 4, 62(1) ; CHECK: stb 3, 55(1) -; CHECK: lbz {{[0-9]+}}, 85(1) -; CHECK: lbz {{[0-9]+}}, 86(1) -; CHECK: lbz {{[0-9]+}}, 83(1) -; CHECK: lbz {{[0-9]+}}, 84(1) -; CHECK: lbz {{[0-9]+}}, 69(1) -; CHECK: lbz {{[0-9]+}}, 70(1) ; CHECK: lha {{[0-9]+}}, 62(1) +; CHECK: lha {{[0-9]+}}, 69(1) ; CHECK: lbz {{[0-9]+}}, 55(1) ; CHECK: lwz {{[0-9]+}}, 76(1) -; CHECK: lhz {{[0-9]+}}, 90(1) -; CHECK: lhz {{[0-9]+}}, 92(1) -; CHECK: lbz {{[0-9]+}}, 99(1) -; CHECK: lbz {{[0-9]+}}, 100(1) -; CHECK: lbz {{[0-9]+}}, 97(1) -; CHECK: lbz {{[0-9]+}}, 98(1) +; CHECK: lwz {{[0-9]+}}, 83(1) +; CHECK: lwz {{[0-9]+}}, 90(1) +; CHECK: lwz {{[0-9]+}}, 97(1) } diff --git a/test/CodeGen/PowerPC/stwu8.ll b/test/CodeGen/PowerPC/stwu8.ll index 897bfc6d6c..e0bd043454 100644 --- a/test/CodeGen/PowerPC/stwu8.ll +++ b/test/CodeGen/PowerPC/stwu8.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -disable-ppc-unaligned < %s | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/tls-gd.ll b/test/CodeGen/PowerPC/tls-gd.ll index fb8dfaf04a..5f0ef9a050 100644 --- a/test/CodeGen/PowerPC/tls-gd.ll +++ b/test/CodeGen/PowerPC/tls-gd.ll @@ -18,6 +18,6 @@ entry: ; CHECK: addis [[REG:[0-9]+]], 2, a@got@tlsgd@ha ; CHECK-NEXT: addi 3, [[REG]], a@got@tlsgd@l -; CHECK-NEXT: bl __tls_get_addr(a@tlsgd) +; CHECK: bl __tls_get_addr(a@tlsgd) ; CHECK-NEXT: nop diff --git a/test/CodeGen/PowerPC/tls-ld-2.ll b/test/CodeGen/PowerPC/tls-ld-2.ll index 4954afeb24..4399b330ea 100644 --- a/test/CodeGen/PowerPC/tls-ld-2.ll +++ b/test/CodeGen/PowerPC/tls-ld-2.ll @@ -18,7 +18,7 @@ entry: ; CHECK: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha ; CHECK-NEXT: addi 3, [[REG]], a@got@tlsld@l -; CHECK-NEXT: bl __tls_get_addr(a@tlsld) +; CHECK: bl __tls_get_addr(a@tlsld) ; CHECK-NEXT: nop -; CHECK-NEXT: addis [[REG2:[0-9]+]], 3, a@dtprel@ha +; CHECK: addis [[REG2:[0-9]+]], 3, a@dtprel@ha ; CHECK-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]]) diff --git a/test/CodeGen/PowerPC/tls-ld.ll b/test/CodeGen/PowerPC/tls-ld.ll index 1ebc6129e2..db02a56f6a 100644 --- a/test/CodeGen/PowerPC/tls-ld.ll +++ b/test/CodeGen/PowerPC/tls-ld.ll @@ -18,7 +18,7 @@ entry: ; CHECK: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha ; CHECK-NEXT: addi 3, [[REG]], a@got@tlsld@l -; CHECK-NEXT: bl __tls_get_addr(a@tlsld) +; CHECK: bl __tls_get_addr(a@tlsld) ; CHECK-NEXT: nop -; CHECK-NEXT: addis [[REG2:[0-9]+]], 3, a@dtprel@ha +; CHECK: addis [[REG2:[0-9]+]], 3, a@dtprel@ha ; CHECK-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l diff --git a/test/CodeGen/PowerPC/tls.ll b/test/CodeGen/PowerPC/tls.ll index 151b4b7dda..2daa60ab37 100644 --- a/test/CodeGen/PowerPC/tls.ll +++ b/test/CodeGen/PowerPC/tls.ll @@ -12,7 +12,7 @@ entry: ;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha ;OPT0-NEXT: li [[REG2:[0-9]+]], 42 ;OPT0-NEXT: addi [[REG1]], [[REG1]], a@tprel@l -;OPT0-NEXT: stw [[REG2]], 0([[REG1]]) +;OPT0: stw [[REG2]], 0([[REG1]]) ;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha ;OPT1-NEXT: li [[REG2:[0-9]+]], 42 ;OPT1-NEXT: stw [[REG2]], a@tprel@l([[REG1]]) diff --git a/test/CodeGen/PowerPC/unal4-std.ll b/test/CodeGen/PowerPC/unal4-std.ll new file mode 100644 index 0000000000..169bd787c0 --- /dev/null +++ b/test/CodeGen/PowerPC/unal4-std.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define fastcc void @copy_to_conceal() #0 { +entry: + br i1 undef, label %if.then, label %if.end210 + +if.then: ; preds = %entry + br label %vector.body.i + +vector.body.i: ; preds = %vector.body.i, %if.then + %index.i = phi i64 [ 0, %vector.body.i ], [ 0, %if.then ] + store <8 x i16> zeroinitializer, <8 x i16>* undef, align 2 + br label %vector.body.i + +if.end210: ; preds = %entry + ret void + +; This will generate two align-1 i64 stores. Make sure that they are +; indexed stores and not in r+i form (which require the offset to be +; a multiple of 4). +; CHECK: @copy_to_conceal +; CHECK: stdx {{[0-9]+}}, 0, +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/PowerPC/unaligned.ll b/test/CodeGen/PowerPC/unaligned.ll new file mode 100644 index 0000000000..d05080338f --- /dev/null +++ b/test/CodeGen/PowerPC/unaligned.ll @@ -0,0 +1,73 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" + +define void @foo1(i16* %p, i16* %r) nounwind { +entry: + %v = load i16* %p, align 1 + store i16 %v, i16* %r, align 1 + ret void + +; CHECK: @foo1 +; CHECK: lhz +; CHECK: sth +} + +define void @foo2(i32* %p, i32* %r) nounwind { +entry: + %v = load i32* %p, align 1 + store i32 %v, i32* %r, align 1 + ret void + +; CHECK: @foo2 +; CHECK: lwz +; CHECK: stw +} + +define void @foo3(i64* %p, i64* %r) nounwind { +entry: + %v = load i64* %p, align 1 + store i64 %v, i64* %r, align 1 + ret void + +; CHECK: @foo3 +; CHECK: ld +; CHECK: std +} + +define void @foo4(float* %p, float* %r) nounwind { +entry: + %v = load float* %p, align 1 + store float %v, float* %r, align 1 + ret void + +; CHECK: @foo4 +; CHECK: lfs +; CHECK: stfs +} + +define void @foo5(double* %p, double* %r) nounwind { +entry: + %v = load double* %p, align 1 + store double %v, double* %r, align 1 + ret void + +; CHECK: @foo5 +; CHECK: lfd +; CHECK: stfd +} + +define void @foo6(<4 x float>* %p, <4 x float>* %r) nounwind { +entry: + %v = load <4 x float>* %p, align 1 + store <4 x float> %v, <4 x float>* %r, align 1 + ret void + +; These loads and stores are legalized into aligned loads and stores +; using aligned stack slots. +; CHECK: @foo6 +; CHECK: ld +; CHECK: ld +; CHECK: std +; CHECK: std +} + diff --git a/test/CodeGen/PowerPC/varargs.ll b/test/CodeGen/PowerPC/varargs.ll index 1769be957a..90f0480d6a 100644 --- a/test/CodeGen/PowerPC/varargs.ll +++ b/test/CodeGen/PowerPC/varargs.ll @@ -8,15 +8,16 @@ define i8* @test1(i8** %foo) nounwind { } ; P32: test1: -; P32: lwz r4, 0(r3) -; P32: addi r5, r4, 4 -; P32: stw r5, 0(r3) -; P32: lwz r3, 0(r4) -; P32: blr +; P32: lwz r2, 0(r3) +; P32: addi r4, r2, 4 +; P32: stw r4, 0(r3) +; P32: lwz r3, 0(r2) +; P32: blr ; P64: test1: -; P64: ld r4, 0(r3) -; P64: addi r5, r4, 8 -; P64: std r5, 0(r3) -; P64: ld r3, 0(r4) -; P64: blr +; P64: ld r2, 0(r3) +; P64: addi r4, r2, 8 +; P64: std r4, 0(r3) +; P64: ld r3, 0(r2) +; P64: blr + diff --git a/test/CodeGen/PowerPC/vec_rounding.ll b/test/CodeGen/PowerPC/vec_rounding.ll index f41faa0339..7c55638620 100644 --- a/test/CodeGen/PowerPC/vec_rounding.ll +++ b/test/CodeGen/PowerPC/vec_rounding.ll @@ -13,8 +13,8 @@ define <2 x double> @floor_v2f64(<2 x double> %p) ret <2 x double> %t } ; CHECK: floor_v2f64: -; CHECK: bl floor -; CHECK: bl floor +; CHECK: frim +; CHECK: frim declare <4 x double> @llvm.floor.v4f64(<4 x double> %p) define <4 x double> @floor_v4f64(<4 x double> %p) @@ -23,10 +23,10 @@ define <4 x double> @floor_v4f64(<4 x double> %p) ret <4 x double> %t } ; CHECK: floor_v4f64: -; CHECK: bl floor -; CHECK: bl floor -; CHECK: bl floor -; CHECK: bl floor +; CHECK: frim +; CHECK: frim +; CHECK: frim +; CHECK: frim declare <2 x double> @llvm.ceil.v2f64(<2 x double> %p) define <2 x double> @ceil_v2f64(<2 x double> %p) @@ -35,8 +35,8 @@ define <2 x double> @ceil_v2f64(<2 x double> %p) ret <2 x double> %t } ; CHECK: ceil_v2f64: -; CHECK: bl ceil -; CHECK: bl ceil +; CHECK: frip +; CHECK: frip declare <4 x double> @llvm.ceil.v4f64(<4 x double> %p) define <4 x double> @ceil_v4f64(<4 x double> %p) @@ -45,10 +45,10 @@ define <4 x double> @ceil_v4f64(<4 x double> %p) ret <4 x double> %t } ; CHECK: ceil_v4f64: -; CHECK: bl ceil -; CHECK: bl ceil -; CHECK: bl ceil -; CHECK: bl ceil +; CHECK: frip +; CHECK: frip +; CHECK: frip +; CHECK: frip declare <2 x double> @llvm.trunc.v2f64(<2 x double> %p) define <2 x double> @trunc_v2f64(<2 x double> %p) @@ -57,8 +57,8 @@ define <2 x double> @trunc_v2f64(<2 x double> %p) ret <2 x double> %t } ; CHECK: trunc_v2f64: -; CHECK: bl trunc -; CHECK: bl trunc +; CHECK: friz +; CHECK: friz declare <4 x double> @llvm.trunc.v4f64(<4 x double> %p) define <4 x double> @trunc_v4f64(<4 x double> %p) @@ -67,10 +67,10 @@ define <4 x double> @trunc_v4f64(<4 x double> %p) ret <4 x double> %t } ; CHECK: trunc_v4f64: -; CHECK: bl trunc -; CHECK: bl trunc -; CHECK: bl trunc -; CHECK: bl trunc +; CHECK: friz +; CHECK: friz +; CHECK: friz +; CHECK: friz declare <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p) define <2 x double> @nearbyint_v2f64(<2 x double> %p) diff --git a/test/CodeGen/PowerPC/vrsave-spill.ll b/test/CodeGen/PowerPC/vrsave-spill.ll new file mode 100644 index 0000000000..c73206d8fc --- /dev/null +++ b/test/CodeGen/PowerPC/vrsave-spill.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -mtriple=powerpc64-apple-darwin -mcpu=g5 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-apple-darwin" + +define <4 x float> @foo(<4 x float> %a, <4 x float> %b) nounwind { +entry: + %c = fadd <4 x float> %a, %b + %d = fmul <4 x float> %c, %a + call void asm sideeffect "", "~{VRsave}"() nounwind + br label %return + +; CHECK: @foo +; CHECK: mfspr r{{[0-9]+}}, 256 +; CHECK: mtspr 256, r{{[0-9]+}} + +return: ; preds = %entry + ret <4 x float> %d +} + diff --git a/test/CodeGen/PowerPC/vrspill.ll b/test/CodeGen/PowerPC/vrspill.ll index 7641017c43..9fb3d03477 100644 --- a/test/CodeGen/PowerPC/vrspill.ll +++ b/test/CodeGen/PowerPC/vrspill.ll @@ -13,7 +13,7 @@ entry: ret void } -; CHECK: stvx 2, 0, 0 -; CHECK: lvx 2, 0, 0 +; CHECK: stvx 2, 1, +; CHECK: lvx 2, 1, declare void @foo(i32*) diff --git a/test/CodeGen/R600/disconnected-predset-break-bug.ll b/test/CodeGen/R600/disconnected-predset-break-bug.ll index a58674269a..09baee7a1d 100644 --- a/test/CodeGen/R600/disconnected-predset-break-bug.ll +++ b/test/CodeGen/R600/disconnected-predset-break-bug.ll @@ -5,9 +5,10 @@ ; and the PREDICATE_BREAK in this loop. ; CHECK: @loop_ge -; CHECK: WHILE +; CHECK: LOOP_START_DX10 ; CHECK: PRED_SET -; CHECK-NEXT: PREDICATED_BREAK +; CHECK-NEXT: JUMP +; CHECK-NEXT: LOOP_BREAK define void @loop_ge(i32 addrspace(1)* nocapture %out, i32 %iterations) nounwind { entry: %cmp5 = icmp sgt i32 %iterations, 0 diff --git a/test/CodeGen/R600/kcache-fold.ll b/test/CodeGen/R600/kcache-fold.ll index 82fb925c0d..3d70e4bd54 100644 --- a/test/CodeGen/R600/kcache-fold.ll +++ b/test/CodeGen/R600/kcache-fold.ll @@ -1,8 +1,8 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -; CHECK: MOV T{{[0-9]+\.[XYZW], CBuf0\[[0-9]+\]\.[XYZW]}} - -define void @main() { +; CHECK: @main1 +; CHECK: MOV T{{[0-9]+\.[XYZW], KC0}} +define void @main1() { main_body: %0 = load <4 x float> addrspace(8)* null %1 = extractelement <4 x float> %0, i32 0 @@ -48,5 +48,53 @@ main_body: ret void } +; CHECK: @main2 +; CHECK-NOT: MOV +define void @main2() { +main_body: + %0 = load <4 x float> addrspace(8)* null + %1 = extractelement <4 x float> %0, i32 0 + %2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %3 = extractelement <4 x float> %2, i32 0 + %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %5 = extractelement <4 x float> %4, i32 1 + %6 = fcmp ult float %1, 0.000000e+00 + %7 = select i1 %6, float %3, float %5 + %8 = load <4 x float> addrspace(8)* null + %9 = extractelement <4 x float> %8, i32 1 + %10 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %11 = extractelement <4 x float> %10, i32 0 + %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %13 = extractelement <4 x float> %12, i32 1 + %14 = fcmp ult float %9, 0.000000e+00 + %15 = select i1 %14, float %11, float %13 + %16 = load <4 x float> addrspace(8)* null + %17 = extractelement <4 x float> %16, i32 2 + %18 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %19 = extractelement <4 x float> %18, i32 3 + %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %21 = extractelement <4 x float> %20, i32 2 + %22 = fcmp ult float %17, 0.000000e+00 + %23 = select i1 %22, float %19, float %21 + %24 = load <4 x float> addrspace(8)* null + %25 = extractelement <4 x float> %24, i32 3 + %26 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %27 = extractelement <4 x float> %26, i32 3 + %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %29 = extractelement <4 x float> %28, i32 2 + %30 = fcmp ult float %25, 0.000000e+00 + %31 = select i1 %30, float %27, float %29 + %32 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00) + %33 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00) + %34 = call float @llvm.AMDIL.clamp.(float %23, float 0.000000e+00, float 1.000000e+00) + %35 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00) + %36 = insertelement <4 x float> undef, float %32, i32 0 + %37 = insertelement <4 x float> %36, float %33, i32 1 + %38 = insertelement <4 x float> %37, float %34, i32 2 + %39 = insertelement <4 x float> %38, float %35, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %39, i32 0, i32 0) + ret void +} + declare float @llvm.AMDIL.clamp.(float, float, float) readnone declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll index a8f604ac6d..bf0cdaa2fa 100644 --- a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll +++ b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll @@ -14,7 +14,7 @@ main_body: declare void @llvm.AMDGPU.shader.type(i32) -declare float @llvm.SI.fs.constant(i32, i32, i32) readonly +declare float @llvm.SI.fs.constant(i32, i32, i32) readnone declare i32 @llvm.SI.packf16(float, float) readnone diff --git a/test/CodeGen/R600/llvm.SI.sample.ll b/test/CodeGen/R600/llvm.SI.sample.ll index d397f3b678..c724395b98 100644 --- a/test/CodeGen/R600/llvm.SI.sample.ll +++ b/test/CodeGen/R600/llvm.SI.sample.ll @@ -1,71 +1,106 @@ ;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s ;CHECK: IMAGE_SAMPLE -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE_C -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE_C -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE_C -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE_C -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE_C -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE_C -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE -;CHECK-NEXT: S_WAITCNT 1904 -;CHECK-NEXT: IMAGE_SAMPLE +;CHECK: IMAGE_SAMPLE +;CHECK: IMAGE_SAMPLE +;CHECK: IMAGE_SAMPLE +;CHECK: IMAGE_SAMPLE +;CHECK: IMAGE_SAMPLE_C +;CHECK: IMAGE_SAMPLE_C +;CHECK: IMAGE_SAMPLE_C +;CHECK: IMAGE_SAMPLE +;CHECK: IMAGE_SAMPLE +;CHECK: IMAGE_SAMPLE_C +;CHECK: IMAGE_SAMPLE_C +;CHECK: IMAGE_SAMPLE_C +;CHECK: IMAGE_SAMPLE +;CHECK: IMAGE_SAMPLE +;CHECK: IMAGE_SAMPLE -define void @test() { - %res1 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, +define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { + %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0 + %v2 = insertelement <4 x i32> undef, i32 %a1, i32 1 + %v3 = insertelement <4 x i32> undef, i32 %a1, i32 2 + %v4 = insertelement <4 x i32> undef, i32 %a1, i32 3 + %v5 = insertelement <4 x i32> undef, i32 %a2, i32 0 + %v6 = insertelement <4 x i32> undef, i32 %a2, i32 1 + %v7 = insertelement <4 x i32> undef, i32 %a2, i32 2 + %v8 = insertelement <4 x i32> undef, i32 %a2, i32 3 + %v9 = insertelement <4 x i32> undef, i32 %a3, i32 0 + %v10 = insertelement <4 x i32> undef, i32 %a3, i32 1 + %v11 = insertelement <4 x i32> undef, i32 %a3, i32 2 + %v12 = insertelement <4 x i32> undef, i32 %a3, i32 3 + %v13 = insertelement <4 x i32> undef, i32 %a4, i32 0 + %v14 = insertelement <4 x i32> undef, i32 %a4, i32 1 + %v15 = insertelement <4 x i32> undef, i32 %a4, i32 2 + %v16 = insertelement <4 x i32> undef, i32 %a4, i32 3 + %res1 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v1, <8 x i32> undef, <4 x i32> undef, i32 1) - %res2 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res2 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v2, <8 x i32> undef, <4 x i32> undef, i32 2) - %res3 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res3 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v3, <8 x i32> undef, <4 x i32> undef, i32 3) - %res4 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res4 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v4, <8 x i32> undef, <4 x i32> undef, i32 4) - %res5 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res5 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v5, <8 x i32> undef, <4 x i32> undef, i32 5) - %res6 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res6 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v6, <8 x i32> undef, <4 x i32> undef, i32 6) - %res7 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res7 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v7, <8 x i32> undef, <4 x i32> undef, i32 7) - %res8 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res8 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v8, <8 x i32> undef, <4 x i32> undef, i32 8) - %res9 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res9 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v9, <8 x i32> undef, <4 x i32> undef, i32 9) - %res10 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res10 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v10, <8 x i32> undef, <4 x i32> undef, i32 10) - %res11 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res11 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v11, <8 x i32> undef, <4 x i32> undef, i32 11) - %res12 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res12 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v12, <8 x i32> undef, <4 x i32> undef, i32 12) - %res13 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res13 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v13, <8 x i32> undef, <4 x i32> undef, i32 13) - %res14 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res14 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v14, <8 x i32> undef, <4 x i32> undef, i32 14) - %res15 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res15 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v15, <8 x i32> undef, <4 x i32> undef, i32 15) - %res16 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef, + %res16 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v16, <8 x i32> undef, <4 x i32> undef, i32 16) + %e1 = extractelement <4 x float> %res1, i32 0 + %e2 = extractelement <4 x float> %res2, i32 0 + %e3 = extractelement <4 x float> %res3, i32 0 + %e4 = extractelement <4 x float> %res4, i32 0 + %e5 = extractelement <4 x float> %res5, i32 0 + %e6 = extractelement <4 x float> %res6, i32 0 + %e7 = extractelement <4 x float> %res7, i32 0 + %e8 = extractelement <4 x float> %res8, i32 0 + %e9 = extractelement <4 x float> %res9, i32 0 + %e10 = extractelement <4 x float> %res10, i32 0 + %e11 = extractelement <4 x float> %res11, i32 0 + %e12 = extractelement <4 x float> %res12, i32 0 + %e13 = extractelement <4 x float> %res13, i32 0 + %e14 = extractelement <4 x float> %res14, i32 0 + %e15 = extractelement <4 x float> %res15, i32 0 + %e16 = extractelement <4 x float> %res16, i32 0 + %s1 = fadd float %e1, %e2 + %s2 = fadd float %s1, %e3 + %s3 = fadd float %s2, %e4 + %s4 = fadd float %s3, %e5 + %s5 = fadd float %s4, %e6 + %s6 = fadd float %s5, %e7 + %s7 = fadd float %s6, %e8 + %s8 = fadd float %s7, %e9 + %s9 = fadd float %s8, %e10 + %s10 = fadd float %s9, %e11 + %s11 = fadd float %s10, %e12 + %s12 = fadd float %s11, %e13 + %s13 = fadd float %s12, %e14 + %s14 = fadd float %s13, %e15 + %s15 = fadd float %s14, %e16 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s15, float %s15, float %s15, float %s15) ret void } -declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) +declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/llvm.pow.ll b/test/CodeGen/R600/llvm.pow.ll index 0ae9172579..b4ce9f429f 100644 --- a/test/CodeGen/R600/llvm.pow.ll +++ b/test/CodeGen/R600/llvm.pow.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;CHECK: LOG_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK-NEXT: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;CHECK-NEXT: EXP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test() { diff --git a/test/CodeGen/R600/lshl.ll b/test/CodeGen/R600/lshl.ll new file mode 100644 index 0000000000..423adb9da9 --- /dev/null +++ b/test/CodeGen/R600/lshl.ll @@ -0,0 +1,14 @@ +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s + +;CHECK: V_LSHLREV_B32_e32 VGPR0, 1, VGPR0 + +define void @test(i32 %p) { + %i = mul i32 %p, 2 + %r = bitcast i32 %i to float + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r) + ret void +} + +declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/lshr.ll b/test/CodeGen/R600/lshr.ll new file mode 100644 index 0000000000..551eac1d76 --- /dev/null +++ b/test/CodeGen/R600/lshr.ll @@ -0,0 +1,14 @@ +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s + +;CHECK: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0 + +define void @test(i32 %p) { + %i = udiv i32 %p, 2 + %r = bitcast i32 %i to float + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r) + ret void +} + +declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/mulhu.ll b/test/CodeGen/R600/mulhu.ll new file mode 100644 index 0000000000..28744e00c3 --- /dev/null +++ b/test/CodeGen/R600/mulhu.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s + +;CHECK: V_MOV_B32_e32 VGPR1, -1431655765 +;CHECK-NEXT: V_MUL_HI_U32 VGPR0, VGPR0, VGPR1, 0, 0, 0, 0, 0 +;CHECK-NEXT: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0 + +define void @test(i32 %p) { + %i = udiv i32 %p, 3 + %r = bitcast i32 %i to float + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r) + ret void +} + +declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/predicates.ll b/test/CodeGen/R600/predicates.ll index 18895a423e..eb8b052b6f 100644 --- a/test/CodeGen/R600/predicates.ll +++ b/test/CodeGen/R600/predicates.ll @@ -45,10 +45,12 @@ ENDIF: } ; CHECK: @nested_if -; CHECK: IF_PREDICATE_SET +; CHECK: ALU_PUSH_BEFORE +; CHECK: PRED_SET{{[EGN][ET]*}}_INT Exec +; CHECK: JUMP ; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred, ; CHECK: LSHL T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel -; CHECK: ENDIF +; CHECK: POP define void @nested_if(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp sgt i32 %in, 0 @@ -70,11 +72,13 @@ ENDIF: } ; CHECK: @nested_if_else -; CHECK: IF_PREDICATE_SET +; CHECK: ALU_PUSH_BEFORE +; CHECK: PRED_SET{{[EGN][ET]*}}_INT Exec +; CHECK: JUMP ; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred, ; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel ; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel -; CHECK: ENDIF +; CHECK: POP define void @nested_if_else(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp sgt i32 %in, 0 diff --git a/test/CodeGen/R600/seto.ll b/test/CodeGen/R600/seto.ll new file mode 100644 index 0000000000..5ab4b87d57 --- /dev/null +++ b/test/CodeGen/R600/seto.ll @@ -0,0 +1,13 @@ +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s + +;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0 + +define void @main(float %p) { +main_body: + %c = fcmp oeq float %p, %p + %r = select i1 %c, float 1.000000e+00, float 0.000000e+00 + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %r, float %r, float %r, float %r) + ret void +} + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/setuo.ll b/test/CodeGen/R600/setuo.ll new file mode 100644 index 0000000000..320835576d --- /dev/null +++ b/test/CodeGen/R600/setuo.ll @@ -0,0 +1,13 @@ +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s + +;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0 + +define void @main(float %p) { +main_body: + %c = fcmp une float %p, %p + %r = select i1 %c, float 1.000000e+00, float 0.000000e+00 + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %r, float %r, float %r, float %r) + ret void +} + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/SPARC/DbgValueOtherTargets.test b/test/CodeGen/SPARC/DbgValueOtherTargets.test index 749a7b5346..a669bf848d 100644 --- a/test/CodeGen/SPARC/DbgValueOtherTargets.test +++ b/test/CodeGen/SPARC/DbgValueOtherTargets.test @@ -1 +1 @@ -; RUN: llc -O0 -march=sparc -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -march=sparc -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/SPARC/lit.local.cfg b/test/CodeGen/SPARC/lit.local.cfg index 786fee9e66..6f30a87979 100644 --- a/test/CodeGen/SPARC/lit.local.cfg +++ b/test/CodeGen/SPARC/lit.local.cfg @@ -1,4 +1,4 @@ -config.suffixes = ['.ll', '.c', '.cpp'] +config.suffixes = ['.ll', '.c', '.cpp', '.test'] targets = set(config.root.targets_to_build.split()) if not 'Sparc' in targets: diff --git a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll index 498c78165e..d6b6495691 100644 --- a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll +++ b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll @@ -47,8 +47,8 @@ declare double @sqrt(double) nounwind readonly declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 46, i32 0, metadata !1, null} -!1 = metadata !{i32 524299, metadata !2, i32 44, i32 0} ; [ DW_TAG_lexical_block ] -!2 = metadata !{i32 524299, metadata !3, i32 44, i32 0} ; [ DW_TAG_lexical_block ] +!1 = metadata !{i32 524299, metadata !4, metadata !2, i32 44, i32 0} ; [ DW_TAG_lexical_block ] +!2 = metadata !{i32 524299, metadata !4, metadata !3, i32 44, i32 0} ; [ DW_TAG_lexical_block ] !3 = metadata !{i32 524334, i32 0, metadata !4, metadata !"getClosestDiagonal3", metadata !"getClosestDiagonal3", metadata !"_Z19getClosestDiagonal3ii", metadata !4, i32 44, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] !4 = metadata !{i32 524329, metadata !"ggEdgeDiscrepancy.cc", metadata !"/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src", metadata !5} ; [ DW_TAG_file_type ] !5 = metadata !{i32 524305, i32 0, i32 4, metadata !"ggEdgeDiscrepancy.cc", metadata !"/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] @@ -140,8 +140,8 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !91 = metadata !{i32 524544, metadata !1, metadata !"vx", metadata !4, i32 46, metadata !13} ; [ DW_TAG_auto_variable ] !92 = metadata !{i32 48, i32 0, metadata !1, null} !93 = metadata !{i32 218, i32 0, metadata !94, metadata !96} -!94 = metadata !{i32 524299, metadata !95, i32 217, i32 0} ; [ DW_TAG_lexical_block ] -!95 = metadata !{i32 524299, metadata !77, i32 217, i32 0} ; [ DW_TAG_lexical_block ] +!94 = metadata !{i32 524299, metadata !4, metadata !95, i32 217, i32 0} ; [ DW_TAG_lexical_block ] +!95 = metadata !{i32 524299, metadata !4, metadata !77, i32 217, i32 0} ; [ DW_TAG_lexical_block ] !96 = metadata !{i32 51, i32 0, metadata !1, null} !97 = metadata !{i32 227, i32 0, metadata !94, metadata !96} !98 = metadata !{i32 52, i32 0, metadata !1, null} diff --git a/test/CodeGen/Thumb/DbgValueOtherTargets.test b/test/CodeGen/Thumb/DbgValueOtherTargets.test index aa31a7c75c..afb18a43be 100644 --- a/test/CodeGen/Thumb/DbgValueOtherTargets.test +++ b/test/CodeGen/Thumb/DbgValueOtherTargets.test @@ -1 +1 @@ -; RUN: llc -O0 -march=thumb -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -march=thumb -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/Thumb/lit.local.cfg b/test/CodeGen/Thumb/lit.local.cfg index cb77b09ef4..4d75f581a1 100644 --- a/test/CodeGen/Thumb/lit.local.cfg +++ b/test/CodeGen/Thumb/lit.local.cfg @@ -1,4 +1,4 @@ -config.suffixes = ['.ll', '.c', '.cpp'] +config.suffixes = ['.ll', '.c', '.cpp', '.test'] targets = set(config.root.targets_to_build.split()) if not 'ARM' in targets: diff --git a/test/CodeGen/X86/Stats/2003-08-03-CallArgLiveRanges.ll b/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll index 0af2445d7f..2e4cb1fe7e 100644 --- a/test/CodeGen/X86/Stats/2003-08-03-CallArgLiveRanges.ll +++ b/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; The old instruction selector used to load all arguments to a call up in ; registers, then start pushing them all onto the stack. This is bad news as ; it makes a ton of annoying overlapping live ranges. This code should not diff --git a/test/CodeGen/X86/Stats/2006-03-02-InstrSchedBug.ll b/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll index 1a3d74918d..7673124d5d 100644 --- a/test/CodeGen/X86/Stats/2006-03-02-InstrSchedBug.ll +++ b/test/CodeGen/X86/2006-03-02-InstrSchedBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -stats 2>&1 | \ ; RUN: grep asm-printer | grep 7 diff --git a/test/CodeGen/X86/Stats/2006-05-01-SchedCausingSpills.ll b/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll index 5cba3efeef..faa3e21a93 100644 --- a/test/CodeGen/X86/Stats/2006-05-01-SchedCausingSpills.ll +++ b/test/CodeGen/X86/2006-05-01-SchedCausingSpills.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mcpu=yonah -stats 2>&1 | \ ; RUN: not grep "Number of register spills" ; END. diff --git a/test/CodeGen/X86/Stats/2006-05-02-InstrSched1.ll b/test/CodeGen/X86/2006-05-02-InstrSched1.ll index 1c75f93915..0afddd8f87 100644 --- a/test/CodeGen/X86/Stats/2006-05-02-InstrSched1.ll +++ b/test/CodeGen/X86/2006-05-02-InstrSched1.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -relocation-model=static -stats 2>&1 | \ ; RUN: grep asm-printer | grep 14 ; diff --git a/test/CodeGen/X86/Stats/2006-05-02-InstrSched2.ll b/test/CodeGen/X86/2006-05-02-InstrSched2.ll index 95eefa1e71..222b7a0b41 100644 --- a/test/CodeGen/X86/Stats/2006-05-02-InstrSched2.ll +++ b/test/CodeGen/X86/2006-05-02-InstrSched2.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -stats 2>&1 | \ ; RUN: grep asm-printer | grep 13 diff --git a/test/CodeGen/X86/Stats/2006-05-11-InstrSched.ll b/test/CodeGen/X86/2006-05-11-InstrSched.ll index 37c510786a..6912351d7b 100644 --- a/test/CodeGen/X86/Stats/2006-05-11-InstrSched.ll +++ b/test/CodeGen/X86/2006-05-11-InstrSched.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mcpu=penryn -mattr=+sse2 -stats -realign-stack=0 2>&1 | \ ; RUN: grep "asm-printer" | grep 35 diff --git a/test/CodeGen/X86/Stats/2008-02-18-TailMergingBug.ll b/test/CodeGen/X86/2008-02-18-TailMergingBug.ll index a1b973d7cc..363a6008a0 100644 --- a/test/CodeGen/X86/Stats/2008-02-18-TailMergingBug.ll +++ b/test/CodeGen/X86/2008-02-18-TailMergingBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mcpu=yonah -stats 2>&1 | grep "Number of block tails merged" | grep 16 ; PR1909 diff --git a/test/CodeGen/X86/Stats/2008-10-27-CoalescerBug.ll b/test/CodeGen/X86/2008-10-27-CoalescerBug.ll index b2cf34cd20..0310a5dcb5 100644 --- a/test/CodeGen/X86/Stats/2008-10-27-CoalescerBug.ll +++ b/test/CodeGen/X86/2008-10-27-CoalescerBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -stats 2>&1 | FileCheck %s ; Now this test spills one register. But a reload in the loop is cheaper than ; the divsd so it's a win. diff --git a/test/CodeGen/X86/Stats/2009-02-25-CommuteBug.ll b/test/CodeGen/X86/2009-02-25-CommuteBug.ll index 9cbf350940..9ea34e27a1 100644 --- a/test/CodeGen/X86/Stats/2009-02-25-CommuteBug.ll +++ b/test/CodeGen/X86/2009-02-25-CommuteBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mattr=+sse2 -stats 2>&1 | not grep commuted ; rdar://6608609 diff --git a/test/CodeGen/X86/Stats/2009-02-26-MachineLICMBug.ll b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll index d50fe6f73a..68a9fafb6d 100644 --- a/test/CodeGen/X86/Stats/2009-02-26-MachineLICMBug.ll +++ b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn -stats 2>&1 | grep "5 machine-licm" ; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn | FileCheck %s ; rdar://6627786 diff --git a/test/CodeGen/X86/Stats/2009-03-23-MultiUseSched.ll b/test/CodeGen/X86/2009-03-23-MultiUseSched.ll index d934ec9a88..351a1722a2 100644 --- a/test/CodeGen/X86/Stats/2009-03-23-MultiUseSched.ll +++ b/test/CodeGen/X86/2009-03-23-MultiUseSched.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-linux -relocation-model=static -o /dev/null -stats -info-output-file - > %t ; RUN: not grep spill %t ; RUN: not grep "%rsp" %t diff --git a/test/CodeGen/X86/Stats/2009-04-16-SpillerUnfold.ll b/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll index ad18a0c5b9..0607eda271 100644 --- a/test/CodeGen/X86/Stats/2009-04-16-SpillerUnfold.ll +++ b/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats 2>&1 | grep "Number of modref unfolded" ; XFAIL: * ; 69408 removed the opportunity for this optimization to work diff --git a/test/CodeGen/X86/2010-01-18-DbgValue.ll b/test/CodeGen/X86/2010-01-18-DbgValue.ll index 7f2b8206b1..7dba332b1b 100644 --- a/test/CodeGen/X86/2010-01-18-DbgValue.ll +++ b/test/CodeGen/X86/2010-01-18-DbgValue.ll @@ -29,23 +29,24 @@ return: ; preds = %entry declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!3} -!18 = metadata !{metadata !1} !0 = metadata !{i32 786689, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (%struct.Rect*)* @foo, null, null, null, i32 11} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 786473, metadata !"b2.c", metadata !"/tmp/", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 0, i32 1, metadata !"b2.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !18, null} ; [ DW_TAG_compile_unit ] -!4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (%struct.Rect*)* @foo, null, null, null, i32 11} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !18, null, metadata !""} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 786453, metadata !19, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6, metadata !7} -!6 = metadata !{i32 786468, metadata !2, metadata !"double", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!7 = metadata !{i32 786451, metadata !2, metadata !"Rect", metadata !2, i32 6, i64 256, i64 64, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_structure_type ] +!6 = metadata !{i32 786468, metadata !19, metadata !2, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 786451, metadata !19, metadata !2, metadata !"Rect", i32 6, i64 256, i64 64, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_structure_type ] !8 = metadata !{metadata !9, metadata !14} -!9 = metadata !{i32 786445, metadata !7, metadata !"P1", metadata !2, i32 7, i64 128, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] -!10 = metadata !{i32 786451, metadata !2, metadata !"Pt", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] +!9 = metadata !{i32 786445, metadata !19, metadata !7, metadata !"P1", i32 7, i64 128, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] +!10 = metadata !{i32 786451, metadata !19, metadata !2, metadata !"Pt", i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] !11 = metadata !{metadata !12, metadata !13} -!12 = metadata !{i32 786445, metadata !10, metadata !"x", metadata !2, i32 2, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] -!13 = metadata !{i32 786445, metadata !10, metadata !"y", metadata !2, i32 3, i64 64, i64 64, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] -!14 = metadata !{i32 786445, metadata !7, metadata !"P2", metadata !2, i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ] +!12 = metadata !{i32 786445, metadata !19, metadata !10, metadata !"x", i32 2, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!13 = metadata !{i32 786445, metadata !19, metadata !10, metadata !"y", i32 3, i64 64, i64 64, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] +!14 = metadata !{i32 786445, metadata !19, metadata !7, metadata !"P2", i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ] !15 = metadata !{i32 11, i32 0, metadata !1, null} !16 = metadata !{i32 12, i32 0, metadata !17, null} !17 = metadata !{i32 786443, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ] +!18 = metadata !{metadata !1} +!19 = metadata !{metadata !"b2.c", metadata !"/tmp/"} diff --git a/test/CodeGen/X86/Stats/2010-01-19-OptExtBug.ll b/test/CodeGen/X86/2010-01-19-OptExtBug.ll index eb4a5c04a2..ec24e73c34 100644 --- a/test/CodeGen/X86/Stats/2010-01-19-OptExtBug.ll +++ b/test/CodeGen/X86/2010-01-19-OptExtBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -relocation-model=pic -disable-fp-elim -stats 2>&1 | not grep ext-opt define fastcc i8* @S_scan_str(i8* %start, i32 %keep_quoted, i32 %keep_delims) nounwind ssp { diff --git a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll index 5707befb9c..8ab93fcb97 100644 --- a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll +++ b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll @@ -199,25 +199,23 @@ declare float @copysignf(float, float) nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!3} -!43 = metadata !{metadata !0, metadata !11, metadata !12, metadata !13, metadata !14, metadata !16, metadata !17, metadata !18} -!44 = metadata !{metadata !1} !0 = metadata !{i32 786689, metadata !1, metadata !"a", metadata !2, i32 1921, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"__divsc3", metadata !"__divsc3", metadata !"__divsc3", metadata !2, i32 1922, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, %0 (float, float, float, float)* @__divsc3, null, null, metadata !43, i32 1922} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 786473, metadata !"libgcc2.c", metadata !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 0, i32 1, metadata !"libgcc2.c", metadata !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !44, null} ; [ DW_TAG_compile_unit ] -!4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!1 = metadata !{i32 786478, metadata !2, metadata !"__divsc3", metadata !"__divsc3", metadata !"__divsc3", metadata !2, i32 1922, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, %0 (float, float, float, float)* @__divsc3, null, null, metadata !43, i32 1922} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !45} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !44, null, metadata !""} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 786453, metadata !45, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6, metadata !9, metadata !9, metadata !9, metadata !9} -!6 = metadata !{i32 786454, metadata !7, metadata !"SCtype", metadata !7, i32 170, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_typedef ] -!7 = metadata !{i32 786473, metadata !"libgcc2.h", metadata !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc", metadata !3} ; [ DW_TAG_file_type ] -!8 = metadata !{i32 786468, metadata !2, metadata !"complex float", metadata !2, i32 0, i64 64, i64 32, i64 0, i32 0, i32 3} ; [ DW_TAG_base_type ] -!9 = metadata !{i32 786454, metadata !7, metadata !"SFtype", metadata !7, i32 167, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ] -!10 = metadata !{i32 786468, metadata !2, metadata !"float", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786454, metadata !46, metadata !7, metadata !"SCtype", i32 170, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_typedef ] +!7 = metadata !{i32 786473, metadata !46} ; [ DW_TAG_file_type ] +!8 = metadata !{i32 786468, metadata !45, metadata !2, metadata !"complex float", i32 0, i64 64, i64 32, i64 0, i32 0, i32 3} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 786454, metadata !46, metadata !7, metadata !"SFtype", i32 167, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ] +!10 = metadata !{i32 786468, metadata !45, metadata !2, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] !11 = metadata !{i32 786689, metadata !1, metadata !"b", metadata !2, i32 1921, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ] !12 = metadata !{i32 786689, metadata !1, metadata !"c", metadata !2, i32 1921, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ] !13 = metadata !{i32 786689, metadata !1, metadata !"d", metadata !2, i32 1921, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ] !14 = metadata !{i32 786688, metadata !15, metadata !"denom", metadata !2, i32 1923, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ] -!15 = metadata !{i32 786443, metadata !1, i32 1922, i32 0} ; [ DW_TAG_lexical_block ] +!15 = metadata !{i32 786443, metadata !2, metadata !1, i32 1922, i32 0} ; [ DW_TAG_lexical_block ] !16 = metadata !{i32 786688, metadata !15, metadata !"ratio", metadata !2, i32 1923, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ] !17 = metadata !{i32 786688, metadata !15, metadata !"x", metadata !2, i32 1923, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ] !18 = metadata !{i32 786688, metadata !15, metadata !"y", metadata !2, i32 1923, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ] @@ -245,3 +243,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !40 = metadata !{i32 1964, i32 0, metadata !15, null} !41 = metadata !{i32 1965, i32 0, metadata !15, null} !42 = metadata !{i32 1969, i32 0, metadata !15, null} +!43 = metadata !{metadata !0, metadata !11, metadata !12, metadata !13, metadata !14, metadata !16, metadata !17, metadata !18} +!44 = metadata !{metadata !1} +!45 = metadata !{metadata !"libgcc2.c", metadata !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc"} +!46 = metadata !{metadata !"libgcc2.h", metadata !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc"} diff --git a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll index fa1e426a8f..6519ca063a 100644 --- a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll +++ b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll @@ -22,22 +22,17 @@ declare void @foo(i32) nounwind optsize noinline ssp declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!2} -!31 = metadata !{metadata !0} -!32 = metadata !{metadata !5, metadata !9, metadata !19} -!33 = metadata !{metadata !4} -!34 = metadata !{metadata !8} -!35 = metadata !{metadata !18, metadata !25, metadata !26} !0 = metadata !{i32 786484, i32 0, metadata !1, metadata !"ret", metadata !"ret", metadata !"", metadata !1, i32 7, metadata !3, i1 false, i1 true, null} ; [ DW_TAG_variable ] -!1 = metadata !{i32 786473, metadata !"foo.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 1, metadata !"foo.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !32, metadata !31} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786473, metadata !36} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !36, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !32, metadata !31, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !4 = metadata !{i32 786689, metadata !5, metadata !"x", metadata !1, i32 12, metadata !3, i32 0, null} ; [ DW_TAG_arg_variable ] -!5 = metadata !{i32 786478, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 13, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, void (i32)* @foo, null, null, metadata !33, i32 13} ; [ DW_TAG_subprogram ] +!5 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 13, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, void (i32)* @foo, null, null, metadata !33, i32 13} ; [ DW_TAG_subprogram ] !6 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] !7 = metadata !{null, metadata !3} !8 = metadata !{i32 786689, metadata !9, metadata !"myvar", metadata !1, i32 17, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ] -!9 = metadata !{i32 786478, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", metadata !1, i32 17, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i8* (%struct.a*)* @bar, null, null, metadata !34, i32 17} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 786478, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", metadata !1, i32 17, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i8* (%struct.a*)* @bar, null, null, metadata !34, i32 17} ; [ DW_TAG_subprogram ] !10 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] !11 = metadata !{metadata !12, metadata !13} !12 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] @@ -47,7 +42,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !16 = metadata !{i32 786445, metadata !14, metadata !"c", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !3} ; [ DW_TAG_member ] !17 = metadata !{i32 786445, metadata !14, metadata !"d", metadata !1, i32 4, i64 64, i64 64, i64 64, i32 0, metadata !13} ; [ DW_TAG_member ] !18 = metadata !{i32 786689, metadata !19, metadata !"argc", metadata !1, i32 22, metadata !3, i32 0, null} ; [ DW_TAG_arg_variable ] -!19 = metadata !{i32 786478, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 22, metadata !20, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, null, null, null, metadata !35, i32 22} ; [ DW_TAG_subprogram ] +!19 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 22, metadata !20, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, null, null, null, metadata !35, i32 22} ; [ DW_TAG_subprogram ] !20 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !21, i32 0, null} ; [ DW_TAG_subroutine_type ] !21 = metadata !{metadata !3, metadata !3, metadata !22} !22 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] @@ -55,10 +50,16 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !24 = metadata !{i32 786468, metadata !1, metadata !"char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] !25 = metadata !{i32 786689, metadata !19, metadata !"argv", metadata !1, i32 22, metadata !22, i32 0, null} ; [ DW_TAG_arg_variable ] !26 = metadata !{i32 786688, metadata !27, metadata !"e", metadata !1, i32 23, metadata !14, i32 0, null} ; [ DW_TAG_auto_variable ] -!27 = metadata !{i32 786443, metadata !19, i32 22, i32 0} ; [ DW_TAG_lexical_block ] +!27 = metadata !{i32 786443, metadata !36, metadata !19, i32 22, i32 0, i32 0} ; [ DW_TAG_lexical_block ] !28 = metadata !{i32 18, i32 0, metadata !29, null} -!29 = metadata !{i32 786443, metadata !9, i32 17, i32 0} ; [ DW_TAG_lexical_block ] +!29 = metadata !{i32 786443, metadata !36, metadata !9, i32 17, i32 0, i32 1} ; [ DW_TAG_lexical_block ] !30 = metadata !{i32 19, i32 0, metadata !29, null} +!31 = metadata !{metadata !0} +!32 = metadata !{metadata !5, metadata !9, metadata !19} +!33 = metadata !{metadata !4} +!34 = metadata !{metadata !8} +!35 = metadata !{metadata !18, metadata !25, metadata !26} +!36 = metadata !{metadata !"foo.c", metadata !"/tmp/"} ; The variable bar:myvar changes registers after the first movq. ; It is cobbered by popq %rbx diff --git a/test/CodeGen/X86/2010-05-28-Crash.ll b/test/CodeGen/X86/2010-05-28-Crash.ll index e1154e340d..4ea3bf0778 100644 --- a/test/CodeGen/X86/2010-05-28-Crash.ll +++ b/test/CodeGen/X86/2010-05-28-Crash.ll @@ -23,25 +23,26 @@ entry: } !llvm.dbg.cu = !{!3} -!15 = metadata !{metadata !0} -!16 = metadata !{metadata !7} -!17 = metadata !{metadata !1, metadata !8} !0 = metadata !{i32 786689, metadata !1, metadata !"y", metadata !2, i32 2, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @foo, null, null, metadata !15, i32 2} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 786473, metadata !"f.c", metadata !"/tmp", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 0, i32 1, metadata !"f.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !17, null} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @foo, null, null, metadata !15, i32 2} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !18} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !17, null, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6, metadata !6} !6 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !7 = metadata !{i32 786689, metadata !8, metadata !"x", metadata !2, i32 6, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] -!8 = metadata !{i32 786478, i32 0, metadata !2, metadata !"bar", metadata !"bar", metadata !"bar", metadata !2, i32 6, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @bar, null, null, metadata !16, i32 6} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 786478, metadata !2, metadata !"bar", metadata !"bar", metadata !"bar", metadata !2, i32 6, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @bar, null, null, metadata !16, i32 6} ; [ DW_TAG_subprogram ] !9 = metadata !{i32 3, i32 0, metadata !10, null} -!10 = metadata !{i32 786443, metadata !1, i32 2, i32 0} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 786443, metadata !2, metadata !1, i32 2, i32 0} ; [ DW_TAG_lexical_block ] !11 = metadata !{i32 1} !12 = metadata !{i32 3, i32 0, metadata !10, metadata !13} !13 = metadata !{i32 7, i32 0, metadata !14, null} -!14 = metadata !{i32 786443, metadata !8, i32 6, i32 0} ; [ DW_TAG_lexical_block ] +!14 = metadata !{i32 786443, metadata !2, metadata !8, i32 6, i32 0} ; [ DW_TAG_lexical_block ] +!15 = metadata !{metadata !0} +!16 = metadata !{metadata !7} +!17 = metadata !{metadata !1, metadata !8} +!18 = metadata !{metadata !"f.c", metadata !"/tmp"} ;CHECK: DEBUG_VALUE: bar:x <- E ;CHECK: Ltmp diff --git a/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll b/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll index 898f808128..b764b0b345 100644 --- a/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll +++ b/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll @@ -22,14 +22,14 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.lv = !{!0, !14, !15, !16, !17, !24, !25, !28} !0 = metadata !{i32 786689, metadata !1, metadata !"this", metadata !3, i32 11, metadata !12, i32 0, null} ; [ DW_TAG_arg_variable ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"bar", metadata !"bar", metadata !"_ZN3foo3barEi", metadata !3, i32 11, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 (%struct.foo*, i32)* @_ZN3foo3bazEi, null, null, null, i32 11} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786478, metadata !3, metadata !2, metadata !"bar", metadata !"bar", metadata !"_ZN3foo3barEi", i32 11, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 (%struct.foo*, i32)* @_ZN3foo3bazEi, null, null, null, i32 11} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786451, metadata !3, metadata !"foo", metadata !3, i32 3, i64 32, i64 32, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_structure_type ] -!3 = metadata !{i32 786473, metadata !"foo.cp", metadata !"/tmp/", metadata !4} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786473, metadata !31} ; [ DW_TAG_file_type ] !4 = metadata !{i32 786449, i32 0, i32 4, metadata !"foo.cp", metadata !"/tmp/", metadata !"4.2.1 LLVM build", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] !5 = metadata !{metadata !6, metadata !1, metadata !8} !6 = metadata !{i32 786445, metadata !2, metadata !"y", metadata !3, i32 8, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_member ] !7 = metadata !{i32 786468, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!8 = metadata !{i32 786478, i32 0, metadata !2, metadata !"baz", metadata !"baz", metadata !"_ZN3foo3bazEi", metadata !3, i32 15, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 (%struct.foo*, i32)* @_ZN3foo3bazEi, null, null, null, i32 15} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 786478, metadata !3, metadata !2, metadata !"baz", metadata !"baz", metadata !"_ZN3foo3bazEi", i32 15, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 (%struct.foo*, i32)* @_ZN3foo3bazEi, null, null, null, i32 15} ; [ DW_TAG_subprogram ] !9 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !10, i32 0, null} ; [ DW_TAG_subroutine_type ] !10 = metadata !{metadata !7, metadata !11, metadata !7} !11 = metadata !{i32 786447, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !2} ; [ DW_TAG_pointer_type ] @@ -39,7 +39,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !15 = metadata !{i32 786689, metadata !8, metadata !"this", metadata !3, i32 15, metadata !12, i32 0, null} ; [ DW_TAG_arg_variable ] !16 = metadata !{i32 786689, metadata !8, metadata !"x", metadata !3, i32 15, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] !17 = metadata !{i32 786689, metadata !18, metadata !"argc", metadata !3, i32 19, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] -!18 = metadata !{i32 786478, i32 0, metadata !3, metadata !"main", metadata !"main", metadata !"main", metadata !3, i32 19, metadata !19, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, null, null, null, null, i32 19} ; [ DW_TAG_subprogram ] +!18 = metadata !{i32 786478, metadata !3, metadata !3, metadata !"main", metadata !"main", metadata !"main", i32 19, metadata !19, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, null, null, null, null, i32 19} ; [ DW_TAG_subprogram ] !19 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !20, i32 0, null} ; [ DW_TAG_subroutine_type ] !20 = metadata !{metadata !7, metadata !7, metadata !21} !21 = metadata !{i32 786447, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ] @@ -52,3 +52,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !28 = metadata !{i32 786688, metadata !26, metadata !"b", metadata !3, i32 21, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ] !29 = metadata !{i32 16, i32 0, metadata !30, null} !30 = metadata !{i32 786443, metadata !8, i32 15, i32 0} ; [ DW_TAG_lexical_block ] +!31 = metadata !{metadata !"foo.cp", metadata !"/tmp/"} diff --git a/test/CodeGen/X86/2010-08-04-StackVariable.ll b/test/CodeGen/X86/2010-08-04-StackVariable.ll index 4ae6996c02..aaa562a439 100644 --- a/test/CodeGen/X86/2010-08-04-StackVariable.ll +++ b/test/CodeGen/X86/2010-08-04-StackVariable.ll @@ -77,27 +77,27 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!3} !46 = metadata !{metadata !0, metadata !9, metadata !16, metadata !17, metadata !20} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 11} ; [ DW_TAG_subprogram ] +!0 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 11} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786451, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ] !2 = metadata !{i32 786473, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 0, i32 4, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !46, null} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786449, i32 4, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !46, null, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9} !5 = metadata !{i32 786445, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] !6 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] !7 = metadata !{i32 786445, metadata !1, metadata !"Kind", metadata !2, i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ] !8 = metadata !{i32 786468, metadata !2, metadata !"unsigned int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!9 = metadata !{i32 786478, i32 0, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", metadata !2, i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 12} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 786478, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", metadata !2, i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 12} ; [ DW_TAG_subprogram ] !10 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] !11 = metadata !{null, metadata !12, metadata !13} !12 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] !13 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !14 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ] !15 = metadata !{null, metadata !12} -!16 = metadata !{i32 786478, i32 0, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", metadata !2, i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev, null, null, null, i32 11} ; [ DW_TAG_subprogram ] -!17 = metadata !{i32 786478, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", metadata !2, i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal, null, null, null, i32 16} ; [ DW_TAG_subprogram ] +!16 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", metadata !2, i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev, null, null, null, i32 11} ; [ DW_TAG_subprogram ] +!17 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", metadata !2, i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal, null, null, null, i32 16} ; [ DW_TAG_subprogram ] !18 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ] !19 = metadata !{metadata !13, metadata !13, metadata !1} -!20 = metadata !{i32 786478, i32 0, metadata !2, metadata !"main", metadata !"main", metadata !"main", metadata !2, i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main, null, null, null, i32 23} ; [ DW_TAG_subprogram ] +!20 = metadata !{i32 786478, metadata !2, metadata !"main", metadata !"main", metadata !"main", metadata !2, i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main, null, null, null, i32 23} ; [ DW_TAG_subprogram ] !21 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ] !22 = metadata !{metadata !13} !23 = metadata !{i32 786689, metadata !17, metadata !"i", metadata !2, i32 16, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ] @@ -105,7 +105,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !25 = metadata !{i32 786689, metadata !17, metadata !"location", metadata !2, i32 16, metadata !26, i32 0, null} ; [ DW_TAG_arg_variable ] !26 = metadata !{i32 786448, metadata !2, metadata !"SVal", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ] !27 = metadata !{i32 17, i32 0, metadata !28, null} -!28 = metadata !{i32 786443, metadata !17, i32 16, i32 0, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 786443, metadata !2, metadata !17, i32 16, i32 0, i32 2} ; [ DW_TAG_lexical_block ] !29 = metadata !{i32 18, i32 0, metadata !28, null} !30 = metadata !{i32 20, i32 0, metadata !28, null} !31 = metadata !{i32 786689, metadata !16, metadata !"this", metadata !2, i32 11, metadata !32, i32 0, null} ; [ DW_TAG_arg_variable ] @@ -113,11 +113,11 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !33 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_pointer_type ] !34 = metadata !{i32 11, i32 0, metadata !16, null} !35 = metadata !{i32 11, i32 0, metadata !36, null} -!36 = metadata !{i32 786443, metadata !37, i32 11, i32 0, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] -!37 = metadata !{i32 786443, metadata !16, i32 11, i32 0, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!36 = metadata !{i32 786443, metadata !2, metadata !37, i32 11, i32 0, i32 1} ; [ DW_TAG_lexical_block ] +!37 = metadata !{i32 786443, metadata !2, metadata !16, i32 11, i32 0, i32 0} ; [ DW_TAG_lexical_block ] !38 = metadata !{i32 786688, metadata !39, metadata !"v", metadata !2, i32 24, metadata !1, i32 0, null} ; [ DW_TAG_auto_variable ] -!39 = metadata !{i32 786443, metadata !40, i32 23, i32 0, metadata !2, i32 4} ; [ DW_TAG_lexical_block ] -!40 = metadata !{i32 786443, metadata !20, i32 23, i32 0, metadata !2, i32 3} ; [ DW_TAG_lexical_block ] +!39 = metadata !{i32 786443, metadata !2, metadata !40, i32 23, i32 0, i32 4} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 786443, metadata !2, metadata !20, i32 23, i32 0, i32 3} ; [ DW_TAG_lexical_block ] !41 = metadata !{i32 24, i32 0, metadata !39, null} !42 = metadata !{i32 25, i32 0, metadata !39, null} !43 = metadata !{i32 26, i32 0, metadata !39, null} diff --git a/test/CodeGen/X86/2010-09-16-EmptyFilename.ll b/test/CodeGen/X86/2010-09-16-EmptyFilename.ll index 60fb68b791..de0d216e26 100644 --- a/test/CodeGen/X86/2010-09-16-EmptyFilename.ll +++ b/test/CodeGen/X86/2010-09-16-EmptyFilename.ll @@ -13,18 +13,20 @@ entry: } !llvm.dbg.cu = !{!2} -!13 = metadata !{metadata !0, metadata !6} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 53, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @foo} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"bug.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 114084)", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !13, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 53, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @foo} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !14} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !15, i32 12, metadata !"clang version 2.9 (trunk 114084)", i1 false, metadata !"", i32 0, null, null, metadata !13, null, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null, null, metadata !13, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 786478, i32 0, metadata !7, metadata !"bar", metadata !"bar", metadata !"bar", metadata !7, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @bar} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 786473, metadata !"bug.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!6 = metadata !{i32 786478, metadata !7, metadata !"bar", metadata !"bar", metadata !"bar", metadata !7, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @bar} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786473, metadata !15} ; [ DW_TAG_file_type ] !8 = metadata !{i32 53, i32 13, metadata !9, null} !9 = metadata !{i32 786443, metadata !0, i32 53, i32 11, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] !10 = metadata !{i32 4, i32 13, metadata !11, null} !11 = metadata !{i32 786443, metadata !12, i32 4, i32 13, metadata !7, i32 2} ; [ DW_TAG_lexical_block ] !12 = metadata !{i32 786443, metadata !6, i32 4, i32 11, metadata !7, i32 1} ; [ DW_TAG_lexical_block ] +!13 = metadata !{metadata !0, metadata !6} +!14 = metadata !{metadata !"", metadata !"/private/tmp"} +!15 = metadata !{metadata !"bug.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/2010-11-02-DbgParameter.ll b/test/CodeGen/X86/2010-11-02-DbgParameter.ll index 9cf2747b77..31a6822b34 100644 --- a/test/CodeGen/X86/2010-11-02-DbgParameter.ll +++ b/test/CodeGen/X86/2010-11-02-DbgParameter.ll @@ -16,12 +16,10 @@ entry: declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!2} -!15 = metadata !{metadata !0} -!16 = metadata !{metadata !6} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (%struct.bar*)* @foo, null, null, metadata !16, i32 3} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"one.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"one.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 117922)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !15, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (%struct.bar*)* @foo, null, null, metadata !16, i32 3} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !17} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 117922)", i1 true, metadata !"", i32 0, null, null, metadata !15, null, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] @@ -34,3 +32,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !12 = metadata !{i32 3, i32 47, metadata !0, null} !13 = metadata !{i32 4, i32 2, metadata !14, null} !14 = metadata !{i32 786443, metadata !0, i32 3, i32 50, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!15 = metadata !{metadata !0} +!16 = metadata !{metadata !6} +!17 = metadata !{metadata !"one.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/2010-12-02-MC-Set.ll b/test/CodeGen/X86/2010-12-02-MC-Set.ll index 628e5ba606..4d8d974f70 100644 --- a/test/CodeGen/X86/2010-12-02-MC-Set.ll +++ b/test/CodeGen/X86/2010-12-02-MC-Set.ll @@ -9,9 +9,9 @@ entry: !llvm.dbg.cu = !{!2} !7 = metadata !{metadata !0} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ] +!0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !"e.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"e.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 120563)", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !7, null} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 120563)", i1 false, metadata !"", i32 0, null, null, metadata !7, null, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{null} !5 = metadata !{i32 5, i32 1, metadata !6, null} diff --git a/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll b/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll index 3d3fff9604..2355528a81 100644 --- a/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll +++ b/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll @@ -70,35 +70,36 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone declare i32 @puts(i8* nocapture) nounwind !llvm.dbg.cu = !{!2} -!28 = metadata !{metadata !0, metadata !6} -!29 = metadata !{metadata !10, metadata !11, metadata !12} -!30 = metadata !{metadata !14, metadata !17} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"gcd", metadata !"gcd", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i64 (i64, i64)* @gcd, null, null, metadata !29, i32 0} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"rem_small.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"rem_small.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 124117)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !28, null, null} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"gcd", metadata !"gcd", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i64 (i64, i64)* @gcd, null, null, metadata !29, i32 0} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !31} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !31, i32 12, metadata !"clang version 2.9 (trunk 124117)", i1 true, metadata !"", i32 0, null, null, metadata !28, null, null} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !1, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} -!5 = metadata !{i32 786468, metadata !2, metadata !"long int", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 786478, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 25, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @main, null, null, metadata !30, i32 0} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{i32 786468, null, metadata !2, metadata !"long int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 25, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @main, null, null, metadata !30, i32 0} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786453, metadata !1, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !8 = metadata !{metadata !9} -!9 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !10 = metadata !{i32 786689, metadata !0, metadata !"a", metadata !1, i32 5, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !11 = metadata !{i32 786689, metadata !0, metadata !"b", metadata !1, i32 5, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !12 = metadata !{i32 786688, metadata !13, metadata !"c", metadata !1, i32 6, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] -!13 = metadata !{i32 786443, metadata !0, i32 5, i32 52, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!13 = metadata !{i32 786443, metadata !1, metadata !0, i32 5, i32 52, i32 0} ; [ DW_TAG_lexical_block ] !14 = metadata !{i32 786688, metadata !15, metadata !"m", metadata !1, i32 26, metadata !16, i32 0, null} ; [ DW_TAG_auto_variable ] -!15 = metadata !{i32 786443, metadata !6, i32 25, i32 12, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] -!16 = metadata !{i32 786468, metadata !2, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!15 = metadata !{i32 786443, metadata !1, metadata !6, i32 25, i32 12, i32 2} ; [ DW_TAG_lexical_block ] +!16 = metadata !{i32 786468, null, metadata !2, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] !17 = metadata !{i32 786688, metadata !15, metadata !"z_s", metadata !1, i32 27, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ] !18 = metadata !{i32 5, i32 41, metadata !0, null} !19 = metadata !{i32 5, i32 49, metadata !0, null} !20 = metadata !{i32 7, i32 5, metadata !13, null} !21 = metadata !{i32 8, i32 9, metadata !22, null} -!22 = metadata !{i32 786443, metadata !13, i32 7, i32 14, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!22 = metadata !{i32 786443, metadata !1, metadata !13, i32 7, i32 14, i32 1} ; [ DW_TAG_lexical_block ] !23 = metadata !{i32 9, i32 9, metadata !22, null} !24 = metadata !{i32 26, i32 38, metadata !15, null} !25 = metadata !{i32 27, i32 38, metadata !15, null} !26 = metadata !{i32 28, i32 9, metadata !15, null} !27 = metadata !{i32 30, i32 1, metadata !15, null} +!28 = metadata !{metadata !0, metadata !6} +!29 = metadata !{metadata !10, metadata !11, metadata !12} +!30 = metadata !{metadata !14, metadata !17} +!31 = metadata !{metadata !"rem_small.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/Stats/2011-06-12-FastAllocSpill.ll b/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll index 47ef693cc2..6f43b94b26 100644 --- a/test/CodeGen/X86/Stats/2011-06-12-FastAllocSpill.ll +++ b/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -O0 -disable-fp-elim -relocation-model=pic -stats 2>&1 | FileCheck %s ; ; This test should not cause any spilling with RAFast. diff --git a/test/CodeGen/X86/2011-09-14-valcoalesce.ll b/test/CodeGen/X86/2011-09-14-valcoalesce.ll index a5ec614a94..54d2b40350 100644 --- a/test/CodeGen/X86/2011-09-14-valcoalesce.ll +++ b/test/CodeGen/X86/2011-09-14-valcoalesce.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -disable-code-place | FileCheck %s +; RUN: llc < %s -march=x86 -disable-block-placement | FileCheck %s ; ; Test RegistersDefinedFromSameValue. We have multiple copies of the same vreg: ; while.body85.i: diff --git a/test/CodeGen/X86/Stats/2012-03-26-PostRALICMBug.ll b/test/CodeGen/X86/2012-03-26-PostRALICMBug.ll index 18a3313773..90d8d3d2dd 100644 --- a/test/CodeGen/X86/Stats/2012-03-26-PostRALICMBug.ll +++ b/test/CodeGen/X86/2012-03-26-PostRALICMBug.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -stats 2>&1 | \ ; RUN: not grep "Number of machine instructions hoisted out of loops post regalloc" diff --git a/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll b/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll index f149e4a11e..9525653f3f 100644 --- a/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll +++ b/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll @@ -42,9 +42,10 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !2 = metadata !{i32 0} !3 = metadata !{null} !4 = metadata !{i32 786689, null, metadata !"hg", metadata !5, i32 67109589, metadata !6, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [hg] [line 725] -!5 = metadata !{i32 786473, metadata !"MultiSource/Benchmarks/Olden/bh/newbh.c", metadata !"MultiSource/Benchmarks/Olden/bh", null} ; [ DW_TAG_file_type ] -!6 = metadata !{i32 786454, null, metadata !"hgstruct", metadata !5, i32 492, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] [hgstruct] [line 492, size 0, align 0, offset 0] [from ] -!7 = metadata !{i32 786451, null, metadata !"", metadata !5, i32 487, i64 512, i64 64, i32 0, i32 0, null, null, i32 0, i32 0, i32 0} ; [ DW_TAG_structure_type ] [line 487, size 512, align 64, offset 0] [from ] +!5 = metadata !{i32 786473, metadata !11} ; [ DW_TAG_file_type ] +!6 = metadata !{i32 786454, metadata !11, null, metadata !"hgstruct", i32 492, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] [hgstruct] [line 492, size 0, align 0, offset 0] [from ] +!7 = metadata !{i32 786451, metadata !11, null, metadata !"", i32 487, i64 512, i64 64, i32 0, i32 0, null, null, i32 0, i32 0, i32 0} ; [ DW_TAG_structure_type ] [line 487, size 512, align 64, offset 0] [from ] !8 = metadata !{metadata !"short", metadata !9} !9 = metadata !{metadata !"omnipotent char", metadata !10} !10 = metadata !{metadata !"Simple C/C++ TBAA"} +!11 = metadata !{metadata !"MultiSource/Benchmarks/Olden/bh/newbh.c", metadata !"MultiSource/Benchmarks/Olden/bh"} diff --git a/test/CodeGen/X86/2012-11-30-misched-dbg.ll b/test/CodeGen/X86/2012-11-30-misched-dbg.ll index f171c16df3..a0fbbb2ff9 100644 --- a/test/CodeGen/X86/2012-11-30-misched-dbg.ll +++ b/test/CodeGen/X86/2012-11-30-misched-dbg.ll @@ -78,11 +78,12 @@ declare i32 @__sprintf_chk(i8*, i32, i64, i8*, ...) !11 = metadata !{i32 786443, metadata !12, i32 250, i32 0, metadata !14, i32 24} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] !12 = metadata !{i32 786443, metadata !13, i32 249, i32 0, metadata !14, i32 23} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] !13 = metadata !{i32 786443, metadata !3, i32 221, i32 0, metadata !14, i32 19} ; [ DW_TAG_lexical_block ] [MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] -!14 = metadata !{i32 786473, metadata !"MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c", metadata !"MultiSource/Benchmarks/MiBench/consumer-typeset", null} ; [ DW_TAG_file_type ] -!15 = metadata !{i32 786433, null, metadata !"", null, i32 0, i64 160, i64 8, i32 0, i32 0, metadata !16, metadata !17, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 160, align 8, offset 0] [from char] -!16 = metadata !{i32 786468, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char] +!14 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ] +!15 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 160, i64 8, i32 0, i32 0, metadata !16, metadata !17, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 160, align 8, offset 0] [from char] +!16 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char] !17 = metadata !{metadata !18} !18 = metadata !{i32 786465, i64 0, i64 20} ; [ DW_TAG_subrange_type ] [0, 19] +!19 = metadata !{metadata !"MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c", metadata !"MultiSource/Benchmarks/MiBench/consumer-typeset"} ; Test DebugValue uses visited by RegisterPressureTracker findUseBetween(). ; @@ -102,7 +103,7 @@ cond.true: ; preds = %entry unreachable cond.end: ; preds = %entry - call void @llvm.dbg.declare(metadata !{%"class.__gnu_cxx::hash_map"* %X}, metadata !21) + call void @llvm.dbg.declare(metadata !{%"class.__gnu_cxx::hash_map"* %X}, metadata !31) %_M_num_elements.i.i.i.i = getelementptr inbounds %"class.__gnu_cxx::hash_map"* %X, i64 0, i32 0, i32 5 invoke void @_Znwm() to label %exit.i unwind label %lpad2.i.i.i.i @@ -126,9 +127,10 @@ declare i32 @__gxx_personality_v0(...) declare void @_Znwm() -!llvm.dbg.cu = !{!20} +!llvm.dbg.cu = !{!30} -!20 = metadata !{i32 786449, i32 0, i32 4, metadata !"SingleSource/Benchmarks/Shootout-C++/hash.cpp", metadata !"SingleSource/Benchmarks/Shootout-C++", metadata !"clang version 3.3 (trunk 169129) (llvm/trunk 169135)", i1 true, i1 true, metadata !"", i32 0, null, null, null, null} ; [ DW_TAG_compile_unit ] [SingleSource/Benchmarks/Shootout-C++/hash.cpp] [DW_LANG_C_plus_plus] -!21 = metadata !{i32 786688, null, metadata !"X", null, i32 29, metadata !22, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [X] [line 29] -!22 = metadata !{i32 786454, null, metadata !"HM", metadata !23, i32 28, i64 0, i64 0, i64 0, i32 0, null} ; [ DW_TAG_typedef ] [HM] [line 28, size 0, align 0, offset 0] [from ] -!23 = metadata !{i32 786473, metadata !"SingleSource/Benchmarks/Shootout-C++/hash.cpp", metadata !"SingleSource/Benchmarks/Shootout-C++", null} ; [ DW_TAG_file_type ] +!30 = metadata !{i32 786449, i32 0, i32 4, metadata !"SingleSource/Benchmarks/Shootout-C++/hash.cpp", metadata !"SingleSource/Benchmarks/Shootout-C++", metadata !"clang version 3.3 (trunk 169129) (llvm/trunk 169135)", i1 true, i1 true, metadata !"", i32 0, null, null, null, null} ; [ DW_TAG_compile_unit ] [SingleSource/Benchmarks/Shootout-C++/hash.cpp] [DW_LANG_C_plus_plus] +!31 = metadata !{i32 786688, null, metadata !"X", null, i32 29, metadata !32, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [X] [line 29] +!32 = metadata !{i32 786454, metadata !34, null, metadata !"HM", i32 28, i64 0, i64 0, i64 0, i32 0, null} ; [ DW_TAG_typedef ] [HM] [line 28, size 0, align 0, offset 0] [from ] +!33 = metadata !{i32 786473, metadata !34} ; [ DW_TAG_file_type ] +!34 = metadata !{metadata !"SingleSource/Benchmarks/Shootout-C++/hash.cpp", metadata !"SingleSource/Benchmarks/Shootout-C++"} diff --git a/test/CodeGen/X86/2012-11-30-regpres-dbg.ll b/test/CodeGen/X86/2012-11-30-regpres-dbg.ll index d290d514cc..df93c5647d 100644 --- a/test/CodeGen/X86/2012-11-30-regpres-dbg.ll +++ b/test/CodeGen/X86/2012-11-30-regpres-dbg.ll @@ -39,5 +39,6 @@ invoke.cont44: ; preds = %if.end !1 = metadata !{metadata !2} !2 = metadata !{null, null} !3 = metadata !{i32 786688, null, metadata !"callback", null, i32 214, metadata !4, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [callback] [line 214] -!4 = metadata !{i32 786451, null, metadata !"btCompoundLeafCallback", metadata !5, i32 90, i64 512, i64 64, i32 0, i32 0, null, null, i32 0, null, null} ; [ DW_TAG_structure_type ] [btCompoundLeafCallback] [line 90, size 512, align 64, offset 0] [from ] -!5 = metadata !{i32 786473, metadata !"MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp", metadata !"MultiSource/Benchmarks/Bullet", null} ; [ DW_TAG_file_type ] +!4 = metadata !{i32 786451, metadata !6, null, metadata !"btCompoundLeafCallback", i32 90, i64 512, i64 64, i32 0, i32 0, null, null, i32 0, null, null} ; [ DW_TAG_structure_type ] [btCompoundLeafCallback] [line 90, size 512, align 64, offset 0] [from ] +!5 = metadata !{i32 786473, metadata !6} ; [ DW_TAG_file_type ] +!6 = metadata !{metadata !"MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp", metadata !"MultiSource/Benchmarks/Bullet"} diff --git a/test/CodeGen/X86/2013-01-09-DAGCombineBug.ll b/test/CodeGen/X86/2013-01-09-DAGCombineBug.ll index db7ec8ae26..1b417e54a2 100644 --- a/test/CodeGen/X86/2013-01-09-DAGCombineBug.ll +++ b/test/CodeGen/X86/2013-01-09-DAGCombineBug.ll @@ -39,3 +39,36 @@ define void @t() nounwind uwtable ssp { ; <label>:11 ; preds = %11, %4 br label %11 } + +; PR15608 +@global = external constant [2 x i8] + +define void @PR15608() { +bb: + br label %bb3 + +bb1: ; No predecessors! + br i1 icmp ult (i64 xor (i64 zext (i1 trunc (i192 lshr (i192 or (i192 shl (i192 zext (i64 trunc (i128 lshr (i128 trunc (i384 lshr (i384 or (i384 shl (i384 zext (i64 ptrtoint ([2 x i8]* @global to i64) to i384), i384 192), i384 425269881901436522087161771558896140289), i384 128) to i128), i128 64) to i64) to i192), i192 64), i192 1), i192 128) to i1) to i64), i64 1), i64 1), label %bb2, label %bb3 + +bb2: ; preds = %bb1 + unreachable + +bb3: ; preds = %bb1, %bb + br i1 xor (i1 trunc (i192 lshr (i192 or (i192 shl (i192 zext (i64 trunc (i128 lshr (i128 trunc (i384 lshr (i384 or (i384 shl (i384 zext (i64 ptrtoint ([2 x i8]* @global to i64) to i384), i384 192), i384 425269881901436522087161771558896140289), i384 128) to i128), i128 64) to i64) to i192), i192 64), i192 1), i192 128) to i1), i1 trunc (i192 lshr (i192 or (i192 and (i192 or (i192 shl (i192 zext (i64 trunc (i128 lshr (i128 trunc (i384 lshr (i384 or (i384 shl (i384 zext (i64 ptrtoint ([2 x i8]* @global to i64) to i384), i384 192), i384 425269881901436522087161771558896140289), i384 128) to i128), i128 64) to i64) to i192), i192 64), i192 1), i192 -340282366920938463463374607431768211457), i192 shl (i192 zext (i1 trunc (i192 lshr (i192 or (i192 shl (i192 zext (i64 trunc (i128 lshr (i128 trunc (i384 lshr (i384 or (i384 shl (i384 zext (i64 ptrtoint ([2 x i8]* @global to i64) to i384), i384 192), i384 425269881901436522087161771558896140289), i384 128) to i128), i128 64) to i64) to i192), i192 64), i192 1), i192 128) to i1) to i192), i192 128)), i192 128) to i1)), label %bb7, label %bb4 + +bb4: ; preds = %bb6, %bb3 + %tmp = phi i1 [ true, %bb6 ], [ trunc (i192 lshr (i192 or (i192 and (i192 or (i192 shl (i192 zext (i64 trunc (i128 lshr (i128 trunc (i384 lshr (i384 or (i384 shl (i384 zext (i64 ptrtoint ([2 x i8]* @global to i64) to i384), i384 192), i384 425269881901436522087161771558896140289), i384 128) to i128), i128 64) to i64) to i192), i192 64), i192 1), i192 -340282366920938463463374607431768211457), i192 shl (i192 zext (i1 trunc (i192 lshr (i192 or (i192 shl (i192 zext (i64 trunc (i128 lshr (i128 trunc (i384 lshr (i384 or (i384 shl (i384 zext (i64 ptrtoint ([2 x i8]* @global to i64) to i384), i384 192), i384 425269881901436522087161771558896140289), i384 128) to i128), i128 64) to i64) to i192), i192 64), i192 1), i192 128) to i1) to i192), i192 128)), i192 128) to i1), %bb3 ] + br i1 false, label %bb8, label %bb5 + +bb5: ; preds = %bb4 + br i1 %tmp, label %bb8, label %bb6 + +bb6: ; preds = %bb5 + br i1 false, label %bb8, label %bb4 + +bb7: ; preds = %bb3 + unreachable + +bb8: ; preds = %bb6, %bb5, %bb4 + unreachable +} diff --git a/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll b/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll new file mode 100644 index 0000000000..03b6bdeafa --- /dev/null +++ b/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core-avx-i -show-mc-encoding + +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +@b = external global [8 x float], align 32 +@e = external global [8 x float], align 16 + +define void @main() #0 { +entry: + %0 = load <8 x float>* bitcast ([8 x float]* @b to <8 x float>*), align 32, !tbaa !0 + %bitcast.i = extractelement <8 x float> %0, i32 0 + %vecinit.i.i = insertelement <4 x float> undef, float %bitcast.i, i32 0 + %vecinit2.i.i = insertelement <4 x float> %vecinit.i.i, float 0.000000e+00, i32 1 + %vecinit3.i.i = insertelement <4 x float> %vecinit2.i.i, float 0.000000e+00, i32 2 + %vecinit4.i.i = insertelement <4 x float> %vecinit3.i.i, float 0.000000e+00, i32 3 + %1 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %vecinit4.i.i) #2 + %vecext.i.i = extractelement <4 x float> %1, i32 0 + store float %vecext.i.i, float* getelementptr inbounds ([8 x float]* @e, i64 0, i64 0), align 16, !tbaa !0 + unreachable +} + +declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) #1 + +attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind } + +!0 = metadata !{metadata !"omnipotent char", metadata !1} +!1 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/DbgValueOtherTargets.test b/test/CodeGen/X86/DbgValueOtherTargets.test index c95e8c6abd..7b4d431c93 100644 --- a/test/CodeGen/X86/DbgValueOtherTargets.test +++ b/test/CodeGen/X86/DbgValueOtherTargets.test @@ -1,2 +1,2 @@ -; RUN: llc -O0 -march=x86 -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll -; RUN: llc -O0 -march=x86-64 -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -march=x86 -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -march=x86-64 -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/X86/GC/erlang-gc.ll b/test/CodeGen/X86/GC/erlang-gc.ll new file mode 100644 index 0000000000..c55b7f6dcf --- /dev/null +++ b/test/CodeGen/X86/GC/erlang-gc.ll @@ -0,0 +1,25 @@ +; RUN: llc -mtriple=x86_64-linux-gnu < %s | FileCheck %s --check-prefix=CHECK64 +; RUN: llc -mtriple=i686-linux-gnu < %s | FileCheck %s --check-prefix=CHECK32 + +define i32 @main(i32 %x) nounwind gc "erlang" { + %puts = tail call i32 @foo(i32 %x) + ret i32 0 + +; CHECK64: .section .note.gc,"",@progbits +; CHECK64-NEXT: .align 8 +; CHECK64-NEXT: .short 1 # safe point count +; CHECK64-NEXT: .long .Ltmp0 # safe point address +; CHECK64-NEXT: .short 1 # stack frame size (in words) +; CHECK64-NEXT: .short 0 # stack arity +; CHECK64-NEXT: .short 0 # live root count + +; CHECK32: .section .note.gc,"",@progbits +; CHECK32-NEXT: .align 4 +; CHECK32-NEXT: .short 1 # safe point count +; CHECK32-NEXT: .long .Ltmp0 # safe point address +; CHECK32-NEXT: .short 3 # stack frame size (in words) +; CHECK32-NEXT: .short 0 # stack arity +; CHECK32-NEXT: .short 0 # live root count +} + +declare i32 @foo(i32) diff --git a/test/CodeGen/X86/MachineSink-DbgValue.ll b/test/CodeGen/X86/MachineSink-DbgValue.ll index cf5d520073..227ef3466e 100644 --- a/test/CodeGen/X86/MachineSink-DbgValue.ll +++ b/test/CodeGen/X86/MachineSink-DbgValue.ll @@ -26,12 +26,10 @@ bb2: declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!18 = metadata !{metadata !1} -!19 = metadata !{metadata !6, metadata !7, metadata !10} -!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"a.c", metadata !"/private/tmp", metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !18, null, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @foo, null, null, metadata !19, i32 0} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 786473, metadata !"a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] +!0 = metadata !{i32 786449, metadata !20, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, null, null, metadata !18, null, null} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @foo, null, null, metadata !19, i32 0} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] @@ -40,10 +38,13 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !8 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ] !9 = metadata !{i32 786468, metadata !0, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] !10 = metadata !{i32 786688, metadata !11, metadata !"a", metadata !2, i32 3, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ] -!11 = metadata !{i32 786443, metadata !1, i32 2, i32 25, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!11 = metadata !{i32 786443, metadata !20, metadata !1, i32 2, i32 25, i32 0} ; [ DW_TAG_lexical_block ] !12 = metadata !{i32 2, i32 13, metadata !1, null} !13 = metadata !{i32 2, i32 22, metadata !1, null} !14 = metadata !{i32 3, i32 14, metadata !11, null} !15 = metadata !{i32 4, i32 3, metadata !11, null} !16 = metadata !{i32 5, i32 5, metadata !11, null} !17 = metadata !{i32 7, i32 1, metadata !11, null} +!18 = metadata !{metadata !1} +!19 = metadata !{metadata !6, metadata !7, metadata !10} +!20 = metadata !{metadata !"a.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/Stats/MachineSink-PHIUse.ll b/test/CodeGen/X86/MachineSink-PHIUse.ll index 33141680aa..1329200c3e 100644 --- a/test/CodeGen/X86/Stats/MachineSink-PHIUse.ll +++ b/test/CodeGen/X86/MachineSink-PHIUse.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-appel-darwin -disable-cgp-branch-opts -stats 2>&1 | grep "machine-sink" define fastcc void @t() nounwind ssp { diff --git a/test/CodeGen/X86/MergeConsecutiveStores.ll b/test/CodeGen/X86/MergeConsecutiveStores.ll index fbe8879ad6..bb227a0185 100644 --- a/test/CodeGen/X86/MergeConsecutiveStores.ll +++ b/test/CodeGen/X86/MergeConsecutiveStores.ll @@ -337,3 +337,99 @@ block4: ; preds = %4, %.lr.ph ret void } +; Make sure that we merge the consecutive load/store sequence below and use a +; word (16 bit) instead of a byte copy. +; CHECK: MergeLoadStoreBaseIndexOffset +; CHECK: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]] +; CHECK: movw [[REG]], (%{{.*}}) +define void @MergeLoadStoreBaseIndexOffset(i64* %a, i8* %b, i8* %c, i32 %n) { + br label %1 + +; <label>:1 + %.09 = phi i32 [ %n, %0 ], [ %11, %1 ] + %.08 = phi i8* [ %b, %0 ], [ %10, %1 ] + %.0 = phi i64* [ %a, %0 ], [ %2, %1 ] + %2 = getelementptr inbounds i64* %.0, i64 1 + %3 = load i64* %.0, align 1 + %4 = getelementptr inbounds i8* %c, i64 %3 + %5 = load i8* %4, align 1 + %6 = add i64 %3, 1 + %7 = getelementptr inbounds i8* %c, i64 %6 + %8 = load i8* %7, align 1 + store i8 %5, i8* %.08, align 1 + %9 = getelementptr inbounds i8* %.08, i64 1 + store i8 %8, i8* %9, align 1 + %10 = getelementptr inbounds i8* %.08, i64 2 + %11 = add nsw i32 %.09, -1 + %12 = icmp eq i32 %11, 0 + br i1 %12, label %13, label %1 + +; <label>:13 + ret void +} + +; Make sure that we merge the consecutive load/store sequence below and use a +; word (16 bit) instead of a byte copy even if there are intermediate sign +; extensions. +; CHECK: MergeLoadStoreBaseIndexOffsetSext +; CHECK: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]] +; CHECK: movw [[REG]], (%{{.*}}) +define void @MergeLoadStoreBaseIndexOffsetSext(i8* %a, i8* %b, i8* %c, i32 %n) { + br label %1 + +; <label>:1 + %.09 = phi i32 [ %n, %0 ], [ %12, %1 ] + %.08 = phi i8* [ %b, %0 ], [ %11, %1 ] + %.0 = phi i8* [ %a, %0 ], [ %2, %1 ] + %2 = getelementptr inbounds i8* %.0, i64 1 + %3 = load i8* %.0, align 1 + %4 = sext i8 %3 to i64 + %5 = getelementptr inbounds i8* %c, i64 %4 + %6 = load i8* %5, align 1 + %7 = add i64 %4, 1 + %8 = getelementptr inbounds i8* %c, i64 %7 + %9 = load i8* %8, align 1 + store i8 %6, i8* %.08, align 1 + %10 = getelementptr inbounds i8* %.08, i64 1 + store i8 %9, i8* %10, align 1 + %11 = getelementptr inbounds i8* %.08, i64 2 + %12 = add nsw i32 %.09, -1 + %13 = icmp eq i32 %12, 0 + br i1 %13, label %14, label %1 + +; <label>:14 + ret void +} + +; However, we can only merge ignore sign extensions when they are on all memory +; computations; +; CHECK: loadStoreBaseIndexOffsetSextNoSex +; CHECK-NOT: movw (%{{.*}},%{{.*}}), [[REG:%[a-z]+]] +; CHECK-NOT: movw [[REG]], (%{{.*}}) +define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) { + br label %1 + +; <label>:1 + %.09 = phi i32 [ %n, %0 ], [ %12, %1 ] + %.08 = phi i8* [ %b, %0 ], [ %11, %1 ] + %.0 = phi i8* [ %a, %0 ], [ %2, %1 ] + %2 = getelementptr inbounds i8* %.0, i64 1 + %3 = load i8* %.0, align 1 + %4 = sext i8 %3 to i64 + %5 = getelementptr inbounds i8* %c, i64 %4 + %6 = load i8* %5, align 1 + %7 = add i8 %3, 1 + %wrap.4 = sext i8 %7 to i64 + %8 = getelementptr inbounds i8* %c, i64 %wrap.4 + %9 = load i8* %8, align 1 + store i8 %6, i8* %.08, align 1 + %10 = getelementptr inbounds i8* %.08, i64 1 + store i8 %9, i8* %10, align 1 + %11 = getelementptr inbounds i8* %.08, i64 2 + %12 = add nsw i32 %.09, -1 + %13 = icmp eq i32 %12, 0 + br i1 %13, label %14, label %1 + +; <label>:14 + ret void +} diff --git a/test/CodeGen/X86/Stats/lit.local.cfg b/test/CodeGen/X86/Stats/lit.local.cfg deleted file mode 100644 index 1a5fd5ec86..0000000000 --- a/test/CodeGen/X86/Stats/lit.local.cfg +++ /dev/null @@ -1,8 +0,0 @@ -config.suffixes = ['.ll', '.c', '.cpp'] - -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: - config.unsupported = True - -if not config.root.enable_assertions: - config.unsupported = True diff --git a/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll new file mode 100644 index 0000000000..4192f13d89 --- /dev/null +++ b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll @@ -0,0 +1,204 @@ +; RUN: llc < %s -mtriple=i386-linux-gnu -mcpu=atom 2>&1 | \ +; RUN: grep "calll" | not grep "(" +; RUN: llc < %s -mtriple=i386-linux-gnu -mcpu=core2 2>&1 | \ +; RUN: grep "calll" | grep "4-byte Folded Reload" + +%struct.targettype = type {i32} +%struct.op_ptr1 = type opaque +%struct.op_ptr2 = type opaque +%union.anon = type { [8 x i32], [48 x i8] } +%struct.const1 = type { [64 x i16], i8 } +%struct.const2 = type { [17 x i8], [256 x i8], i8 } + +%struct.ref1 = type { void (%struct.ref2*)*, i32 (%struct.ref2*)*, void (%struct.ref2*)*, i32 (%struct.ref2*, i8***)*, %struct.op_ptr2** } +%struct.ref2 = type { %struct.localref13*, %struct.localref15*, %struct.localref12*, i8*, i8, i32, %struct.localref11*, i32, i32, i32, i32, i32, i32, i32, double, i8, i8, i32, i8, i8, i8, i32, i8, i32, i8, i8, i8, i32, i32, i32, i32, i32, i32, i8**, i32, i32, i32, i32, i32, [64 x i32]*, [4 x %struct.const1*], [4 x %struct.const2*], [4 x %struct.const2*], i32, %struct.ref3*, i8, i8, [16 x i8], [16 x i8], [16 x i8], i32, i8, i8, i8, i8, i16, i16, i8, i8, i8, %struct.localref10*, i32, i32, i32, i32, i8*, i32, [4 x %struct.ref3*], i32, i32, i32, [10 x i32], i32, i32, i32, i32, i32, %struct.localref8*, %struct.localref9*, %struct.ref1*, %struct.localref7*, %struct.localref6*, %struct.localref5*, %struct.localref1*, %struct.ref4*, %struct.localref2*, %struct.localref3*, %struct.localref4* } +%struct.ref3 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i32, i32, i32, i32, i32, i32, %struct.const1*, i8* } +%struct.ref4 = type { void (%struct.ref2*)*, [5 x void (%struct.ref2*, %struct.ref3*, i16*, i8**, i32)*] } + +%struct.localref1 = type { void (%struct.ref2*)*, i8 (%struct.ref2*, [64 x i16]**)*, i8 } +%struct.localref2 = type { void (%struct.ref2*)*, void (%struct.ref2*, i8***, i32*, i32, i8**, i32*, i32)*, i8 } +%struct.localref3 = type { void (%struct.ref2*)*, void (%struct.ref2*, i8***, i32, i8**, i32)* } +%struct.localref4 = type { {}*, void (%struct.ref2*, i8**, i8**, i32)*, void (%struct.ref2*)*, void (%struct.ref2*)* } +%struct.localref5 = type { void (%struct.ref2*)*, i32 (%struct.ref2*)*, i8 (%struct.ref2*)*, i8, i8, i32, i32 } +%struct.localref6 = type { i32 (%struct.ref2*)*, void (%struct.ref2*)*, void (%struct.ref2*)*, void (%struct.ref2*)*, i8, i8 } +%struct.localref7 = type { void (%struct.ref2*, i32)*, void (%struct.ref2*, i8***, i32*, i32, i8**, i32*, i32)* } +%struct.localref8 = type { void (%struct.ref2*)*, void (%struct.ref2*)*, i8 } +%struct.localref9 = type { void (%struct.ref2*, i32)*, void (%struct.ref2*, i8**, i32*, i32)* } +%struct.localref10 = type { %struct.localref10*, i8, i32, i32, i8* } +%struct.localref11 = type { i8*, %struct.targettype, void (%struct.ref2*)*, i8 (%struct.ref2*)*, void (%struct.ref2*, %struct.targettype)*, i8 (%struct.ref2*, i32)*, void (%struct.ref2*)* } +%struct.localref12 = type { {}*, %struct.targettype, %struct.targettype, i32, i32 } +%struct.localref13 = type { void (%struct.localref14*)*, void (%struct.localref14*, i32)*, void (%struct.localref14*)*, void (%struct.localref14*, i8*)*, void (%struct.localref14*)*, i32, %union.anon, i32, %struct.targettype, i8**, i32, i8**, i32, i32 } +%struct.localref14 = type { %struct.localref13*, %struct.localref15*, %struct.localref12*, i8*, i8, i32 } +%struct.localref15 = type { i8* (%struct.localref14*, i32, %struct.targettype)*, i8* (%struct.localref14*, i32, %struct.targettype)*, i8** (%struct.localref14*, i32, i32, i32)*, [64 x i16]** (%struct.localref14*, i32, i32, i32)*, %struct.op_ptr1* (%struct.localref14*, i32, i8, i32, i32, i32)*, %struct.op_ptr2* (%struct.localref14*, i32, i8, i32, i32, i32)*, {}*, i8** (%struct.localref14*, %struct.op_ptr1*, i32, i32, i8)*, [64 x i16]** (%struct.localref14*, %struct.op_ptr2*, i32, i32, i8)*, void (%struct.localref14*, i32)*, {}*, %struct.targettype, %struct.targettype} + +define internal i32 @foldedreload(%struct.ref2* %cinfo, i8*** nocapture %output1) { + %1 = getelementptr inbounds %struct.ref2* %cinfo, i32 0, i32 79 + %2 = load %struct.ref1** %1, align 4 + %3 = getelementptr inbounds %struct.ref2* %cinfo, i32 0, i32 68 + %4 = load i32* %3, align 4 + %5 = add i32 %4, -1 + %6 = getelementptr inbounds %struct.ref2* %cinfo, i32 0, i32 64 + %7 = load i32* %6, align 4 + %8 = add i32 %7, -1 + %9 = getelementptr inbounds %struct.ref1* %2, i32 1, i32 1 + %10 = bitcast i32 (%struct.ref2*)** %9 to i32* + %11 = load i32* %10, align 4 + %12 = getelementptr inbounds %struct.ref1* %2, i32 1, i32 2 + %13 = bitcast void (%struct.ref2*)** %12 to i32* + %14 = load i32* %13, align 4 + %15 = icmp slt i32 %11, %14 + br i1 %15, label %.lr.ph18, label %._crit_edge19 + +.lr.ph18: + %16 = getelementptr inbounds %struct.ref1* %2, i32 1 + %17 = bitcast %struct.ref1* %16 to i32* + %18 = getelementptr inbounds %struct.ref1* %16, i32 0, i32 0 + %19 = getelementptr inbounds %struct.ref2* %cinfo, i32 0, i32 66 + %20 = getelementptr inbounds %struct.ref2* %cinfo, i32 0, i32 84 + %21 = getelementptr inbounds %struct.ref2* %cinfo, i32 0, i32 36 + %22 = getelementptr inbounds %struct.ref1* %2, i32 1, i32 3 + %23 = bitcast i32 (%struct.ref2*, i8***)** %22 to [10 x [64 x i16]*]* + %.pre = load i32* %17, align 4 + br label %24 + +; <label>:24 + %25 = phi i32 [ %14, %.lr.ph18 ], [ %89, %88 ] + %26 = phi i32 [ %.pre, %.lr.ph18 ], [ 0, %88 ] + %var1.015 = phi i32 [ %11, %.lr.ph18 ], [ %90, %88 ] + %27 = icmp ugt i32 %26, %5 + br i1 %27, label %88, label %.preheader7.lr.ph + +.preheader7.lr.ph: + %.pre24 = load i32* %19, align 4 + br label %.preheader7 + +.preheader7: + %28 = phi i32 [ %.pre24, %.preheader7.lr.ph ], [ %85, %._crit_edge11 ] + %var2.012 = phi i32 [ %26, %.preheader7.lr.ph ], [ %86, %._crit_edge11 ] + %29 = icmp sgt i32 %28, 0 + br i1 %29, label %.lr.ph10, label %._crit_edge11 + +.lr.ph10: + %30 = phi i32 [ %28, %.preheader7 ], [ %82, %81 ] + %var4.09 = phi i32 [ 0, %.preheader7 ], [ %var4.1.lcssa, %81 ] + %ci.08 = phi i32 [ 0, %.preheader7 ], [ %83, %81 ] + %31 = getelementptr inbounds %struct.ref2* %cinfo, i32 0, i32 67, i32 %ci.08 + %32 = load %struct.ref3** %31, align 4 + %33 = getelementptr inbounds %struct.ref3* %32, i32 0, i32 1 + %34 = load i32* %33, align 4 + %35 = load %struct.ref4** %20, align 4 + %36 = getelementptr inbounds %struct.ref4* %35, i32 0, i32 1, i32 %34 + %37 = load void (%struct.ref2*, %struct.ref3*, i16*, i8**, i32)** %36, align 4 + %38 = getelementptr inbounds %struct.ref3* %32, i32 0, i32 17 + %39 = load i32* %38, align 4 + %40 = getelementptr inbounds %struct.ref3* %32, i32 0, i32 9 + %41 = load i32* %40, align 4 + %42 = getelementptr inbounds %struct.ref3* %32, i32 0, i32 16 + %43 = load i32* %42, align 4 + %44 = mul i32 %43, %var2.012 + %45 = getelementptr inbounds %struct.ref3* %32, i32 0, i32 14 + %46 = load i32* %45, align 4 + %47 = icmp sgt i32 %46, 0 + br i1 %47, label %.lr.ph6, label %81 + +.lr.ph6: + %48 = getelementptr inbounds i8*** %output1, i32 %34 + %49 = mul nsw i32 %41, %var1.015 + %50 = load i8*** %48, align 4 + %51 = getelementptr inbounds i8** %50, i32 %49 + %52 = getelementptr inbounds %struct.ref3* %32, i32 0, i32 13 + %53 = getelementptr inbounds %struct.ref3* %32, i32 0, i32 18 + %54 = icmp sgt i32 %39, 0 + br i1 %54, label %.lr.ph6.split.us, label %.lr.ph6..lr.ph6.split_crit_edge + +.lr.ph6..lr.ph6.split_crit_edge: + br label %._crit_edge26 + +.lr.ph6.split.us: + %55 = phi i32 [ %63, %._crit_edge28 ], [ %46, %.lr.ph6 ] + %56 = phi i32 [ %64, %._crit_edge28 ], [ %41, %.lr.ph6 ] + %var4.15.us = phi i32 [ %66, %._crit_edge28 ], [ %var4.09, %.lr.ph6 ] + %output2.04.us = phi i8** [ %69, %._crit_edge28 ], [ %51, %.lr.ph6 ] + %var5.03.us = phi i32 [ %67, %._crit_edge28 ], [ 0, %.lr.ph6 ] + %57 = load i32* %21, align 4 + %58 = icmp ult i32 %57, %8 + br i1 %58, label %.lr.ph.us, label %59 + +; <label>:59 + %60 = add nsw i32 %var5.03.us, %var1.015 + %61 = load i32* %53, align 4 + %62 = icmp slt i32 %60, %61 + br i1 %62, label %.lr.ph.us, label %._crit_edge27 + +._crit_edge27: + %63 = phi i32 [ %.pre23.pre, %.loopexit.us ], [ %55, %59 ] + %64 = phi i32 [ %74, %.loopexit.us ], [ %56, %59 ] + %65 = load i32* %52, align 4 + %66 = add nsw i32 %65, %var4.15.us + %67 = add nsw i32 %var5.03.us, 1 + %68 = icmp slt i32 %67, %63 + br i1 %68, label %._crit_edge28, label %._crit_edge + +._crit_edge28: + %69 = getelementptr inbounds i8** %output2.04.us, i32 %64 + br label %.lr.ph6.split.us + +.lr.ph.us: + %var3.02.us = phi i32 [ %75, %.lr.ph.us ], [ %44, %.lr.ph6.split.us ], [ %44, %59 ] + %xindex.01.us = phi i32 [ %76, %.lr.ph.us ], [ 0, %.lr.ph6.split.us ], [ 0, %59 ] + %70 = add nsw i32 %xindex.01.us, %var4.15.us + %71 = getelementptr inbounds [10 x [64 x i16]*]* %23, i32 0, i32 %70 + %72 = load [64 x i16]** %71, align 4 + %73 = getelementptr inbounds [64 x i16]* %72, i32 0, i32 0 + tail call void %37(%struct.ref2* %cinfo, %struct.ref3* %32, i16* %73, i8** %output2.04.us, i32 %var3.02.us) nounwind + %74 = load i32* %40, align 4 + %75 = add i32 %74, %var3.02.us + %76 = add nsw i32 %xindex.01.us, 1 + %exitcond = icmp eq i32 %76, %39 + br i1 %exitcond, label %.loopexit.us, label %.lr.ph.us + +.loopexit.us: + %.pre23.pre = load i32* %45, align 4 + br label %._crit_edge27 + +._crit_edge26: + %var4.15 = phi i32 [ %var4.09, %.lr.ph6..lr.ph6.split_crit_edge ], [ %78, %._crit_edge26 ] + %var5.03 = phi i32 [ 0, %.lr.ph6..lr.ph6.split_crit_edge ], [ %79, %._crit_edge26 ] + %77 = load i32* %52, align 4 + %78 = add nsw i32 %77, %var4.15 + %79 = add nsw i32 %var5.03, 1 + %80 = icmp slt i32 %79, %46 + br i1 %80, label %._crit_edge26, label %._crit_edge + +._crit_edge: + %split = phi i32 [ %66, %._crit_edge27 ], [ %78, %._crit_edge26 ] + %.pre25 = load i32* %19, align 4 + br label %81 + +; <label>:81 + %82 = phi i32 [ %.pre25, %._crit_edge ], [ %30, %.lr.ph10 ] + %var4.1.lcssa = phi i32 [ %split, %._crit_edge ], [ %var4.09, %.lr.ph10 ] + %83 = add nsw i32 %ci.08, 1 + %84 = icmp slt i32 %83, %82 + br i1 %84, label %.lr.ph10, label %._crit_edge11 + +._crit_edge11: + %85 = phi i32 [ %28, %.preheader7 ], [ %82, %81 ] + %86 = add i32 %var2.012, 1 + %87 = icmp ugt i32 %86, %5 + br i1 %87, label %._crit_edge14, label %.preheader7 + +._crit_edge14: + %.pre21 = load i32* %13, align 4 + br label %88 + +; <label>:88 + %89 = phi i32 [ %.pre21, %._crit_edge14 ], [ %25, %24 ] + store void (%struct.ref2*)* null, void (%struct.ref2*)** %18, align 4 + %90 = add nsw i32 %var1.015, 1 + %91 = icmp slt i32 %90, %89 + br i1 %91, label %24, label %._crit_edge19 + +._crit_edge19: + ret i32 3 +} diff --git a/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll new file mode 100644 index 0000000000..a7f249aae3 --- /dev/null +++ b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll @@ -0,0 +1,213 @@ +; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=atom 2>&1 | \ +; RUN: grep "callq" | not grep "(" +; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=core2 2>&1 | \ +; RUN: grep "callq" | grep "8-byte Folded Reload" + +%struct.targettype = type {i64} +%struct.op_ptr1 = type opaque +%struct.op_ptr2 = type opaque +%union.anon = type { [8 x i32], [48 x i8] } +%struct.const1 = type { [64 x i16], i8 } +%struct.const2 = type { [17 x i8], [256 x i8], i8 } +%struct.coef1 = type { %struct.ref1, i32, i32, i32, [10 x [64 x i16]*] } + +%struct.ref1 = type { void (%struct.ref2*)*, i32 (%struct.ref2*)*, void (%struct.ref2*)*, i32 (%struct.ref2*, i8***)*, %struct.op_ptr2** } +%struct.ref2 = type { %struct.localref13*, %struct.localref15*, %struct.localref12*, i8*, i8, i32, %struct.localref11*, i32, i32, i32, i32, i32, i32, i32, double, i8, i8, i32, i8, i8, i8, i32, i8, i32, i8, i8, i8, i32, i32, i32, i32, i32, i32, i8**, i32, i32, i32, i32, i32, [64 x i32]*, [4 x %struct.const1*], [4 x %struct.const2*], [4 x %struct.const2*], i32, %struct.ref3*, i8, i8, [16 x i8], [16 x i8], [16 x i8], i32, i8, i8, i8, i8, i16, i16, i8, i8, i8, %struct.localref10*, i32, i32, i32, i32, i8*, i32, [4 x %struct.ref3*], i32, i32, i32, [10 x i32], i32, i32, i32, i32, i32, %struct.localref8*, %struct.localref9*, %struct.ref1*, %struct.localref7*, %struct.localref6*, %struct.localref5*, %struct.localref1*, %struct.ref4*, %struct.localref2*, %struct.localref3*, %struct.localref4* } +%struct.ref3 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i32, i32, i32, i32, i32, i32, %struct.const1*, i8* } +%struct.ref4 = type { void (%struct.ref2*)*, [5 x void (%struct.ref2*, %struct.ref3*, i16*, i8**, i32)*] } + +%struct.localref1 = type { void (%struct.ref2*)*, i8 (%struct.ref2*, [64 x i16]**)*, i8 } +%struct.localref2 = type { void (%struct.ref2*)*, void (%struct.ref2*, i8***, i32*, i32, i8**, i32*, i32)*, i8 } +%struct.localref3 = type { void (%struct.ref2*)*, void (%struct.ref2*, i8***, i32, i8**, i32)* } +%struct.localref4 = type { {}*, void (%struct.ref2*, i8**, i8**, i32)*, void (%struct.ref2*)*, void (%struct.ref2*)* } +%struct.localref5 = type { void (%struct.ref2*)*, i32 (%struct.ref2*)*, i8 (%struct.ref2*)*, i8, i8, i32, i32 } +%struct.localref6 = type { i32 (%struct.ref2*)*, void (%struct.ref2*)*, void (%struct.ref2*)*, void (%struct.ref2*)*, i8, i8 } +%struct.localref7 = type { void (%struct.ref2*, i32)*, void (%struct.ref2*, i8***, i32*, i32, i8**, i32*, i32)* } +%struct.localref8 = type { void (%struct.ref2*)*, void (%struct.ref2*)*, i8 } +%struct.localref9 = type { void (%struct.ref2*, i32)*, void (%struct.ref2*, i8**, i32*, i32)* } +%struct.localref10 = type { %struct.localref10*, i8, i32, i32, i8* } +%struct.localref11 = type { i8*, %struct.targettype, void (%struct.ref2*)*, i8 (%struct.ref2*)*, void (%struct.ref2*, %struct.targettype)*, i8 (%struct.ref2*, i32)*, void (%struct.ref2*)* } +%struct.localref12 = type { {}*, %struct.targettype, %struct.targettype, i32, i32 } +%struct.localref13 = type { void (%struct.localref14*)*, void (%struct.localref14*, i32)*, void (%struct.localref14*)*, void (%struct.localref14*, i8*)*, void (%struct.localref14*)*, i32, %union.anon, i32, %struct.targettype, i8**, i32, i8**, i32, i32 } +%struct.localref14 = type { %struct.localref13*, %struct.localref15*, %struct.localref12*, i8*, i8, i32 } +%struct.localref15 = type { i8* (%struct.localref14*, i32, %struct.targettype)*, i8* (%struct.localref14*, i32, %struct.targettype)*, i8** (%struct.localref14*, i32, i32, i32)*, [64 x i16]** (%struct.localref14*, i32, i32, i32)*, %struct.op_ptr1* (%struct.localref14*, i32, i8, i32, i32, i32)*, %struct.op_ptr2* (%struct.localref14*, i32, i8, i32, i32, i32)*, {}*, i8** (%struct.localref14*, %struct.op_ptr1*, i32, i32, i8)*, [64 x i16]** (%struct.localref14*, %struct.op_ptr2*, i32, i32, i8)*, void (%struct.localref14*, i32)*, {}*, %struct.targettype, %struct.targettype} + +define internal i32 @foldedreload(%struct.ref2* %cinfo, i8*** nocapture %output1) { + %1 = getelementptr inbounds %struct.ref2* %cinfo, i64 0, i32 79 + %2 = load %struct.ref1** %1, align 8 + %3 = bitcast %struct.ref1* %2 to %struct.coef1* + %4 = getelementptr inbounds %struct.ref2* %cinfo, i64 0, i32 68 + %5 = load i32* %4, align 4 + %6 = add i32 %5, -1 + %7 = getelementptr inbounds %struct.ref2* %cinfo, i64 0, i32 64 + %8 = load i32* %7, align 4 + %9 = add i32 %8, -1 + %10 = getelementptr inbounds %struct.coef1* %3, i64 0, i32 2 + %11 = load i32* %10, align 4 + %12 = getelementptr inbounds %struct.ref1* %2, i64 1, i32 1 + %13 = bitcast i32 (%struct.ref2*)** %12 to i32* + %14 = load i32* %13, align 4 + %15 = icmp slt i32 %11, %14 + br i1 %15, label %.lr.ph18, label %._crit_edge19 + +.lr.ph18: + %16 = getelementptr inbounds %struct.ref1* %2, i64 1 + %17 = bitcast %struct.ref1* %16 to i32* + %18 = getelementptr inbounds %struct.ref2* %cinfo, i64 0, i32 66 + %19 = getelementptr inbounds %struct.ref2* %cinfo, i64 0, i32 84 + %20 = getelementptr inbounds %struct.ref2* %cinfo, i64 0, i32 36 + %21 = getelementptr inbounds %struct.ref1* %2, i64 1, i32 2 + %22 = bitcast void (%struct.ref2*)** %21 to [10 x [64 x i16]*]* + %.pre = load i32* %17, align 4 + br label %23 + +; <label>:23 + %24 = phi i32 [ %14, %.lr.ph18 ], [ %92, %91 ] + %25 = phi i32 [ %.pre, %.lr.ph18 ], [ 0, %91 ] + %var1.015 = phi i32 [ %11, %.lr.ph18 ], [ %93, %91 ] + %26 = icmp ugt i32 %25, %6 + br i1 %26, label %91, label %.preheader7.lr.ph + +.preheader7.lr.ph: + %.pre24 = load i32* %18, align 4 + br label %.preheader7 + +.preheader7: + %27 = phi i32 [ %.pre24, %.preheader7.lr.ph ], [ %88, %._crit_edge11 ] + %var2.012 = phi i32 [ %25, %.preheader7.lr.ph ], [ %89, %._crit_edge11 ] + %28 = icmp sgt i32 %27, 0 + br i1 %28, label %.lr.ph10, label %._crit_edge11 + +.lr.ph10: + %29 = phi i32 [ %27, %.preheader7 ], [ %85, %84 ] + %indvars.iv21 = phi i64 [ 0, %.preheader7 ], [ %indvars.iv.next22, %84 ] + %var4.09 = phi i32 [ 0, %.preheader7 ], [ %var4.1.lcssa, %84 ] + %30 = getelementptr inbounds %struct.ref2* %cinfo, i64 0, i32 67, i64 %indvars.iv21 + %31 = load %struct.ref3** %30, align 8 + %32 = getelementptr inbounds %struct.ref3* %31, i64 0, i32 1 + %33 = load i32* %32, align 4 + %34 = sext i32 %33 to i64 + %35 = load %struct.ref4** %19, align 8 + %36 = getelementptr inbounds %struct.ref4* %35, i64 0, i32 1, i64 %34 + %37 = load void (%struct.ref2*, %struct.ref3*, i16*, i8**, i32)** %36, align 8 + %38 = getelementptr inbounds %struct.ref3* %31, i64 0, i32 17 + %39 = load i32* %38, align 4 + %40 = getelementptr inbounds %struct.ref3* %31, i64 0, i32 9 + %41 = load i32* %40, align 4 + %42 = getelementptr inbounds %struct.ref3* %31, i64 0, i32 16 + %43 = load i32* %42, align 4 + %44 = mul i32 %43, %var2.012 + %45 = getelementptr inbounds %struct.ref3* %31, i64 0, i32 14 + %46 = load i32* %45, align 4 + %47 = icmp sgt i32 %46, 0 + br i1 %47, label %.lr.ph6, label %84 + +.lr.ph6: + %48 = mul nsw i32 %41, %var1.015 + %49 = getelementptr inbounds i8*** %output1, i64 %34 + %50 = sext i32 %48 to i64 + %51 = load i8*** %49, align 8 + %52 = getelementptr inbounds i8** %51, i64 %50 + %53 = getelementptr inbounds %struct.ref3* %31, i64 0, i32 13 + %54 = getelementptr inbounds %struct.ref3* %31, i64 0, i32 18 + %55 = icmp sgt i32 %39, 0 + br i1 %55, label %.lr.ph6.split.us, label %.lr.ph6..lr.ph6.split_crit_edge + +.lr.ph6..lr.ph6.split_crit_edge: + br label %._crit_edge28 + +.lr.ph6.split.us: + %56 = phi i32 [ %64, %._crit_edge30 ], [ %46, %.lr.ph6 ] + %57 = phi i32 [ %65, %._crit_edge30 ], [ %41, %.lr.ph6 ] + %var4.15.us = phi i32 [ %67, %._crit_edge30 ], [ %var4.09, %.lr.ph6 ] + %output2.04.us = phi i8** [ %71, %._crit_edge30 ], [ %52, %.lr.ph6 ] + %var5.03.us = phi i32 [ %68, %._crit_edge30 ], [ 0, %.lr.ph6 ] + %58 = load i32* %20, align 4 + %59 = icmp ult i32 %58, %9 + br i1 %59, label %.lr.ph.us, label %60 + +; <label>:60 + %61 = add nsw i32 %var5.03.us, %var1.015 + %62 = load i32* %54, align 4 + %63 = icmp slt i32 %61, %62 + br i1 %63, label %.lr.ph.us, label %._crit_edge29 + +._crit_edge29: + %64 = phi i32 [ %.pre25.pre, %.loopexit.us ], [ %56, %60 ] + %65 = phi i32 [ %77, %.loopexit.us ], [ %57, %60 ] + %66 = load i32* %53, align 4 + %67 = add nsw i32 %66, %var4.15.us + %68 = add nsw i32 %var5.03.us, 1 + %69 = icmp slt i32 %68, %64 + br i1 %69, label %._crit_edge30, label %._crit_edge + +._crit_edge30: + %70 = sext i32 %65 to i64 + %71 = getelementptr inbounds i8** %output2.04.us, i64 %70 + br label %.lr.ph6.split.us + +; <label>:72 + %indvars.iv = phi i64 [ 0, %.lr.ph.us ], [ %indvars.iv.next, %72 ] + %var3.02.us = phi i32 [ %44, %.lr.ph.us ], [ %78, %72 ] + %73 = add nsw i64 %indvars.iv, %79 + %74 = getelementptr inbounds [10 x [64 x i16]*]* %22, i64 0, i64 %73 + %75 = load [64 x i16]** %74, align 8 + %76 = getelementptr inbounds [64 x i16]* %75, i64 0, i64 0 + tail call void %37(%struct.ref2* %cinfo, %struct.ref3* %31, i16* %76, i8** %output2.04.us, i32 %var3.02.us) nounwind + %77 = load i32* %40, align 4 + %78 = add i32 %77, %var3.02.us + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %39 + br i1 %exitcond, label %.loopexit.us, label %72 + +.loopexit.us: + %.pre25.pre = load i32* %45, align 4 + br label %._crit_edge29 + +.lr.ph.us: + %79 = sext i32 %var4.15.us to i64 + br label %72 + +._crit_edge28: + %var4.15 = phi i32 [ %var4.09, %.lr.ph6..lr.ph6.split_crit_edge ], [ %81, %._crit_edge28 ] + %var5.03 = phi i32 [ 0, %.lr.ph6..lr.ph6.split_crit_edge ], [ %82, %._crit_edge28 ] + %80 = load i32* %53, align 4 + %81 = add nsw i32 %80, %var4.15 + %82 = add nsw i32 %var5.03, 1 + %83 = icmp slt i32 %82, %46 + br i1 %83, label %._crit_edge28, label %._crit_edge + +._crit_edge: + %split = phi i32 [ %67, %._crit_edge29 ], [ %81, %._crit_edge28 ] + %.pre27 = load i32* %18, align 4 + br label %84 + +; <label>:84 + %85 = phi i32 [ %.pre27, %._crit_edge ], [ %29, %.lr.ph10 ] + %var4.1.lcssa = phi i32 [ %split, %._crit_edge ], [ %var4.09, %.lr.ph10 ] + %indvars.iv.next22 = add i64 %indvars.iv21, 1 + %86 = trunc i64 %indvars.iv.next22 to i32 + %87 = icmp slt i32 %86, %85 + br i1 %87, label %.lr.ph10, label %._crit_edge11 + +._crit_edge11: + %88 = phi i32 [ %27, %.preheader7 ], [ %85, %84 ] + %89 = add i32 %var2.012, 1 + %90 = icmp ugt i32 %89, %6 + br i1 %90, label %._crit_edge14, label %.preheader7 + +._crit_edge14: + %.pre23 = load i32* %13, align 4 + br label %91 + +; <label>:91 + %92 = phi i32 [ %.pre23, %._crit_edge14 ], [ %24, %23 ] + store i32 0, i32* %17, align 4 + %93 = add nsw i32 %var1.015, 1 + %94 = icmp slt i32 %93, %92 + br i1 %94, label %23, label %._crit_edge19 + +._crit_edge19: + ret i32 3 +} diff --git a/test/CodeGen/X86/atom-call-reg-indirect.ll b/test/CodeGen/X86/atom-call-reg-indirect.ll new file mode 100644 index 0000000000..632781130d --- /dev/null +++ b/test/CodeGen/X86/atom-call-reg-indirect.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck -check-prefix=ATOM32 %s +; RUN: llc < %s -mcpu=core2 -mtriple=i686-linux | FileCheck -check-prefix=ATOM-NOT32 %s +; RUN: llc < %s -mcpu=atom -mtriple=x86_64-linux | FileCheck -check-prefix=ATOM64 %s +; RUN: llc < %s -mcpu=core2 -mtriple=x86_64-linux | FileCheck -check-prefix=ATOM-NOT64 %s + + +; fn_ptr.ll +%class.A = type { i32 (...)** } + +define i32 @test1() #0 { + ;ATOM: test1 +entry: + %call = tail call %class.A* @_Z3facv() + %0 = bitcast %class.A* %call to void (%class.A*)*** + %vtable = load void (%class.A*)*** %0, align 8 + %1 = load void (%class.A*)** %vtable, align 8 + ;ATOM32: movl (%ecx), %ecx + ;ATOM32: calll *%ecx + ;ATOM-NOT32: calll *(%ecx) + ;ATOM64: movq (%rcx), %rcx + ;ATOM64: callq *%rcx + ;ATOM-NOT64: callq *(%rcx) + tail call void %1(%class.A* %call) + ret i32 0 +} + +declare %class.A* @_Z3facv() #1 + +; virt_fn.ll +@p = external global void (i32)** + +define i32 @test2() #0 { + ;ATOM: test2 +entry: + %0 = load void (i32)*** @p, align 8 + %1 = load void (i32)** %0, align 8 + ;ATOM32: movl (%eax), %eax + ;ATOM32: calll *%eax + ;ATOM-NOT: calll *(%eax) + ;ATOM64: movq (%rax), %rax + ;ATOM64: callq *%rax + ;ATOM-NOT64: callq *(%rax) + tail call void %1(i32 2) + ret i32 0 +} diff --git a/test/CodeGen/X86/atomic32.ll b/test/CodeGen/X86/atomic32.ll index 3ea96bf169..080828702e 100644 --- a/test/CodeGen/X86/atomic32.ll +++ b/test/CodeGen/X86/atomic32.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X32 ; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 -mattr=-cmov -verify-machineinstrs | FileCheck %s --check-prefix NOCMOV -; XFAIL: cygwin,mingw32,win32 +; XFAIL: cygwin,mingw32 @sc32 = external global i32 diff --git a/test/CodeGen/X86/atomic64.ll b/test/CodeGen/X86/atomic64.ll index d362c31e6d..05939e8fc6 100644 --- a/test/CodeGen/X86/atomic64.ll +++ b/test/CodeGen/X86/atomic64.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -O0 -march=x86-64 -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X64 -; XFAIL: cygwin,mingw32,win32 +; XFAIL: cygwin,mingw32 @sc64 = external global i64 diff --git a/test/CodeGen/X86/avx-cvt.ll b/test/CodeGen/X86/avx-cvt.ll index 62bdea2b49..22fad7ce4b 100644 --- a/test/CodeGen/X86/avx-cvt.ll +++ b/test/CodeGen/X86/avx-cvt.ll @@ -18,6 +18,12 @@ define <4 x double> @sitofp01(<4 x i32> %a) { ret <4 x double> %b } +; CHECK: vcvtdq2ps %ymm +define <8 x float> @sitofp02(<8 x i16> %a) { + %b = sitofp <8 x i16> %a to <8 x float> + ret <8 x float> %b +} + ; CHECK: vcvttpd2dqy %ymm define <4 x i32> @fptosi01(<4 x double> %a) { %b = fptosi <4 x double> %a to <4 x i32> diff --git a/test/CodeGen/X86/avx-load-store.ll b/test/CodeGen/X86/avx-load-store.ll index 77a7c4f945..a6775aba09 100644 --- a/test/CodeGen/X86/avx-load-store.ll +++ b/test/CodeGen/X86/avx-load-store.ll @@ -55,7 +55,7 @@ define void @storev16i16(<16 x i16> %a) nounwind { ; CHECK: storev16i16_01 ; CHECK: vextractf128 -; CHECK: vmovaps %xmm +; CHECK: vmovups %xmm define void @storev16i16_01(<16 x i16> %a) nounwind { store <16 x i16> %a, <16 x i16>* undef, align 4 unreachable @@ -81,7 +81,7 @@ define void @storev32i8_01(<32 x i8> %a) nounwind { ; CHECK: _double_save ; CHECK-NOT: vinsertf128 $1 ; CHECK-NOT: vinsertf128 $0 -; CHECK: vmovups %xmm +; CHECK: vmovaps %xmm ; CHECK: vmovaps %xmm define void @double_save(<4 x i32> %A, <4 x i32> %B, <8 x i32>* %P) nounwind ssp { entry: @@ -114,3 +114,38 @@ cif_mixed_test_any_check: ; preds = %cif_mask_mixed unreachable } +; CHECK: add8i32 +; CHECK: vmovups +; CHECK: vmovups +; CHECK-NOT: vinsertf128 +; CHECK-NOT: vextractf128 +; CHECK: vmovups +; CHECK: vmovups +define void @add8i32(<8 x i32>* %ret, <8 x i32>* %bp) nounwind { + %b = load <8 x i32>* %bp, align 1 + %x = add <8 x i32> zeroinitializer, %b + store <8 x i32> %x, <8 x i32>* %ret, align 1 + ret void +} + +; CHECK: add4i64a64 +; CHECK: vmovaps ({{.*}}), %ymm{{.*}} +; CHECK: vmovaps %ymm{{.*}}, ({{.*}}) +define void @add4i64a64(<4 x i64>* %ret, <4 x i64>* %bp) nounwind { + %b = load <4 x i64>* %bp, align 64 + %x = add <4 x i64> zeroinitializer, %b + store <4 x i64> %x, <4 x i64>* %ret, align 64 + ret void +} + +; CHECK: add4i64a16 +; CHECK: vmovaps {{.*}}({{.*}}), %xmm{{.*}} +; CHECK: vmovaps {{.*}}({{.*}}), %xmm{{.*}} +; CHECK: vmovaps %xmm{{.*}}, {{.*}}({{.*}}) +; CHECK: vmovaps %xmm{{.*}}, {{.*}}({{.*}}) +define void @add4i64a16(<4 x i64>* %ret, <4 x i64>* %bp) nounwind { + %b = load <4 x i64>* %bp, align 16 + %x = add <4 x i64> zeroinitializer, %b + store <4 x i64> %x, <4 x i64>* %ret, align 16 + ret void +} diff --git a/test/CodeGen/X86/avx-sext.ll b/test/CodeGen/X86/avx-sext.ll index 7ae0d36c08..b9c7000510 100755 --- a/test/CodeGen/X86/avx-sext.ll +++ b/test/CodeGen/X86/avx-sext.ll @@ -165,3 +165,24 @@ define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) { ret <4 x i64> %extmask } +; AVX: sext_4i8_to_4i64 +; AVX: vpmovsxbd +; AVX: vpmovsxdq +; AVX: vpmovsxdq +; AVX: ret +define <4 x i64> @load_sext_4i8_to_4i64(<4 x i8> *%ptr) { + %X = load <4 x i8>* %ptr + %Y = sext <4 x i8> %X to <4 x i64> + ret <4 x i64>%Y +} + +; AVX: sext_4i16_to_4i64 +; AVX: vpmovsxwd +; AVX: vpmovsxdq +; AVX: vpmovsxdq +; AVX: ret +define <4 x i64> @load_sext_4i16_to_4i64(<4 x i16> *%ptr) { + %X = load <4 x i16>* %ptr + %Y = sext <4 x i16> %X to <4 x i64> + ret <4 x i64>%Y +} diff --git a/test/CodeGen/X86/bool-simplify.ll b/test/CodeGen/X86/bool-simplify.ll index 09eb5d1038..fa6f6e85e9 100644 --- a/test/CodeGen/X86/bool-simplify.ll +++ b/test/CodeGen/X86/bool-simplify.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx,+rdrand | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx,+rdrand,+rdseed | FileCheck %s define i32 @foo(<2 x i64> %c, i32 %a, i32 %b) { %t1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> %c) @@ -39,7 +39,22 @@ define i32 @bax(<2 x i64> %c) { ; CHECK: ret } -define i32 @rnd(i32 %arg) nounwind uwtable { +define i16 @rnd16(i16 %arg) nounwind uwtable { + %1 = tail call { i16, i32 } @llvm.x86.rdrand.16() nounwind + %2 = extractvalue { i16, i32 } %1, 0 + %3 = extractvalue { i16, i32 } %1, 1 + %4 = icmp eq i32 %3, 0 + %5 = select i1 %4, i16 0, i16 %arg + %6 = add i16 %5, %2 + ret i16 %6 +; CHECK: rnd16 +; CHECK: rdrand +; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: ret +} + +define i32 @rnd32(i32 %arg) nounwind uwtable { %1 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind %2 = extractvalue { i32, i32 } %1, 0 %3 = extractvalue { i32, i32 } %1, 1 @@ -47,12 +62,77 @@ define i32 @rnd(i32 %arg) nounwind uwtable { %5 = select i1 %4, i32 0, i32 %arg %6 = add i32 %5, %2 ret i32 %6 -; CHECK: rnd +; CHECK: rnd32 ; CHECK: rdrand ; CHECK: cmov ; CHECK-NOT: cmov ; CHECK: ret } +define i64 @rnd64(i64 %arg) nounwind uwtable { + %1 = tail call { i64, i32 } @llvm.x86.rdrand.64() nounwind + %2 = extractvalue { i64, i32 } %1, 0 + %3 = extractvalue { i64, i32 } %1, 1 + %4 = icmp eq i32 %3, 0 + %5 = select i1 %4, i64 0, i64 %arg + %6 = add i64 %5, %2 + ret i64 %6 +; CHECK: rnd64 +; CHECK: rdrand +; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: ret +} + +define i16 @seed16(i16 %arg) nounwind uwtable { + %1 = tail call { i16, i32 } @llvm.x86.rdseed.16() nounwind + %2 = extractvalue { i16, i32 } %1, 0 + %3 = extractvalue { i16, i32 } %1, 1 + %4 = icmp eq i32 %3, 0 + %5 = select i1 %4, i16 0, i16 %arg + %6 = add i16 %5, %2 + ret i16 %6 +; CHECK: seed16 +; CHECK: rdseed +; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: ret +} + +define i32 @seed32(i32 %arg) nounwind uwtable { + %1 = tail call { i32, i32 } @llvm.x86.rdseed.32() nounwind + %2 = extractvalue { i32, i32 } %1, 0 + %3 = extractvalue { i32, i32 } %1, 1 + %4 = icmp eq i32 %3, 0 + %5 = select i1 %4, i32 0, i32 %arg + %6 = add i32 %5, %2 + ret i32 %6 +; CHECK: seed32 +; CHECK: rdseed +; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: ret +} + +define i64 @seed64(i64 %arg) nounwind uwtable { + %1 = tail call { i64, i32 } @llvm.x86.rdseed.64() nounwind + %2 = extractvalue { i64, i32 } %1, 0 + %3 = extractvalue { i64, i32 } %1, 1 + %4 = icmp eq i32 %3, 0 + %5 = select i1 %4, i64 0, i64 %arg + %6 = add i64 %5, %2 + ret i64 %6 +; CHECK: seed64 +; CHECK: rdseed +; CHECK: cmov +; CHECK-NOT: cmov +; CHECK: ret +} + declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone +declare { i16, i32 } @llvm.x86.rdrand.16() nounwind declare { i32, i32 } @llvm.x86.rdrand.32() nounwind +declare { i64, i32 } @llvm.x86.rdrand.64() nounwind +declare { i16, i32 } @llvm.x86.rdseed.16() nounwind +declare { i32, i32 } @llvm.x86.rdseed.32() nounwind +declare { i64, i32 } @llvm.x86.rdseed.64() nounwind diff --git a/test/CodeGen/X86/complex-fca.ll b/test/CodeGen/X86/complex-fca.ll index 7e7acaa98a..8ad38a4ee5 100644 --- a/test/CodeGen/X86/complex-fca.ll +++ b/test/CodeGen/X86/complex-fca.ll @@ -1,5 +1,8 @@ ; RUN: llc < %s -march=x86 | grep mov | count 2 +; Skip this on Windows as there is no ccosl and sret behaves differently. +; XFAIL: pc-win32 + define void @ccosl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 } %z) nounwind { entry: %z8 = extractvalue { x86_fp80, x86_fp80 } %z, 0 diff --git a/test/CodeGen/X86/Stats/constant-pool-remat-0.ll b/test/CodeGen/X86/constant-pool-remat-0.ll index 4be14d2128..4a0110896c 100644 --- a/test/CodeGen/X86/Stats/constant-pool-remat-0.ll +++ b/test/CodeGen/X86/constant-pool-remat-0.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-linux -regalloc=greedy | FileCheck %s ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s diff --git a/test/CodeGen/X86/Stats/convert-2-addr-3-addr-inc64.ll b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll index 064ee364d1..74a7240c81 100644 --- a/test/CodeGen/X86/Stats/convert-2-addr-3-addr-inc64.ll +++ b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-linux -o /dev/null -stats 2>&1 | FileCheck %s -check-prefix=STATS ; RUN: llc < %s -mtriple=x86_64-win32 -o /dev/null -stats 2>&1 | FileCheck %s -check-prefix=STATS ; STATS: 9 asm-printer diff --git a/test/CodeGen/X86/Stats/dagcombine-cse.ll b/test/CodeGen/X86/dagcombine-cse.ll index af69531246..75d3d93ddb 100644 --- a/test/CodeGen/X86/Stats/dagcombine-cse.ll +++ b/test/CodeGen/X86/dagcombine-cse.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -stats 2>&1 | grep asm-printer | grep 14 define i32 @t(i8* %ref_frame_ptr, i32 %ref_frame_stride, i32 %idxX, i32 %idxY) nounwind { diff --git a/test/CodeGen/X86/dagcombine_unsafe_math.ll b/test/CodeGen/X86/dagcombine_unsafe_math.ll index a3221dea5b..592cf1bec2 100644 --- a/test/CodeGen/X86/dagcombine_unsafe_math.ll +++ b/test/CodeGen/X86/dagcombine_unsafe_math.ll @@ -40,3 +40,17 @@ define float @test4(float %x, float %y) { ; CHECK: test4 ; CHECK: vaddss } + +; rdar://13445387 +; "x + x + x => 3.0 * x" should be disabled after legalization because +; Instruction-Selection dosen't know how to handle "3.0" +; +define float @test5() { + %mul.i.i151 = fmul <4 x float> zeroinitializer, zeroinitializer + %vecext.i8.i152 = extractelement <4 x float> %mul.i.i151, i32 1 + %vecext1.i9.i153 = extractelement <4 x float> %mul.i.i151, i32 0 + %add.i10.i154 = fadd float %vecext1.i9.i153, %vecext.i8.i152 + %vecext.i7.i155 = extractelement <4 x float> %mul.i.i151, i32 2 + %add.i.i156 = fadd float %vecext.i7.i155, %add.i10.i154 + ret float %add.i.i156 +} diff --git a/test/CodeGen/X86/dbg-byval-parameter.ll b/test/CodeGen/X86/dbg-byval-parameter.ll index 25c946bbb6..aca06a27a1 100644 --- a/test/CodeGen/X86/dbg-byval-parameter.ll +++ b/test/CodeGen/X86/dbg-byval-parameter.ll @@ -26,23 +26,24 @@ return: ; preds = %entry declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!3} -!18 = metadata !{metadata !1} !0 = metadata !{i32 786689, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (%struct.Rect*)* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 786473, metadata !"b2.c", metadata !"/tmp/", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 0, i32 1, metadata !"b2.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !18, null} ; [ DW_TAG_compile_unit ] -!4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (%struct.Rect*)* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !18, null, metadata !""} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 786453, metadata !19, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6, metadata !7} -!6 = metadata !{i32 786468, metadata !2, metadata !"double", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] -!7 = metadata !{i32 786451, metadata !2, metadata !"Rect", metadata !2, i32 6, i64 256, i64 64, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_structure_type ] +!6 = metadata !{i32 786468, metadata !19, metadata !2, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 786451, metadata !19, metadata !2, metadata !"Rect", i32 6, i64 256, i64 64, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_structure_type ] !8 = metadata !{metadata !9, metadata !14} -!9 = metadata !{i32 786445, metadata !7, metadata !"P1", metadata !2, i32 7, i64 128, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] -!10 = metadata !{i32 786451, metadata !2, metadata !"Pt", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] +!9 = metadata !{i32 786445, metadata !19, metadata !7, metadata !"P1", i32 7, i64 128, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] +!10 = metadata !{i32 786451, metadata !19, metadata !2, metadata !"Pt", i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] !11 = metadata !{metadata !12, metadata !13} -!12 = metadata !{i32 786445, metadata !10, metadata !"x", metadata !2, i32 2, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] -!13 = metadata !{i32 786445, metadata !10, metadata !"y", metadata !2, i32 3, i64 64, i64 64, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] -!14 = metadata !{i32 786445, metadata !7, metadata !"P2", metadata !2, i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ] +!12 = metadata !{i32 786445, metadata !19, metadata !10, metadata !"x", i32 2, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!13 = metadata !{i32 786445, metadata !19, metadata !10, metadata !"y", i32 3, i64 64, i64 64, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] +!14 = metadata !{i32 786445, metadata !19, metadata !7, metadata !"P2", i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ] !15 = metadata !{i32 11, i32 0, metadata !1, null} !16 = metadata !{i32 12, i32 0, metadata !17, null} -!17 = metadata !{i32 786443, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ] +!17 = metadata !{i32 786443, metadata !2, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ] +!18 = metadata !{metadata !1} +!19 = metadata !{metadata !"b2.c", metadata !"/tmp/"} diff --git a/test/CodeGen/X86/dbg-const-int.ll b/test/CodeGen/X86/dbg-const-int.ll index 1f9c43ad9a..aabc206806 100644 --- a/test/CodeGen/X86/dbg-const-int.ll +++ b/test/CodeGen/X86/dbg-const-int.ll @@ -13,17 +13,18 @@ entry: declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!11 = metadata !{metadata !1} -!12 = metadata !{metadata !6} -!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"a.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 132191)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !11, null, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @foo, null, null, metadata !12, i32 0} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 786473, metadata !"a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] +!0 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 (trunk 132191)", i1 true, metadata !"", i32 0, null, null, metadata !11, null, null} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @foo, null, null, metadata !12, i32 0} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !13} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !6 = metadata !{i32 786688, metadata !7, metadata !"i", metadata !2, i32 2, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] -!7 = metadata !{i32 786443, metadata !1, i32 1, i32 11, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!7 = metadata !{i32 786443, metadata !2, metadata !1, i32 1, i32 11, i32 0} ; [ DW_TAG_lexical_block ] !8 = metadata !{i32 42} !9 = metadata !{i32 2, i32 12, metadata !7, null} !10 = metadata !{i32 3, i32 2, metadata !7, null} +!11 = metadata !{metadata !1} +!12 = metadata !{metadata !6} +!13 = metadata !{metadata !"a.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/dbg-const.ll b/test/CodeGen/X86/dbg-const.ll index cd60e533cc..a9b8f1fdc4 100644 --- a/test/CodeGen/X86/dbg-const.ll +++ b/test/CodeGen/X86/dbg-const.ll @@ -17,19 +17,20 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone declare i32 @bar() nounwind readnone !llvm.dbg.cu = !{!2} -!13 = metadata !{metadata !0} -!14 = metadata !{metadata !6} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"foobar", metadata !"foobar", metadata !"foobar", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @foobar, null, null, metadata !14, i32 0} -!1 = metadata !{i32 786473, metadata !"mu.c", metadata !"/private/tmp", metadata !2} -!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"mu.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 114183)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !13, null} +!0 = metadata !{i32 786478, metadata !1, metadata !"foobar", metadata !"foobar", metadata !"foobar", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @foobar, null, null, metadata !14, i32 0} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !15} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 114183)", i1 true, metadata !"", i32 0, null, null, metadata !13, null, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} !6 = metadata !{i32 786688, metadata !7, metadata !"j", metadata !1, i32 15, metadata !5, i32 0, null} -!7 = metadata !{i32 786443, metadata !0, i32 12, i32 52, metadata !1, i32 0} +!7 = metadata !{i32 786443, metadata !1, metadata !0, i32 12, i32 52, i32 0} ; [ DW_TAG_lexical_block ] !8 = metadata !{i32 42} !9 = metadata !{i32 15, i32 12, metadata !7, null} !10 = metadata !{i32 23, i32 3, metadata !7, null} !11 = metadata !{i32 17, i32 3, metadata !7, null} !12 = metadata !{i32 18, i32 3, metadata !7, null} +!13 = metadata !{metadata !0} +!14 = metadata !{metadata !6} +!15 = metadata !{metadata !"mu.c", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/dbg-declare-arg.ll b/test/CodeGen/X86/dbg-declare-arg.ll index 957f37bd87..f7e0c91cdf 100644 --- a/test/CodeGen/X86/dbg-declare-arg.ll +++ b/test/CodeGen/X86/dbg-declare-arg.ll @@ -70,34 +70,33 @@ entry: } !llvm.dbg.cu = !{!2} -!50 = metadata !{metadata !0, metadata !10, metadata !14, metadata !19, metadata !22, metadata !25} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"~A", metadata !"~A", metadata !"", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null} ; [ DW_TAG_subprogram ] +!0 = metadata !{i32 786478, metadata !"", i32 0, metadata !1, metadata !"~A", metadata !"~A", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 589826, metadata !2, metadata !"A", metadata !3, i32 2, i64 128, i64 32, i32 0, i32 0, null, metadata !4, i32 0, null, null} ; [ DW_TAG_class_type ] -!2 = metadata !{i32 786449, i32 0, i32 4, metadata !"a.cc", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 130127)", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !50, null, null} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 786473, metadata !"a.cc", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 4, metadata !3, metadata !"clang version 3.0 (trunk 130127)", i1 false, metadata !"", i32 0, null, null, metadata !50, null, null} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786473, metadata !51} ; [ DW_TAG_file_type ] !4 = metadata !{metadata !5, metadata !7, metadata !8, metadata !9, metadata !0, metadata !10, metadata !14} !5 = metadata !{i32 786445, metadata !3, metadata !"x", metadata !3, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] !6 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !7 = metadata !{i32 786445, metadata !3, metadata !"y", metadata !3, i32 2, i64 32, i64 32, i64 32, i32 0, metadata !6} ; [ DW_TAG_member ] !8 = metadata !{i32 786445, metadata !3, metadata !"z", metadata !3, i32 2, i64 32, i64 32, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] !9 = metadata !{i32 786445, metadata !3, metadata !"o", metadata !3, i32 2, i64 32, i64 32, i64 96, i32 0, metadata !6} ; [ DW_TAG_member ] -!10 = metadata !{i32 786478, i32 0, metadata !1, metadata !"A", metadata !"A", metadata !"", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 786478, metadata !"", i32 0, metadata !1, metadata !"A", metadata !"A", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ] !11 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !12 = metadata !{null, metadata !13} !13 = metadata !{i32 786447, metadata !2, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] -!14 = metadata !{i32 786478, i32 0, metadata !1, metadata !"A", metadata !"A", metadata !"", metadata !3, i32 2, metadata !15, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ] +!14 = metadata !{i32 786478, metadata !"", i32 0, metadata !1, metadata !"A", metadata !"A", metadata !3, i32 2, metadata !15, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ] !15 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !16, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !16 = metadata !{null, metadata !13, metadata !17} !17 = metadata !{i32 589840, metadata !2, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !18} ; [ DW_TAG_reference_type ] !18 = metadata !{i32 786470, metadata !2, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !1} ; [ DW_TAG_const_type ] -!19 = metadata !{i32 786478, i32 0, metadata !3, metadata !"foo", metadata !"foo", metadata !"_Z3fooi", metadata !3, i32 4, metadata !20, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*, i32)* @_Z3fooi, null, null} ; [ DW_TAG_subprogram ] +!19 = metadata !{i32 786478, metadata !"_Z3fooi", i32 0, metadata !3, metadata !"foo", metadata !"foo", metadata !3, i32 4, metadata !20, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*, i32)* @_Z3fooi, null, null} ; [ DW_TAG_subprogram ] !20 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !21, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !21 = metadata !{metadata !1} -!22 = metadata !{i32 786478, i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !"_ZN1AD1Ev", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD1Ev, null, null} ; [ DW_TAG_subprogram ] +!22 = metadata !{i32 786478, metadata !"_ZN1AD1Ev", i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD1Ev, null, null} ; [ DW_TAG_subprogram ] !23 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !24, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !24 = metadata !{null} -!25 = metadata !{i32 786478, i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !"_ZN1AD2Ev", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD2Ev, null, null} ; [ DW_TAG_subprogram ] +!25 = metadata !{i32 786478, metadata !"_ZN1AD2Ev", i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD2Ev, null, null} ; [ DW_TAG_subprogram ] !26 = metadata !{i32 786689, metadata !19, metadata !"i", metadata !3, i32 16777220, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] !27 = metadata !{i32 4, i32 11, metadata !19, null} !28 = metadata !{i32 786688, metadata !29, metadata !"j", metadata !3, i32 5, metadata !6, i32 0, null} ; [ DW_TAG_auto_variable ] @@ -122,3 +121,5 @@ entry: !47 = metadata !{i32 2, i32 47, metadata !25, null} !48 = metadata !{i32 2, i32 54, metadata !49, null} !49 = metadata !{i32 786443, metadata !25, i32 2, i32 52, metadata !3, i32 2} ; [ DW_TAG_lexical_block ] +!50 = metadata !{metadata !0, metadata !10, metadata !14, metadata !19, metadata !22, metadata !25} +!51 = metadata !{metadata !"a.cc", metadata !"/private/tmp"} diff --git a/test/CodeGen/X86/dbg-declare.ll b/test/CodeGen/X86/dbg-declare.ll index 9d13de16da..6ac397ac42 100644 --- a/test/CodeGen/X86/dbg-declare.ll +++ b/test/CodeGen/X86/dbg-declare.ll @@ -29,10 +29,10 @@ declare void @llvm.stackrestore(i8*) nounwind !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"20020104-2.c", metadata !"/Volumes/Sandbox/llvm", metadata !"clang version 3.1 (trunk 153698)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 153698)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} -!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"foo", metadata !"foo", metadata !"", metadata !6, i32 6, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32*)* @foo, null, null, metadata !12} ; [ DW_TAG_subprogram ] +!5 = metadata !{i32 786478, metadata !6, metadata !"foo", metadata !"foo", metadata !"", metadata !6, i32 6, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32*)* @foo, null, null, metadata !12} ; [ DW_TAG_subprogram ] !6 = metadata !{i32 786473, metadata !"20020104-2.c", metadata !"/Volumes/Sandbox/llvm", null} ; [ DW_TAG_file_type ] !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !8 = metadata !{metadata !9, metadata !10} diff --git a/test/CodeGen/X86/dbg-file-name.ll b/test/CodeGen/X86/dbg-file-name.ll index 0a526100e6..1bd3d77522 100644 --- a/test/CodeGen/X86/dbg-file-name.ll +++ b/test/CodeGen/X86/dbg-file-name.ll @@ -10,11 +10,12 @@ define i32 @main() nounwind { } !llvm.dbg.cu = !{!2} -!9 = metadata !{metadata !6} -!1 = metadata !{i32 786473, metadata !"simple.c", metadata !"/Users/manav/one/two", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 1, metadata !"simple.c", metadata !"/Users/manav/one/two", metadata !"LLVM build 00", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !9, null} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786473, metadata !10} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !10, i32 1, metadata !"LLVM build 00", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !9, null} ; [ DW_TAG_compile_unit ] !5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !6 = metadata !{i32 786478, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 9, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, null, i32 0} ; [ DW_TAG_subprogram ] !7 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_subroutine_type ] !8 = metadata !{metadata !5} +!9 = metadata !{metadata !6} +!10 = metadata !{metadata !"simple.c", metadata !"/Users/manav/one/two"} diff --git a/test/CodeGen/X86/dbg-i128-const.ll b/test/CodeGen/X86/dbg-i128-const.ll index 725b5b73d5..17d645757d 100644 --- a/test/CodeGen/X86/dbg-i128-const.ll +++ b/test/CodeGen/X86/dbg-i128-const.ll @@ -13,17 +13,19 @@ entry: declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!5} -!12 = metadata !{metadata !3} !0 = metadata !{i128 42 } !1 = metadata !{i32 786688, metadata !2, metadata !"MAX", metadata !4, i32 29, metadata !8, i32 0, null} ; [ DW_TAG_auto_variable ] -!2 = metadata !{i32 786443, metadata !3, i32 26, i32 0, metadata !4, i32 0} ; [ DW_TAG_lexical_block ] -!3 = metadata !{i32 786478, i32 0, metadata !4, metadata !"__foo", metadata !"__foo", metadata !"__foo", metadata !4, i32 26, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i128 (i128, i128)* @__foo, null, null, null, i32 26} ; [ DW_TAG_subprogram ] -!4 = metadata !{i32 786473, metadata !"foo.c", metadata !"/tmp", metadata !5} ; [ DW_TAG_file_type ] -!5 = metadata !{i32 786449, i32 0, i32 1, metadata !"foo.c", metadata !"/tmp", metadata !"clang", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !12, null} ; [ DW_TAG_compile_unit ] -!6 = metadata !{i32 786453, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] +!2 = metadata !{i32 786443, metadata !4, metadata !3, i32 26, i32 0, i32 0} ; [ DW_TAG_lexical_block ] +!3 = metadata !{i32 786478, metadata !4, metadata !"__foo", metadata !"__foo", metadata !"__foo", metadata !4, i32 26, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i128 (i128, i128)* @__foo, null, null, null, i32 26} ; [ DW_TAG_subprogram ] +!4 = metadata !{i32 786473, metadata !13} ; [ DW_TAG_file_type ] +!5 = metadata !{i32 786449, i32 1, metadata !4, metadata !"clang", i1 true, metadata !"", i32 0, null, null, metadata !12, null, metadata !""} ; [ DW_TAG_compile_unit ] +!6 = metadata !{i32 786453, metadata !13, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] !7 = metadata !{metadata !8, metadata !8, metadata !8} -!8 = metadata !{i32 786454, metadata !4, metadata !"ti_int", metadata !9, i32 78, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ] -!9 = metadata !{i32 786473, metadata !"myint.h", metadata !"/tmp", metadata !5} ; [ DW_TAG_file_type ] -!10 = metadata !{i32 786468, metadata !4, metadata !"", metadata !4, i32 0, i64 128, i64 128, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 786454, metadata !14, metadata !4, metadata !"ti_int", i32 78, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ] +!9 = metadata !{i32 786473, metadata !14} ; [ DW_TAG_file_type ] +!10 = metadata !{i32 786468, metadata !13, metadata !4, metadata !"", i32 0, i64 128, i64 128, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !11 = metadata !{i32 29, i32 0, metadata !2, null} +!12 = metadata !{metadata !3} +!13 = metadata !{metadata !"foo.c", metadata !"/tmp"} +!14 = metadata !{metadata !"myint.h", metadata !"/tmp"} diff --git a/test/CodeGen/X86/dbg-large-unsigned-const.ll b/test/CodeGen/X86/dbg-large-unsigned-const.ll index 9a767621d9..ff16318efc 100644 --- a/test/CodeGen/X86/dbg-large-unsigned-const.ll +++ b/test/CodeGen/X86/dbg-large-unsigned-const.ll @@ -30,13 +30,13 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !30 = metadata !{metadata !7, metadata !11} !31 = metadata !{metadata !12} -!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"lli.cc", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 135593)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !29, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"ise", metadata !"ise", metadata !"_Z3iseRKxS0_", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64*, i64*)* @_Z3iseRKxS0_, null, null, metadata !30, i32 2} ; [ DW_TAG_subprogram ] +!0 = metadata !{i32 786449, i32 4, metadata !2, metadata !"clang version 3.0 (trunk 135593)", i1 true, metadata !"", i32 0, null, null, metadata !29, null, metadata !""} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !"_Z3iseRKxS0_", i32 0, metadata !2, metadata !"ise", metadata !"ise", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64*, i64*)* @_Z3iseRKxS0_, null, null, metadata !30, i32 2} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !"lli.cc", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !0, metadata !"bool", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 786478, i32 0, metadata !2, metadata !"fn", metadata !"fn", metadata !"_Z2fnx", metadata !2, i32 6, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64)* @_Z2fnx, null, null, metadata !31, i32 6} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 786478, metadata !"_Z2fnx", i32 0, metadata !2, metadata !"fn", metadata !"fn", metadata !2, i32 6, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64)* @_Z2fnx, null, null, metadata !31, i32 6} ; [ DW_TAG_subprogram ] !7 = metadata !{i32 786689, metadata !1, metadata !"LHS", metadata !2, i32 16777218, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] !8 = metadata !{i32 786448, metadata !0, null, null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !9} ; [ DW_TAG_reference_type ] !9 = metadata !{i32 786470, metadata !0, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_const_type ] @@ -46,14 +46,14 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !13 = metadata !{i32 2, i32 27, metadata !1, null} !14 = metadata !{i32 2, i32 49, metadata !1, null} !15 = metadata !{i32 3, i32 3, metadata !16, null} -!16 = metadata !{i32 786443, metadata !1, i32 2, i32 54, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!16 = metadata !{i32 786443, metadata !2, metadata !1, i32 2, i32 54, i32 0} ; [ DW_TAG_lexical_block ] !17 = metadata !{metadata !"long long", metadata !18} !18 = metadata !{metadata !"omnipotent char", metadata !19} !19 = metadata !{metadata !"Simple C/C++ TBAA", null} !20 = metadata !{i32 6, i32 19, metadata !6, null} !21 = metadata !{i32 786689, metadata !1, metadata !"LHS", metadata !2, i32 16777218, metadata !8, i32 0, metadata !22} ; [ DW_TAG_arg_variable ] !22 = metadata !{i32 7, i32 10, metadata !23, null} -!23 = metadata !{i32 786443, metadata !6, i32 6, i32 22, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] +!23 = metadata !{i32 786443, metadata !2, metadata !6, i32 6, i32 22, i32 1} ; [ DW_TAG_lexical_block ] !24 = metadata !{i32 2, i32 27, metadata !1, metadata !22} !25 = metadata !{i64 9223372036854775807} !26 = metadata !{i32 786689, metadata !1, metadata !"RHS", metadata !2, i32 33554434, metadata !8, i32 0, metadata !22} ; [ DW_TAG_arg_variable ] diff --git a/test/CodeGen/X86/dbg-merge-loc-entry.ll b/test/CodeGen/X86/dbg-merge-loc-entry.ll index 4e5078a31b..baad6c0b60 100644 --- a/test/CodeGen/X86/dbg-merge-loc-entry.ll +++ b/test/CodeGen/X86/dbg-merge-loc-entry.ll @@ -44,33 +44,35 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone declare %0 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone !llvm.dbg.cu = !{!2} -!28 = metadata !{metadata !0, metadata !9} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"__udivmodti4", metadata !"__udivmodti4", metadata !"", metadata !1, i32 879, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, null, i32 879} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"foobar.c", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 1, metadata !"foobar.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !28, null} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"__udivmodti4", metadata !"__udivmodti4", metadata !"", metadata !1, i32 879, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, null, i32 879} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !29} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !28, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !29, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5, metadata !5, metadata !5, metadata !8} -!5 = metadata !{i32 786454, metadata !6, metadata !"UTItype", metadata !6, i32 166, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] -!6 = metadata !{i32 786473, metadata !"foobar.h", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ] -!7 = metadata !{i32 786468, metadata !1, metadata !"", metadata !1, i32 0, i64 128, i64 128, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!8 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_pointer_type ] -!9 = metadata !{i32 786478, i32 0, metadata !1, metadata !"__divti3", metadata !"__divti3", metadata !"__divti3", metadata !1, i32 1094, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i128 (i128, i128)* @__divti3, null, null, null, i32 1094} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{i32 786454, metadata !30, metadata !6, metadata !"UTItype", i32 166, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] +!6 = metadata !{i32 786473, metadata !30} ; [ DW_TAG_file_type ] +!7 = metadata !{i32 786468, metadata !29, metadata !1, metadata !"", i32 0, i64 128, i64 128, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 786447, metadata !29, metadata !1, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_pointer_type ] +!9 = metadata !{i32 786478, metadata !1, metadata !"__divti3", metadata !"__divti3", metadata !"__divti3", metadata !1, i32 1094, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i128 (i128, i128)* @__divti3, null, null, null, i32 1094} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 786453, metadata !29, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] !11 = metadata !{metadata !12, metadata !12, metadata !12} -!12 = metadata !{i32 786454, metadata !6, metadata !"TItype", metadata !6, i32 160, i64 0, i64 0, i64 0, i32 0, metadata !13} ; [ DW_TAG_typedef ] -!13 = metadata !{i32 786468, metadata !1, metadata !"", metadata !1, i32 0, i64 128, i64 128, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!12 = metadata !{i32 786454, metadata !30, metadata !6, metadata !"TItype", i32 160, i64 0, i64 0, i64 0, i32 0, metadata !13} ; [ DW_TAG_typedef ] +!13 = metadata !{i32 786468, metadata !29, metadata !1, metadata !"", i32 0, i64 128, i64 128, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !14 = metadata !{i32 786689, metadata !9, metadata !"u", metadata !1, i32 1093, metadata !12, i32 0, null} ; [ DW_TAG_arg_variable ] !15 = metadata !{i32 1093, i32 0, metadata !9, null} !16 = metadata !{i64 0} !17 = metadata !{i32 786688, metadata !18, metadata !"c", metadata !1, i32 1095, metadata !19, i32 0, null} ; [ DW_TAG_auto_variable ] -!18 = metadata !{i32 786443, metadata !9, i32 1094, i32 0, metadata !1, i32 13} ; [ DW_TAG_lexical_block ] -!19 = metadata !{i32 786454, metadata !6, metadata !"word_type", metadata !6, i32 424, i64 0, i64 0, i64 0, i32 0, metadata !20} ; [ DW_TAG_typedef ] -!20 = metadata !{i32 786468, metadata !1, metadata !"long int", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!18 = metadata !{i32 786443, metadata !1, metadata !9, i32 1094, i32 0, i32 13} ; [ DW_TAG_lexical_block ] +!19 = metadata !{i32 786454, metadata !30, metadata !6, metadata !"word_type", i32 424, i64 0, i64 0, i64 0, i32 0, metadata !20} ; [ DW_TAG_typedef ] +!20 = metadata !{i32 786468, metadata !29, metadata !1, metadata !"long int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !21 = metadata !{i32 1095, i32 0, metadata !18, null} !22 = metadata !{i32 1103, i32 0, metadata !18, null} !23 = metadata !{i32 1104, i32 0, metadata !18, null} !24 = metadata !{i32 1003, i32 0, metadata !25, metadata !26} -!25 = metadata !{i32 786443, metadata !0, i32 879, i32 0, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!25 = metadata !{i32 786443, metadata !1, metadata !0, i32 879, i32 0, i32 0} ; [ DW_TAG_lexical_block ] !26 = metadata !{i32 1107, i32 0, metadata !18, null} !27 = metadata !{i32 1111, i32 0, metadata !18, null} +!28 = metadata !{metadata !0, metadata !9} +!29 = metadata !{metadata !"foobar.c", metadata !"/tmp"} +!30 = metadata !{metadata !"foobar.h", metadata !"/tmp"} diff --git a/test/CodeGen/X86/dbg-prolog-end.ll b/test/CodeGen/X86/dbg-prolog-end.ll index 868017cd21..26bac2e082 100644 --- a/test/CodeGen/X86/dbg-prolog-end.ll +++ b/test/CodeGen/X86/dbg-prolog-end.ll @@ -35,21 +35,21 @@ entry: !llvm.dbg.cu = !{!0} !18 = metadata !{metadata !1, metadata !6} -!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"/tmp/a.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 131100)", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !18, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32)* @foo, null, null, null, i32 1} ; [ DW_TAG_subprogram ] +!0 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 (trunk 131100)", i1 false, metadata !"", i32 0, null, null, metadata !18, null, metadata !""} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32)* @foo, null, null, null, i32 1} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !"/tmp/a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 786478, i32 0, metadata !2, metadata !"main", metadata !"main", metadata !"", metadata !2, i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @main, null, null, null, i32 7} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 786478, metadata !2, metadata !"main", metadata !"main", metadata !"", metadata !2, i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @main, null, null, null, i32 7} ; [ DW_TAG_subprogram ] !7 = metadata !{i32 786689, metadata !1, metadata !"i", metadata !2, i32 16777217, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !8 = metadata !{i32 1, i32 13, metadata !1, null} !9 = metadata !{i32 786688, metadata !10, metadata !"j", metadata !2, i32 2, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] -!10 = metadata !{i32 786443, metadata !1, i32 1, i32 16, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 786443, metadata !2, metadata !1, i32 1, i32 16, i32 0} ; [ DW_TAG_lexical_block ] !11 = metadata !{i32 2, i32 6, metadata !10, null} !12 = metadata !{i32 2, i32 11, metadata !10, null} !13 = metadata !{i32 3, i32 2, metadata !10, null} !14 = metadata !{i32 4, i32 2, metadata !10, null} !15 = metadata !{i32 5, i32 2, metadata !10, null} !16 = metadata !{i32 8, i32 2, metadata !17, null} -!17 = metadata !{i32 786443, metadata !6, i32 7, i32 12, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] +!17 = metadata !{i32 786443, metadata !2, metadata !6, i32 7, i32 12, i32 1} ; [ DW_TAG_lexical_block ] diff --git a/test/CodeGen/X86/dbg-subrange.ll b/test/CodeGen/X86/dbg-subrange.ll index 2f590ee8cc..6090185dc1 100644 --- a/test/CodeGen/X86/dbg-subrange.ll +++ b/test/CodeGen/X86/dbg-subrange.ll @@ -14,10 +14,10 @@ entry: !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"small.c", metadata !"/private/tmp", metadata !"clang version 3.1 (trunk 144833)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !11} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 144833)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !11, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} -!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"bar", metadata !"bar", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @bar, null, null, metadata !9} ; [ DW_TAG_subprogram ] +!5 = metadata !{i32 720942, metadata !6, metadata !"bar", metadata !"bar", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @bar, null, null, metadata !9} ; [ DW_TAG_subprogram ] !6 = metadata !{i32 720937, metadata !"small.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ] !7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !8 = metadata !{null} diff --git a/test/CodeGen/X86/dbg-value-dag-combine.ll b/test/CodeGen/X86/dbg-value-dag-combine.ll index 0066cd0498..fcbf64f423 100644 --- a/test/CodeGen/X86/dbg-value-dag-combine.ll +++ b/test/CodeGen/X86/dbg-value-dag-combine.ll @@ -24,13 +24,10 @@ entry: ret void, !dbg !17 } !llvm.dbg.cu = !{!2} -!18 = metadata !{metadata !0} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata -!"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", metadata -!"__OpenCL_test_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"OCL6368.tmp.cl", metadata !"E:\5CUsers\5Cmvillmow.AMD\5CAppData\5CLocal\5CTemp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 1, metadata !"OCL6368.tmp.cl", metadata !"E:\5CUsers\5Cmvillmow.AMD\5CAppData\5CLocal\5CTemp", metadata !"clc", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !18, null, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786478, metadata !1, metadata !"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"clc", i1 false, metadata !"", i32 0, null, null, metadata !18, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{null, metadata !5} !5 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ] @@ -46,4 +43,5 @@ entry: !15 = metadata !{i32 5, i32 15, metadata !10, null} !16 = metadata !{i32 6, i32 18, metadata !10, null} !17 = metadata !{i32 7, i32 1, metadata !0, null} - +!18 = metadata !{metadata !0} +!19 = metadata !{metadata !"OCL6368.tmp.cl", metadata !"E:\5CUsers\5Cmvillmow.AMD\5CAppData\5CLocal\5CTemp"} diff --git a/test/CodeGen/X86/dbg-value-isel.ll b/test/CodeGen/X86/dbg-value-isel.ll index e0dc9a4798..55be3b1f22 100644 --- a/test/CodeGen/X86/dbg-value-isel.ll +++ b/test/CodeGen/X86/dbg-value-isel.ll @@ -79,16 +79,15 @@ declare <4 x i32> @__amdil_get_global_id_int() nounwind declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!2} -!19 = metadata !{metadata !0} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"OCLlLwTXZ.cl", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 1, metadata !"OCLlLwTXZ.cl", metadata !"/tmp", metadata !"clc", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !19, null, null} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = metadata !{i32 786478, metadata !1, metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !20, i32 1, metadata !"clc", i1 false, metadata !"", i32 0, null, null, metadata !19, null, null} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786453, metadata !20, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{null, metadata !5} -!5 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ] -!6 = metadata !{i32 589846, metadata !2, metadata !"uint", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] -!7 = metadata !{i32 786468, metadata !2, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!5 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ] +!6 = metadata !{i32 589846, metadata !20, metadata !2, metadata !"uint", i32 0, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] +!7 = metadata !{i32 786468, null, metadata !2, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] !8 = metadata !{i32 786689, metadata !0, metadata !"ip", metadata !1, i32 1, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !9 = metadata !{i32 1, i32 32, metadata !0, null} !10 = metadata !{i32 786688, metadata !11, metadata !"tid", metadata !1, i32 3, metadata !6, i32 0, null} ; [ DW_TAG_auto_variable ] @@ -100,4 +99,5 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !16 = metadata !{i32 7, i32 26, metadata !11, null} !17 = metadata !{i32 9, i32 24, metadata !11, null} !18 = metadata !{i32 10, i32 1, metadata !0, null} - +!19 = metadata !{metadata !0} +!20 = metadata !{metadata !"OCLlLwTXZ.cl", metadata !"/tmp"} diff --git a/test/CodeGen/X86/dbg-value-location.ll b/test/CodeGen/X86/dbg-value-location.ll index 5ad8370618..2a1916f26c 100644 --- a/test/CodeGen/X86/dbg-value-location.ll +++ b/test/CodeGen/X86/dbg-value-location.ll @@ -46,26 +46,29 @@ declare hidden fastcc i32 @bar3(i32) nounwind optsize ssp declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!2} -!24 = metadata !{metadata !0, metadata !6, metadata !7, metadata !8} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 19510, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i64, i8*, i32)* @foo, null, null, null, i32 19510} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"/tmp/f.c", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"f.i", metadata !"/tmp", metadata !"clang version 2.9 (trunk 124753)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !24, null, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 19510, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i64, i8*, i32)* @foo, null, null, null, i32 19510} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !26} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !27, i32 12, metadata !"clang version 2.9 (trunk 124753)", i1 true, metadata !"", i32 0, null, null, metadata !24, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 786478, i32 0, metadata !1, metadata !"bar3", metadata !"bar3", metadata !"", metadata !1, i32 14827, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @bar3} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 786478, i32 0, metadata !1, metadata !"bar2", metadata !"bar2", metadata !"", metadata !1, i32 15397, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @bar2} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 786478, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"", metadata !1, i32 12382, metadata !9, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @bar} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"bar3", metadata !"bar3", metadata !"", i32 14827, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @bar3} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"bar2", metadata !"bar2", metadata !"", i32 15397, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @bar2} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"bar", metadata !"bar", metadata !"", i32 12382, metadata !9, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @bar} ; [ DW_TAG_subprogram ] !9 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !10, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !10 = metadata !{metadata !11} !11 = metadata !{i32 786468, metadata !2, metadata !"unsigned char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] !12 = metadata !{i32 786689, metadata !0, metadata !"var", metadata !1, i32 19509, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !13 = metadata !{i32 19509, i32 20, metadata !0, null} !14 = metadata !{i32 18091, i32 2, metadata !15, metadata !17} -!15 = metadata !{i32 786443, metadata !16, i32 18086, i32 1, metadata !1, i32 748} ; [ DW_TAG_lexical_block ] -!16 = metadata !{i32 786478, i32 0, metadata !1, metadata !"foo_bar", metadata !"foo_bar", metadata !"", metadata !1, i32 18086, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 786443, metadata !1, metadata !16, i32 18086, i32 1, i32 748} ; [ DW_TAG_lexical_block ] +!16 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"foo_bar", metadata !"foo_bar", metadata !"", i32 18086, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null} ; [ DW_TAG_subprogram ] !17 = metadata !{i32 19514, i32 2, metadata !18, null} -!18 = metadata !{i32 786443, metadata !0, i32 19510, i32 1, metadata !1, i32 99} ; [ DW_TAG_lexical_block ] +!18 = metadata !{i32 786443, metadata !1, metadata !0, i32 19510, i32 1, i32 99} ; [ DW_TAG_lexical_block ] !22 = metadata !{i32 18094, i32 2, metadata !15, metadata !17} !23 = metadata !{i32 19524, i32 1, metadata !18, null} +!24 = metadata !{metadata !0, metadata !6, metadata !7, metadata !8} +!25 = metadata !{i32 786473, metadata !27} ; [ DW_TAG_file_type ] +!26 = metadata !{metadata !"/tmp/f.c", metadata !"/tmp"} +!27 = metadata !{metadata !"f.i", metadata !"/tmp"} diff --git a/test/CodeGen/X86/dbg-value-range.ll b/test/CodeGen/X86/dbg-value-range.ll index 2b26af93b6..6766dbe9ed 100644 --- a/test/CodeGen/X86/dbg-value-range.ll +++ b/test/CodeGen/X86/dbg-value-range.ll @@ -18,12 +18,10 @@ declare i32 @foo(...) declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!2} -!20 = metadata !{metadata !0} -!21 = metadata !{metadata !6, metadata !11} -!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (%struct.a*)* @bar, null, null, metadata !21, i32 0} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786473, metadata !"bar.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"bar.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 122997)", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !20, null, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786478, metadata !1, metadata !"bar", metadata !"bar", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (%struct.a*)* @bar, null, null, metadata !21, i32 0} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786473, metadata !22} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 786449, metadata !22, i32 12, metadata !"clang version 2.9 (trunk 122997)", i1 true, metadata !"", i32 0, null, null, metadata !20, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] @@ -33,7 +31,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !9 = metadata !{metadata !10} !10 = metadata !{i32 786445, metadata !1, metadata !"c", metadata !1, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] !11 = metadata !{i32 786688, metadata !12, metadata !"x", metadata !1, i32 6, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] -!12 = metadata !{i32 786443, metadata !0, i32 5, i32 22, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!12 = metadata !{i32 786443, metadata !22, metadata !0, i32 5, i32 22, i32 0} ; [ DW_TAG_lexical_block ] !13 = metadata !{i32 5, i32 19, metadata !0, null} !14 = metadata !{i32 6, i32 14, metadata !12, null} !15 = metadata !{metadata !"int", metadata !16} @@ -41,6 +39,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !17 = metadata !{metadata !"Simple C/C++ TBAA", null} !18 = metadata !{i32 7, i32 2, metadata !12, null} !19 = metadata !{i32 8, i32 2, metadata !12, null} +!20 = metadata !{metadata !0} +!21 = metadata !{metadata !6, metadata !11} +!22 = metadata !{metadata !"bar.c", metadata !"/private/tmp"} ; Check that variable bar:b value range is appropriately trucated in debug info. ; The variable is in %rdi which is clobbered by 'movl %ebx, %edi' diff --git a/test/CodeGen/X86/dwarf-comp-dir.ll b/test/CodeGen/X86/dwarf-comp-dir.ll index 63e6167bcb..3bc2957963 100644 --- a/test/CodeGen/X86/dwarf-comp-dir.ll +++ b/test/CodeGen/X86/dwarf-comp-dir.ll @@ -6,9 +6,11 @@ target triple = "x86_64-unknown-linux-gnu" !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"empty.c", metadata !"/home/nlewycky", metadata !"clang version 3.1 (trunk 143523)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !1} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 720913, metadata !4, i32 12, metadata !"clang version 3.1 (trunk 143523)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !1} ; [ DW_TAG_compile_unit ] !1 = metadata !{metadata !2} !2 = metadata !{i32 0} +!3 = metadata !{i32 786473, metadata !4} ; [ DW_TAG_file_type ] +!4 = metadata !{metadata !"empty.c", metadata !"/home/nlewycky"} ; The important part of the following check is that dir = #0. ; Dir Mod Time File Len File Name diff --git a/test/CodeGen/X86/fast-isel-args-fail.ll b/test/CodeGen/X86/fast-isel-args-fail.ll index 4995baa3e5..45a2b384de 100644 --- a/test/CodeGen/X86/fast-isel-args-fail.ll +++ b/test/CodeGen/X86/fast-isel-args-fail.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -fast-isel -verify-machineinstrs -mtriple=x86_64-apple-darwin10 +; RUN: llc < %s -fast-isel -verify-machineinstrs -mtriple=x86_64-pc-win32 | FileCheck %s ; Requires: Asserts ; Previously, this would cause an assert. @@ -8,3 +9,12 @@ entry: %add1 = add nsw i31 %add, %c ret i31 %add1 } + +; We don't handle the Windows CC, yet. +define i32 @foo(i32* %p) { +entry: +; CHECK: foo +; CHECK: movl (%rcx), %eax + %0 = load i32* %p, align 4 + ret i32 %0 +} diff --git a/test/CodeGen/X86/fast-isel-expect.ll b/test/CodeGen/X86/fast-isel-expect.ll index 1f53348bd0..c4be7f364f 100644 --- a/test/CodeGen/X86/fast-isel-expect.ll +++ b/test/CodeGen/X86/fast-isel-expect.ll @@ -5,7 +5,7 @@ target triple = "x86_64-unknown-linux-gnu" @glbl = extern_weak constant i8 -declare i64 @llvm.expect.i64(i64, i64) #0 +declare i64 @llvm.expect.i64(i64, i64) define void @test() { ; CHECK: movl $glbl @@ -19,5 +19,3 @@ bb1: bb2: unreachable } - -attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/X86/Stats/hoist-invariant-load.ll b/test/CodeGen/X86/hoist-invariant-load.ll index 74ecd045b3..34191e3f9a 100644 --- a/test/CodeGen/X86/Stats/hoist-invariant-load.ll +++ b/test/CodeGen/X86/hoist-invariant-load.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -stats -O2 2>&1 | grep "1 machine-licm" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" diff --git a/test/CodeGen/X86/Stats/licm-nested.ll b/test/CodeGen/X86/licm-nested.ll index c3f991d7a9..66074fb368 100644 --- a/test/CodeGen/X86/Stats/licm-nested.ll +++ b/test/CodeGen/X86/licm-nested.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc -mtriple=x86_64-apple-darwin -march=x86-64 < %s -o /dev/null -stats -info-output-file - | grep "hoisted out of loops" | grep 3 ; MachineLICM should be able to hoist the symbolic addresses out of diff --git a/test/CodeGen/X86/lit.local.cfg b/test/CodeGen/X86/lit.local.cfg index a8ad0f1a28..9d285bf4e2 100644 --- a/test/CodeGen/X86/lit.local.cfg +++ b/test/CodeGen/X86/lit.local.cfg @@ -1,4 +1,4 @@ -config.suffixes = ['.ll', '.c', '.cpp'] +config.suffixes = ['.ll', '.c', '.cpp', '.test'] targets = set(config.root.targets_to_build.split()) if not 'X86' in targets: diff --git a/test/CodeGen/X86/misched-ilp.ll b/test/CodeGen/X86/misched-ilp.ll index c6cedb7be8..4ca296ca92 100644 --- a/test/CodeGen/X86/misched-ilp.ll +++ b/test/CodeGen/X86/misched-ilp.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=x86_64-apple-macosx -mcpu=core2 -enable-misched -misched=ilpmax | FileCheck -check-prefix=MAX %s -; RUN: llc < %s -mtriple=x86_64-apple-macosx -mcpu=core2 -enable-misched -misched=ilpmin | FileCheck -check-prefix=MIN %s +; RUN: llc < %s -mtriple=x86_64-apple-macosx -mcpu=nocona -enable-misched -misched=ilpmax | FileCheck -check-prefix=MAX %s +; RUN: llc < %s -mtriple=x86_64-apple-macosx -mcpu=nocona -enable-misched -misched=ilpmin | FileCheck -check-prefix=MIN %s ; ; Basic verification of the ScheduleDAGILP metric. ; diff --git a/test/CodeGen/X86/movgs.ll b/test/CodeGen/X86/movgs.ll index 65ee7b1d8e..bb42734833 100644 --- a/test/CodeGen/X86/movgs.ll +++ b/test/CodeGen/X86/movgs.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mattr=sse41 | FileCheck %s --check-prefix=X32 -; RUN: llc < %s -mtriple=x86_64-linux -mattr=sse41 | FileCheck %s --check-prefix=X64 -; RUN: llc < %s -mtriple=x86_64-win32 -mattr=sse41 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mcpu=penryn -mattr=sse41 | FileCheck %s --check-prefix=X32 +; RUN: llc < %s -mtriple=x86_64-linux -mcpu=penryn -mattr=sse41 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=penryn -mattr=sse41 | FileCheck %s --check-prefix=X64 define i32 @test1() nounwind readonly { entry: diff --git a/test/CodeGen/X86/multiple-loop-post-inc.ll b/test/CodeGen/X86/multiple-loop-post-inc.ll index 9f7d036cf1..29b9f34464 100644 --- a/test/CodeGen/X86/multiple-loop-post-inc.ll +++ b/test/CodeGen/X86/multiple-loop-post-inc.ll @@ -1,4 +1,4 @@ -; RUN: llc -asm-verbose=false -disable-branch-fold -disable-code-place -disable-tail-duplicate -march=x86-64 -mcpu=nehalem < %s | FileCheck %s +; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem < %s | FileCheck %s ; rdar://7236213 ; ; The scheduler's 2-address hack has been disabled, so there is diff --git a/test/CodeGen/X86/Stats/phi-immediate-factoring.ll b/test/CodeGen/X86/phi-immediate-factoring.ll index 476bb10998..6425ef0e83 100644 --- a/test/CodeGen/X86/Stats/phi-immediate-factoring.ll +++ b/test/CodeGen/X86/phi-immediate-factoring.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -stats 2>&1 | grep "Number of blocks eliminated" | grep 6 ; PR1296 diff --git a/test/CodeGen/X86/pr15296.ll b/test/CodeGen/X86/pr15296.ll new file mode 100644 index 0000000000..1187d80cdf --- /dev/null +++ b/test/CodeGen/X86/pr15296.ll @@ -0,0 +1,46 @@ +; RUN: llc < %s -mtriple=i686-pc-linux -mcpu=corei7-avx | FileCheck %s + +define <8 x i32> @shiftInput___vyuunu(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwind { +allocas: + %smear.0 = insertelement <8 x i32> undef, i32 %shiftval, i32 0 + %smear.1 = insertelement <8 x i32> %smear.0, i32 %shiftval, i32 1 + %smear.2 = insertelement <8 x i32> %smear.1, i32 %shiftval, i32 2 + %smear.3 = insertelement <8 x i32> %smear.2, i32 %shiftval, i32 3 + %smear.4 = insertelement <8 x i32> %smear.3, i32 %shiftval, i32 4 + %smear.5 = insertelement <8 x i32> %smear.4, i32 %shiftval, i32 5 + %smear.6 = insertelement <8 x i32> %smear.5, i32 %shiftval, i32 6 + %smear.7 = insertelement <8 x i32> %smear.6, i32 %shiftval, i32 7 + %bitop = lshr <8 x i32> %input, %smear.7 + ret <8 x i32> %bitop +} + +; CHECK: shiftInput___vyuunu +; CHECK: psrld +; CHECK: psrld +; CHECK: ret + +define <8 x i32> @shiftInput___canonical(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwind { +allocas: + %smear.0 = insertelement <8 x i32> undef, i32 %shiftval, i32 0 + %smear.7 = shufflevector <8 x i32> %smear.0, <8 x i32> undef, <8 x i32> zeroinitializer + %bitop = lshr <8 x i32> %input, %smear.7 + ret <8 x i32> %bitop +} + +; CHECK: shiftInput___canonical +; CHECK: psrld +; CHECK: psrld +; CHECK: ret + +define <4 x i64> @shiftInput___64in32bitmode(<4 x i64> %input, i64 %shiftval, <4 x i64> %__mask) nounwind { +allocas: + %smear.0 = insertelement <4 x i64> undef, i64 %shiftval, i32 0 + %smear.7 = shufflevector <4 x i64> %smear.0, <4 x i64> undef, <4 x i32> zeroinitializer + %bitop = lshr <4 x i64> %input, %smear.7 + ret <4 x i64> %bitop +} + +; CHECK: shiftInput___64in32bitmode +; CHECK: psrlq +; CHECK: psrlq +; CHECK: ret diff --git a/test/CodeGen/X86/pr15309.ll b/test/CodeGen/X86/pr15309.ll new file mode 100644 index 0000000000..6dbbc72a7b --- /dev/null +++ b/test/CodeGen/X86/pr15309.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=i686-linux-pc -mcpu=corei7 | FileCheck %s + +define void @test_convert_float2_ulong2(<2 x i64>* nocapture %src, <2 x float>* nocapture %dest) noinline { +L.entry: + %0 = getelementptr <2 x i64>* %src, i32 10 + %1 = load <2 x i64>* %0, align 16 + %2 = uitofp <2 x i64> %1 to <2 x float> + %3 = getelementptr <2 x float>* %dest, i32 10 + store <2 x float> %2, <2 x float>* %3, align 8 + ret void +} + +; CHECK: test_convert_float2_ulong2 +; CHECK-NOT: cvtpd2ps +; CHECK: ret diff --git a/test/CodeGen/X86/Stats/pr3522.ll b/test/CodeGen/X86/pr3522.ll index d8f37781fc..9f8dc03706 100644 --- a/test/CodeGen/X86/Stats/pr3522.ll +++ b/test/CodeGen/X86/pr3522.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -stats 2>&1 | not grep "instructions sunk" ; PR3522 diff --git a/test/CodeGen/X86/prefetch.ll b/test/CodeGen/X86/prefetch.ll index ec2f302b14..efb51913c5 100644 --- a/test/CodeGen/X86/prefetch.ll +++ b/test/CodeGen/X86/prefetch.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s ; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse -mattr=+prfchw | FileCheck %s -check-prefix=PRFCHW ; rdar://10538297 @@ -9,10 +10,12 @@ entry: ; CHECK: prefetcht1 ; CHECK: prefetcht0 ; CHECK: prefetchnta +; PRFCHW: prefetchw tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 ) tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 ) tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 ) tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 ) + tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 ) ret void } diff --git a/test/CodeGen/X86/rdseed.ll b/test/CodeGen/X86/rdseed.ll new file mode 100644 index 0000000000..35de7ebf74 --- /dev/null +++ b/test/CodeGen/X86/rdseed.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -march=x86-64 -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s + +declare {i16, i32} @llvm.x86.rdseed.16() +declare {i32, i32} @llvm.x86.rdseed.32() +declare {i64, i32} @llvm.x86.rdseed.64() + +define i32 @_rdseed16_step(i16* %random_val) { + %call = call {i16, i32} @llvm.x86.rdseed.16() + %randval = extractvalue {i16, i32} %call, 0 + store i16 %randval, i16* %random_val + %isvalid = extractvalue {i16, i32} %call, 1 + ret i32 %isvalid +; CHECK: _rdseed16_step: +; CHECK: rdseedw %ax +; CHECK: movw %ax, (%r[[A0:di|cx]]) +; CHECK: movzwl %ax, %ecx +; CHECK: movl $1, %eax +; CHECK: cmovael %ecx, %eax +; CHECK: ret +} + +define i32 @_rdseed32_step(i32* %random_val) { + %call = call {i32, i32} @llvm.x86.rdseed.32() + %randval = extractvalue {i32, i32} %call, 0 + store i32 %randval, i32* %random_val + %isvalid = extractvalue {i32, i32} %call, 1 + ret i32 %isvalid +; CHECK: _rdseed32_step: +; CHECK: rdseedl %e[[T0:[a-z]+]] +; CHECK: movl %e[[T0]], (%r[[A0]]) +; CHECK: movl $1, %eax +; CHECK: cmovael %e[[T0]], %eax +; CHECK: ret +} + +define i32 @_rdseed64_step(i64* %random_val) { + %call = call {i64, i32} @llvm.x86.rdseed.64() + %randval = extractvalue {i64, i32} %call, 0 + store i64 %randval, i64* %random_val + %isvalid = extractvalue {i64, i32} %call, 1 + ret i32 %isvalid +; CHECK: _rdseed64_step: +; CHECK: rdseedq %r[[T1:[a-z]+]] +; CHECK: movq %r[[T1]], (%r[[A0]]) +; CHECK: movl $1, %eax +; CHECK: cmovael %e[[T1]], %eax +; CHECK: ret +} diff --git a/test/CodeGen/X86/Stats/regpressure.ll b/test/CodeGen/X86/regpressure.ll index 52d7b56f18..1f756bee8a 100644 --- a/test/CodeGen/X86/Stats/regpressure.ll +++ b/test/CodeGen/X86/regpressure.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ;; Both functions in this testcase should codegen to the same function, and ;; neither of them should require spilling anything to the stack. diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll index 2af355905d..ceb79ea927 100644 --- a/test/CodeGen/X86/sibcall.ll +++ b/test/CodeGen/X86/sibcall.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=32 -; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=64 +; RUN: llc < %s -mtriple=i686-linux -mcpu=core2 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=32 +; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core2 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=64 define void @t1(i32 %x) nounwind ssp { entry: diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll index 649cd61ab7..2aca5b897d 100644 --- a/test/CodeGen/X86/sink-hoist.ll +++ b/test/CodeGen/X86/sink-hoist.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -mcpu=nehalem -post-RA-scheduler=true | FileCheck %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -mcpu=nehalem -post-RA-scheduler=true -schedmodel=false | FileCheck %s ; Currently, floating-point selects are lowered to CFG triangles. ; This means that one side of the select is always unconditionally diff --git a/test/CodeGen/X86/tls.ll b/test/CodeGen/X86/tls.ll index e8a79bfa6e..8cdecd81bf 100644 --- a/test/CodeGen/X86/tls.ll +++ b/test/CodeGen/X86/tls.ll @@ -22,13 +22,13 @@ define i32 @f1() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movl _i1@SECREL(%eax), %eax +; X32_WIN-NEXT: movl _i1@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f1: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movl i1@SECREL(%rax), %eax +; X64_WIN-NEXT: movl i1@SECREL32(%rax), %eax ; X64_WIN-NEXT: ret entry: @@ -49,13 +49,13 @@ define i32* @f2() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: leal _i1@SECREL(%eax), %eax +; X32_WIN-NEXT: leal _i1@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f2: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: leaq i1@SECREL(%rax), %rax +; X64_WIN-NEXT: leaq i1@SECREL32(%rax), %rax ; X64_WIN-NEXT: ret entry: @@ -75,13 +75,13 @@ define i32 @f3() nounwind { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movl _i2@SECREL(%eax), %eax +; X32_WIN-NEXT: movl _i2@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f3: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movl i2@SECREL(%rax), %eax +; X64_WIN-NEXT: movl i2@SECREL32(%rax), %eax ; X64_WIN-NEXT: ret entry: @@ -102,13 +102,13 @@ define i32* @f4() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: leal _i2@SECREL(%eax), %eax +; X32_WIN-NEXT: leal _i2@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f4: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: leaq i2@SECREL(%rax), %rax +; X64_WIN-NEXT: leaq i2@SECREL32(%rax), %rax ; X64_WIN-NEXT: ret entry: @@ -126,13 +126,13 @@ define i32 @f5() nounwind { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movl _i3@SECREL(%eax), %eax +; X32_WIN-NEXT: movl _i3@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f5: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movl i3@SECREL(%rax), %eax +; X64_WIN-NEXT: movl i3@SECREL32(%rax), %eax ; X64_WIN-NEXT: ret entry: @@ -153,13 +153,13 @@ define i32* @f6() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: leal _i3@SECREL(%eax), %eax +; X32_WIN-NEXT: leal _i3@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f6: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: leaq i3@SECREL(%rax), %rax +; X64_WIN-NEXT: leaq i3@SECREL32(%rax), %rax ; X64_WIN-NEXT: ret entry: @@ -234,14 +234,14 @@ define i16 @f11() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movzwl _s1@SECREL(%eax), %eax +; X32_WIN-NEXT: movzwl _s1@SECREL32(%eax), %eax ; X32_WIN-NEXT: # kill ; X32_WIN-NEXT: ret ; X64_WIN: f11: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movzwl s1@SECREL(%rax), %eax +; X64_WIN-NEXT: movzwl s1@SECREL32(%rax), %eax ; X64_WIN-NEXT: # kill ; X64_WIN-NEXT: ret @@ -261,13 +261,13 @@ define i32 @f12() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movswl _s1@SECREL(%eax), %eax +; X32_WIN-NEXT: movswl _s1@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f12: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movswl s1@SECREL(%rax), %eax +; X64_WIN-NEXT: movswl s1@SECREL32(%rax), %eax ; X64_WIN-NEXT: ret entry: @@ -287,13 +287,13 @@ define i8 @f13() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movb _b1@SECREL(%eax), %al +; X32_WIN-NEXT: movb _b1@SECREL32(%eax), %al ; X32_WIN-NEXT: ret ; X64_WIN: f13: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movb b1@SECREL(%rax), %al +; X64_WIN-NEXT: movb b1@SECREL32(%rax), %al ; X64_WIN-NEXT: ret entry: @@ -312,13 +312,13 @@ define i32 @f14() { ; X32_WIN: movl __tls_index, %eax ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax -; X32_WIN-NEXT: movsbl _b1@SECREL(%eax), %eax +; X32_WIN-NEXT: movsbl _b1@SECREL32(%eax), %eax ; X32_WIN-NEXT: ret ; X64_WIN: f14: ; X64_WIN: movl _tls_index(%rip), %eax ; X64_WIN-NEXT: movq %gs:88, %rcx ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax -; X64_WIN-NEXT: movsbl b1@SECREL(%rax), %eax +; X64_WIN-NEXT: movsbl b1@SECREL32(%rax), %eax ; X64_WIN-NEXT: ret entry: diff --git a/test/CodeGen/X86/Stats/twoaddr-coalesce-2.ll b/test/CodeGen/X86/twoaddr-coalesce-2.ll index af6d47af7a..cbcde06555 100644 --- a/test/CodeGen/X86/Stats/twoaddr-coalesce-2.ll +++ b/test/CodeGen/X86/twoaddr-coalesce-2.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn -stats 2>&1 | \ ; RUN: grep "twoaddrinstr" | grep "Number of instructions aggressively commuted" ; rdar://6480363 diff --git a/test/CodeGen/X86/Stats/twoaddr-pass-sink.ll b/test/CodeGen/X86/twoaddr-pass-sink.ll index 513c304e3b..9ca280627a 100644 --- a/test/CodeGen/X86/Stats/twoaddr-pass-sink.ll +++ b/test/CodeGen/X86/twoaddr-pass-sink.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mattr=+sse2 -stats 2>&1 | grep "Number of 3-address instructions sunk" define void @t2(<2 x i64>* %vDct, <2 x i64>* %vYp, i8* %skiplist, <2 x i64> %a1) nounwind { diff --git a/test/CodeGen/X86/unknown-location.ll b/test/CodeGen/X86/unknown-location.ll index d3b4d31f6a..e02e3b5475 100644 --- a/test/CodeGen/X86/unknown-location.ll +++ b/test/CodeGen/X86/unknown-location.ll @@ -19,14 +19,15 @@ entry: } !llvm.dbg.cu = !{!3} -!9 = metadata !{metadata !1} !0 = metadata !{i32 786689, metadata !1, metadata !"x", metadata !2, i32 1, metadata !6} ; [ DW_TAG_arg_variable ] -!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 1, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, i32, i32, i32)* @foo, null, null, null, i32 1} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 786473, metadata !"test.c", metadata !"/dir", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 0, i32 12, metadata !"test.c", metadata !".", metadata !"producer", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !9, null} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 1, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, i32, i32, i32)* @foo, null, null, null, i32 1} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 786473, metadata !10} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 786449, metadata !10, i32 12, metadata !"producer", i1 false, metadata !"", i32 0, null, null, metadata !9, null, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6} !6 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !7 = metadata !{i32 786443, metadata !1, i32 1, i32 30} ; [ DW_TAG_lexical_block ] !8 = metadata !{i32 4, i32 3, metadata !7, null} +!9 = metadata !{metadata !1} +!10 = metadata !{metadata !"test.c", metadata !"/dir"} diff --git a/test/CodeGen/X86/vec_align_i256.ll b/test/CodeGen/X86/vec_align_i256.ll new file mode 100644 index 0000000000..078bcb1544 --- /dev/null +++ b/test/CodeGen/X86/vec_align_i256.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i686-apple-darwin8" + +; Make sure that we are not generating a movaps because the vector is aligned to 1. +;CHECK: @foo +;CHECK: xor +;CHECK-NEXT: vmovups +;CHECK-NEXT: ret +define void @foo() { + store <16 x i16> zeroinitializer, <16 x i16>* undef, align 1 + ret void +} diff --git a/test/CodeGen/X86/vec_fpext.ll b/test/CodeGen/X86/vec_fpext.ll index e4a8f46cbc..863712ff48 100644 --- a/test/CodeGen/X86/vec_fpext.ll +++ b/test/CodeGen/X86/vec_fpext.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 -mattr=+sse41,-avx | FileCheck %s -; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck --check-prefix=AVX %s +; RUN: llc < %s -march=x86 -mcpu=corei7-avx | FileCheck --check-prefix=AVX %s ; PR11674 define void @fpext_frommem(<2 x float>* %in, <2 x double>* %out) { diff --git a/test/CodeGen/X86/Stats/vec_insert-6.ll b/test/CodeGen/X86/vec_insert-6.ll index 2a4864a48a..4583e1925e 100644 --- a/test/CodeGen/X86/Stats/vec_insert-6.ll +++ b/test/CodeGen/X86/vec_insert-6.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn | grep pslldq ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn -mtriple=i686-apple-darwin9 -o /dev/null -stats -info-output-file - | grep asm-printer | grep 6 diff --git a/test/CodeGen/X86/Stats/vec_shuffle-19.ll b/test/CodeGen/X86/vec_shuffle-19.ll index b26f920e5e..48db8de0d9 100644 --- a/test/CodeGen/X86/Stats/vec_shuffle-19.ll +++ b/test/CodeGen/X86/vec_shuffle-19.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -o /dev/null -march=x86 -mcpu=penryn -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 4 ; PR2485 diff --git a/test/CodeGen/X86/Stats/vec_shuffle-20.ll b/test/CodeGen/X86/vec_shuffle-20.ll index b6b8ba6f84..5a2c444945 100644 --- a/test/CodeGen/X86/Stats/vec_shuffle-20.ll +++ b/test/CodeGen/X86/vec_shuffle-20.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -o /dev/null -march=x86 -mcpu=corei7 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 2 define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) nounwind { diff --git a/test/CodeGen/X86/wide-fma-contraction.ll b/test/CodeGen/X86/wide-fma-contraction.ll new file mode 100644 index 0000000000..d93f33ba0e --- /dev/null +++ b/test/CodeGen/X86/wide-fma-contraction.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s + +; CHECK: fmafunc +define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x float> %c) { +; CHECK-NOT: vmulps +; CHECK-NOT: vaddps +; CHECK: vfmaddps +; CHECK-NOT: vmulps +; CHECK-NOT: vaddps +; CHECK: vfmaddps +; CHECK-NOT: vmulps +; CHECK-NOT: vaddps + %ret = tail call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c) + ret <16 x float> %ret +} + +declare <16 x float> @llvm.fmuladd.v16f32(<16 x float>, <16 x float>, <16 x float>) nounwind readnone + + + diff --git a/test/CodeGen/X86/win32_sret.ll b/test/CodeGen/X86/win32_sret.ll index 878c6db992..19cbfd45ed 100644 --- a/test/CodeGen/X86/win32_sret.ll +++ b/test/CodeGen/X86/win32_sret.ll @@ -1,28 +1,84 @@ -; RUN: llc < %s -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN_X32 -; RUN: llc < %s -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X32 +; RUN: llc < %s -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN32 +; RUN: llc < %s -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X86 ; RUN: llc < %s -mtriple=i386-pc-linux | FileCheck %s -check-prefix=LINUX -; RUN: llc < %s -O0 -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN_X32 -; RUN: llc < %s -O0 -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X32 +; RUN: llc < %s -O0 -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN32 +; RUN: llc < %s -O0 -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X86 ; RUN: llc < %s -O0 -mtriple=i386-pc-linux | FileCheck %s -check-prefix=LINUX ; The SysV ABI used by most Unixes and Mingw on x86 specifies that an sret pointer ; is callee-cleanup. However, in MSVC's cdecl calling convention, sret pointer ; arguments are caller-cleanup like normal arguments. -define void @sret1(i8* sret) nounwind { +define void @sret1(i8* sret %x) nounwind { entry: -; WIN_X32: {{ret$}} -; MINGW_X32: ret $4 +; WIN32: sret1 +; WIN32: movb $42, (%eax) +; WIN32-NOT: popl %eax +; WIN32: {{ret$}} + +; MINGW_X86: sret1 +; MINGW_X86: ret $4 + +; LINUX: sret1 ; LINUX: ret $4 + + store i8 42, i8* %x, align 4 ret void } -define void @sret2(i32* sret %x, i32 %y) nounwind { +define void @sret2(i8* sret %x, i8 %y) nounwind { entry: -; WIN_X32: {{ret$}} -; MINGW_X32: ret $4 +; WIN32: sret2 +; WIN32: movb {{.*}}, (%eax) +; WIN32-NOT: popl %eax +; WIN32: {{ret$}} + +; MINGW_X86: sret2 +; MINGW_X86: ret $4 + +; LINUX: sret2 ; LINUX: ret $4 - store i32 %y, i32* %x + + store i8 %y, i8* %x ret void } +define void @sret3(i8* sret %x, i8* %y) nounwind { +entry: +; WIN32: sret3 +; WIN32: movb $42, (%eax) +; WIN32-NOT: movb $13, (%eax) +; WIN32-NOT: popl %eax +; WIN32: {{ret$}} + +; MINGW_X86: sret3 +; MINGW_X86: ret $4 + +; LINUX: sret3 +; LINUX: ret $4 + + store i8 42, i8* %x + store i8 13, i8* %y + ret void +} + +; PR15556 +%struct.S4 = type { i32, i32, i32 } + +define void @sret4(%struct.S4* noalias sret %agg.result) { +entry: +; WIN32: sret4 +; WIN32: movl $42, (%eax) +; WIN32-NOT: popl %eax +; WIN32: {{ret$}} + +; MINGW_X86: sret4 +; MINGW_X86: ret $4 + +; LINUX: sret4 +; LINUX: ret $4 + + %x = getelementptr inbounds %struct.S4* %agg.result, i32 0, i32 0 + store i32 42, i32* %x, align 4 + ret void +} diff --git a/test/CodeGen/X86/win_ftol2.ll b/test/CodeGen/X86/win_ftol2.ll index 7f8ae07463..14591248f3 100644 --- a/test/CodeGen/X86/win_ftol2.ll +++ b/test/CodeGen/X86/win_ftol2.ll @@ -63,9 +63,9 @@ define i64 @double_ui64_2(double %x, double %y, double %z) nounwind { %1 = fdiv double %x, %y %2 = fsub double %x, %z - %3 = fptoui double %1 to i64 - %4 = fptoui double %2 to i64 - %5 = sub i64 %3, %4 + %3 = fptoui double %2 to i64 + %4 = fptoui double %1 to i64 + %5 = sub i64 %4, %3 ret i64 %5 } @@ -121,9 +121,9 @@ define {double, i64} @double_ui64_4(double %x, double %y) nounwind { ; FTOL_2: calll __ftol2 ;; stack is %x - %1 = fptoui double %x to i64 - %2 = fptoui double %y to i64 - %3 = sub i64 %1, %2 + %1 = fptoui double %y to i64 + %2 = fptoui double %x to i64 + %3 = sub i64 %2, %1 %4 = insertvalue {double, i64} undef, double %x, 0 %5 = insertvalue {double, i64} %4, i64 %3, 1 ret {double, i64} %5 diff --git a/test/CodeGen/X86/xtest.ll b/test/CodeGen/X86/xtest.ll new file mode 100644 index 0000000000..e85565edcd --- /dev/null +++ b/test/CodeGen/X86/xtest.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=x86-64 -mattr=+rtm | FileCheck %s + +declare i32 @llvm.x86.xtest() nounwind + +define i32 @test_xtest() nounwind uwtable { +entry: + %0 = tail call i32 @llvm.x86.xtest() nounwind + ret i32 %0 +; CHECK: test_xtest +; CHECK: xtest +} diff --git a/test/CodeGen/X86/Stats/zero-remat.ll b/test/CodeGen/X86/zero-remat.ll index 4242530f77..5d25a2d749 100644 --- a/test/CodeGen/X86/Stats/zero-remat.ll +++ b/test/CodeGen/X86/zero-remat.ll @@ -1,3 +1,4 @@ +; REQUIRES: asserts ; RUN: llc < %s -march=x86-64 | FileCheck %s --check-prefix=CHECK-64 ; RUN: llc < %s -march=x86-64 -o /dev/null -stats -info-output-file - | grep asm-printer | grep 12 ; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32 diff --git a/test/CodeGen/XCore/DbgValueOtherTargets.test b/test/CodeGen/XCore/DbgValueOtherTargets.test index 93ab7e0f15..7c2ecd0312 100644 --- a/test/CodeGen/XCore/DbgValueOtherTargets.test +++ b/test/CodeGen/XCore/DbgValueOtherTargets.test @@ -1 +1 @@ -; RUN: llc -O0 -march=xcore -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -march=xcore -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/test/CodeGen/XCore/lit.local.cfg b/test/CodeGen/XCore/lit.local.cfg index f8726af57f..8756f37fe8 100644 --- a/test/CodeGen/XCore/lit.local.cfg +++ b/test/CodeGen/XCore/lit.local.cfg @@ -1,4 +1,4 @@ -config.suffixes = ['.ll', '.c', '.cpp'] +config.suffixes = ['.ll', '.c', '.cpp', '.test'] targets = set(config.root.targets_to_build.split()) if not 'XCore' in targets: |