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-rw-r--r--test/CodeGen/Mips/DbgValueOtherTargets.test2
-rw-r--r--test/CodeGen/Mips/dsp-patterns.ll31
-rw-r--r--test/CodeGen/Mips/lit.local.cfg2
-rw-r--r--test/CodeGen/Mips/madd-msub.ll22
4 files changed, 48 insertions, 9 deletions
diff --git a/test/CodeGen/Mips/DbgValueOtherTargets.test b/test/CodeGen/Mips/DbgValueOtherTargets.test
index 9c351ace68..da20e7ef52 100644
--- a/test/CodeGen/Mips/DbgValueOtherTargets.test
+++ b/test/CodeGen/Mips/DbgValueOtherTargets.test
@@ -1 +1 @@
-; RUN: llc -O0 -march=mips -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll
+RUN: llc -O0 -march=mips -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll
diff --git a/test/CodeGen/Mips/dsp-patterns.ll b/test/CodeGen/Mips/dsp-patterns.ll
new file mode 100644
index 0000000000..0752f69c3e
--- /dev/null
+++ b/test/CodeGen/Mips/dsp-patterns.ll
@@ -0,0 +1,31 @@
+; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s
+
+; CHECK: test_lbux:
+; CHECK: lbux ${{[0-9]+}}
+
+define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) {
+entry:
+ %add.ptr = getelementptr inbounds i8* %b, i32 %i
+ %0 = load i8* %add.ptr, align 1
+ ret i8 %0
+}
+
+; CHECK: test_lhx:
+; CHECK: lhx ${{[0-9]+}}
+
+define signext i16 @test_lhx(i16* nocapture %b, i32 %i) {
+entry:
+ %add.ptr = getelementptr inbounds i16* %b, i32 %i
+ %0 = load i16* %add.ptr, align 2
+ ret i16 %0
+}
+
+; CHECK: test_lwx:
+; CHECK: lwx ${{[0-9]+}}
+
+define i32 @test_lwx(i32* nocapture %b, i32 %i) {
+entry:
+ %add.ptr = getelementptr inbounds i32* %b, i32 %i
+ %0 = load i32* %add.ptr, align 4
+ ret i32 %0
+}
diff --git a/test/CodeGen/Mips/lit.local.cfg b/test/CodeGen/Mips/lit.local.cfg
index 0587d3243e..e157c540b5 100644
--- a/test/CodeGen/Mips/lit.local.cfg
+++ b/test/CodeGen/Mips/lit.local.cfg
@@ -1,4 +1,4 @@
-config.suffixes = ['.ll', '.c', '.cpp']
+config.suffixes = ['.ll', '.c', '.cpp', '.test']
targets = set(config.root.targets_to_build.split())
if not 'Mips' in targets:
diff --git a/test/CodeGen/Mips/madd-msub.ll b/test/CodeGen/Mips/madd-msub.ll
index 0aeabb30e2..0dbb2c27b8 100644
--- a/test/CodeGen/Mips/madd-msub.ll
+++ b/test/CodeGen/Mips/madd-msub.ll
@@ -1,6 +1,9 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=32
+; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
+; RUN: llc -march=mips -mcpu=mips16 < %s
-; CHECK: madd
+; 32: madd ${{[0-9]+}}
+; DSP: madd $ac
define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = sext i32 %a to i64
@@ -11,7 +14,8 @@ entry:
ret i64 %add
}
-; CHECK: maddu
+; 32: maddu ${{[0-9]+}}
+; DSP: maddu $ac
define i64 @madd2(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = zext i32 %a to i64
@@ -22,7 +26,8 @@ entry:
ret i64 %add
}
-; CHECK: madd
+; 32: madd ${{[0-9]+}}
+; DSP: madd $ac
define i64 @madd3(i32 %a, i32 %b, i64 %c) nounwind readnone {
entry:
%conv = sext i32 %a to i64
@@ -32,7 +37,8 @@ entry:
ret i64 %add
}
-; CHECK: msub
+; 32: msub ${{[0-9]+}}
+; DSP: msub $ac
define i64 @msub1(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = sext i32 %c to i64
@@ -43,7 +49,8 @@ entry:
ret i64 %sub
}
-; CHECK: msubu
+; 32: msubu ${{[0-9]+}}
+; DSP: msubu $ac
define i64 @msub2(i32 %a, i32 %b, i32 %c) nounwind readnone {
entry:
%conv = zext i32 %c to i64
@@ -54,7 +61,8 @@ entry:
ret i64 %sub
}
-; CHECK: msub
+; 32: msub ${{[0-9]+}}
+; DSP: msub $ac
define i64 @msub3(i32 %a, i32 %b, i64 %c) nounwind readnone {
entry:
%conv = sext i32 %a to i64