diff options
Diffstat (limited to 'lib/CodeGen/SelectionDAG')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 16 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 8 |
2 files changed, 12 insertions, 12 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index d33e1ecef7..71f2bce118 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -255,11 +255,11 @@ static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI, // the machine instruction. unsigned ResultReg = RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0)); - MI->addRegOperand(ResultReg, MachineOperand::Def); + MI->addRegOperand(ResultReg, true); for (unsigned i = 1; i != NumResults; ++i) { const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i); assert(RC && "Isn't a register operand!"); - MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def); + MI->addRegOperand(RegMap->createVirtualRegister(RC), true); } return ResultReg; } @@ -291,7 +291,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, // Get/emit the operand. unsigned VReg = getVR(Op, VRBaseMap); - MI->addRegOperand(VReg, MachineOperand::Use); + MI->addRegOperand(VReg, false); // Verify that it is right. assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); @@ -307,7 +307,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, MI->addImmOperand(C->getValue()); } else if (RegisterSDNode*R = dyn_cast<RegisterSDNode>(Op)) { - MI->addRegOperand(R->getReg(), MachineOperand::Use); + MI->addRegOperand(R->getReg(), false); } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset()); @@ -349,7 +349,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, Op.getValueType() != MVT::Flag && "Chain and flag operands should occur at end of operand list!"); unsigned VReg = getVR(Op, VRBaseMap); - MI->addRegOperand(VReg, MachineOperand::Use); + MI->addRegOperand(VReg, false); // Verify that it is right. assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); @@ -402,7 +402,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg(); if (MRegisterInfo::isVirtualRegister(Reg)) { VRBase = Reg; - MI->addRegOperand(Reg, MachineOperand::Def); + MI->addRegOperand(Reg, true); break; } } @@ -529,13 +529,13 @@ void ScheduleDAG::EmitNode(SDNode *Node, case 1: // Use of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); - MI->addRegOperand(Reg, MachineOperand::Use); + MI->addRegOperand(Reg, false); } break; case 2: // Def of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); - MI->addRegOperand(Reg, MachineOperand::Def); + MI->addRegOperand(Reg, true); } break; case 3: { // Immediate. diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 317c1e90bf..b1f70cdf22 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3547,7 +3547,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, MachineInstr *PHI = PHINodesToUpdate[i].first; assert(PHI->getOpcode() == TargetInstrInfo::PHI && "This is not a machine PHI node that we are updating!"); - PHI->addRegOperand(PHINodesToUpdate[i].second); + PHI->addRegOperand(PHINodesToUpdate[i].second, false); PHI->addMachineBasicBlockOperand(BB); } return; @@ -3576,11 +3576,11 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, assert(PHI->getOpcode() == TargetInstrInfo::PHI && "This is not a machine PHI node that we are updating!"); if (PHIBB == JT.Default) { - PHI->addRegOperand(PHINodesToUpdate[pi].second); + PHI->addRegOperand(PHINodesToUpdate[pi].second, false); PHI->addMachineBasicBlockOperand(RangeBB); } if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { - PHI->addRegOperand(PHINodesToUpdate[pi].second); + PHI->addRegOperand(PHINodesToUpdate[pi].second, false); PHI->addMachineBasicBlockOperand(BB); } } @@ -3610,7 +3610,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, assert(PHI->getOpcode() == TargetInstrInfo::PHI && "This is not a machine PHI node that we are updating!"); if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) { - PHI->addRegOperand(PHINodesToUpdate[pi].second); + PHI->addRegOperand(PHINodesToUpdate[pi].second, false); PHI->addMachineBasicBlockOperand(BB); } } |