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-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAG.cpp16
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp8
-rw-r--r--lib/Target/ARM/ARMRegisterInfo.cpp4
-rw-r--r--lib/Target/Alpha/AlphaRegisterInfo.cpp44
-rw-r--r--lib/Target/IA64/IA64RegisterInfo.cpp26
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.cpp6
-rw-r--r--lib/Target/Sparc/SparcRegisterInfo.cpp4
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp4
8 files changed, 61 insertions, 51 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index d33e1ecef7..71f2bce118 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -255,11 +255,11 @@ static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI,
// the machine instruction.
unsigned ResultReg =
RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
- MI->addRegOperand(ResultReg, MachineOperand::Def);
+ MI->addRegOperand(ResultReg, true);
for (unsigned i = 1; i != NumResults; ++i) {
const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
assert(RC && "Isn't a register operand!");
- MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def);
+ MI->addRegOperand(RegMap->createVirtualRegister(RC), true);
}
return ResultReg;
}
@@ -291,7 +291,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
- MI->addRegOperand(VReg, MachineOperand::Use);
+ MI->addRegOperand(VReg, false);
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@@ -307,7 +307,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
MI->addImmOperand(C->getValue());
} else if (RegisterSDNode*R =
dyn_cast<RegisterSDNode>(Op)) {
- MI->addRegOperand(R->getReg(), MachineOperand::Use);
+ MI->addRegOperand(R->getReg(), false);
} else if (GlobalAddressSDNode *TGA =
dyn_cast<GlobalAddressSDNode>(Op)) {
MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
@@ -349,7 +349,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
unsigned VReg = getVR(Op, VRBaseMap);
- MI->addRegOperand(VReg, MachineOperand::Use);
+ MI->addRegOperand(VReg, false);
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@@ -402,7 +402,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
if (MRegisterInfo::isVirtualRegister(Reg)) {
VRBase = Reg;
- MI->addRegOperand(Reg, MachineOperand::Def);
+ MI->addRegOperand(Reg, true);
break;
}
}
@@ -529,13 +529,13 @@ void ScheduleDAG::EmitNode(SDNode *Node,
case 1: // Use of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addRegOperand(Reg, MachineOperand::Use);
+ MI->addRegOperand(Reg, false);
}
break;
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addRegOperand(Reg, MachineOperand::Def);
+ MI->addRegOperand(Reg, true);
}
break;
case 3: { // Immediate.
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 317c1e90bf..b1f70cdf22 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3547,7 +3547,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
MachineInstr *PHI = PHINodesToUpdate[i].first;
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!");
- PHI->addRegOperand(PHINodesToUpdate[i].second);
+ PHI->addRegOperand(PHINodesToUpdate[i].second, false);
PHI->addMachineBasicBlockOperand(BB);
}
return;
@@ -3576,11 +3576,11 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!");
if (PHIBB == JT.Default) {
- PHI->addRegOperand(PHINodesToUpdate[pi].second);
+ PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(RangeBB);
}
if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
- PHI->addRegOperand(PHINodesToUpdate[pi].second);
+ PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(BB);
}
}
@@ -3610,7 +3610,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!");
if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
- PHI->addRegOperand(PHINodesToUpdate[pi].second);
+ PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(BB);
}
}
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index c5eef11952..9e6708141a 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -107,7 +107,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
assert (Offset >= 0);
if (Offset < 4096) {
// Replace the FrameIndex with r13
- MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13);
+ MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13, false);
// Replace the ldr offset with Offset
MI.getOperand(OffIdx).ChangeToImmediate(Offset);
} else {
@@ -117,7 +117,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
// Replace the FrameIndex with r12
- MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
+ MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
}
}
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 772840a3eb..1b6fa44908 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -67,14 +67,18 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
- //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
+ //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
+ //<< FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
if (RC == Alpha::F4RCRegisterClass)
- BuildMI(MBB, MI, Alpha::STS, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ BuildMI(MBB, MI, Alpha::STS, 3)
+ .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass)
- BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ BuildMI(MBB, MI, Alpha::STT, 3)
+ .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::GPRCRegisterClass)
- BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ BuildMI(MBB, MI, Alpha::STQ, 3)
+ .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
abort();
}
@@ -84,13 +88,17 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
- //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
+ //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to "
+ //<< FrameIdx << "\n";
if (RC == Alpha::F4RCRegisterClass)
- BuildMI(MBB, MI, Alpha::LDS, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ BuildMI(MBB, MI, Alpha::LDS, 2, DestReg)
+ .addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass)
- BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ BuildMI(MBB, MI, Alpha::LDT, 2, DestReg)
+ .addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::GPRCRegisterClass)
- BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg)
+ .addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
abort();
}
@@ -243,7 +251,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
int FrameIndex = MI.getOperand(i).getFrameIndex();
// Add the base register of R30 (SP) or R15 (FP).
- MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30);
+ MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
// Now add the frame object offset to the offset from the virtual frame index.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
@@ -256,11 +264,12 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
" for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
if (Offset > IMM_HIGH || Offset < IMM_LOW) {
- DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: " << Offset << "\n");
- //so in this case, we need to use a temporary register, and move the original
- //inst off the SP/FP
+ DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: "
+ << Offset << "\n");
+ //so in this case, we need to use a temporary register, and move the
+ //original inst off the SP/FP
//fix up the old:
- MI.getOperand(i + 1).ChangeToRegister(Alpha::R28);
+ MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
//insert the new
MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
@@ -335,9 +344,11 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
//now if we need to, save the old FP and set the new
if (FP)
{
- BuildMI(MBB, MBBI, Alpha::STQ, 3).addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
+ BuildMI(MBB, MBBI, Alpha::STQ, 3)
+ .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
//this must be the last instr in the prolog
- BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15).addReg(Alpha::R30).addReg(Alpha::R30);
+ BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15)
+ .addReg(Alpha::R30).addReg(Alpha::R30);
}
}
@@ -346,7 +357,8 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
- assert(MBBI->getOpcode() == Alpha::RETDAG || MBBI->getOpcode() == Alpha::RETDAGp
+ assert(MBBI->getOpcode() == Alpha::RETDAG ||
+ MBBI->getOpcode() == Alpha::RETDAGp
&& "Can only insert epilog into returning blocks");
bool FP = hasFP(MF);
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index 7fcd502de9..ff927503d6 100644
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -85,7 +85,8 @@ void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
// (SrcReg) DestReg = cmp.eq.unc(r0, r0)
- BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg).addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
+ BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg)
+ .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
else // otherwise, MOV works (for both gen. regs and FP regs)
BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
}
@@ -152,7 +153,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MBB.erase(I);
}
-void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
+void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)const{
unsigned i = 0;
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
@@ -170,7 +171,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
// choose a base register: ( hasFP? framepointer : stack pointer )
unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
// Add the base register
- MI.getOperand(i).ChangeToRegister(BaseRegister);
+ MI.getOperand(i).ChangeToRegister(BaseRegister, false);
// Now add the frame object offset to the offset from r1.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
@@ -181,20 +182,16 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
Offset += MF.getFrameInfo()->getStackSize();
// XXX: we use 'r22' as another hack+slash temporary register here :(
- if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
- //fix up the old:
- MI.getOperand(i).ChangeToRegister(IA64::r22);
- MI.getOperand(i).setUse(); // mark r22 as being used
- // (the bundler wants to know this)
+ if (Offset <= 8191 && Offset >= -8192) { // smallish offset
+ // Fix up the old:
+ MI.getOperand(i).ChangeToRegister(IA64::r22, false);
//insert the new
MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
.addReg(BaseRegister).addImm(Offset);
MBB.insert(II, nMI);
} else { // it's big
//fix up the old:
- MI.getOperand(i).ChangeToRegister(IA64::r22);
- MI.getOperand(i).setUse(); // mark r22 as being used
- // (the bundler wants to know this)
+ MI.getOperand(i).ChangeToRegister(IA64::r22, false);
MachineInstr* nMI;
nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
MBB.insert(II, nMI);
@@ -242,7 +239,8 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
- // XXX FIXME : this code should be a bit more reliable (in case there _isn't_ a pseudo_alloc in the MBB)
+ // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
+ // a pseudo_alloc in the MBB)
unsigned dstRegOfPseudoAlloc;
for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
assert(MBBI != MBB.end());
@@ -284,7 +282,7 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
// adjust stack pointer: r12 -= numbytes
if (NumBytes <= 8191) {
- MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
+ MI=BuildMI(IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
MBB.insert(MBBI, MI);
} else { // we use r22 as a scratch register here
MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes);
@@ -332,7 +330,7 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
if (NumBytes != 0)
{
if (NumBytes <= 8191) {
- MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(NumBytes);
+ MI=BuildMI(IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).addImm(NumBytes);
MBB.insert(MBBI, MI);
} else {
MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index bf50e3579e..34c23bd1fa 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -421,7 +421,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
int FrameIndex = MI.getOperand(i).getFrameIndex();
// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
- MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
+ MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false);
// Take into account whether it's an add or mem instruction
unsigned OffIdx = (i == 2) ? 1 : 2;
@@ -466,8 +466,8 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
"No indexed form of load or store available!");
unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
MI.setOpcode(NewOpcode);
- MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
- MI.getOperand(2).ChangeToRegister(PPC::R0);
+ MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false);
+ MI.getOperand(2).ChangeToRegister(PPC::R0, false);
} else {
if (isIXAddr) {
assert((Offset & 3) == 0 && "Invalid frame offset!");
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 7331ebdbff..81ebdba3f2 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -147,7 +147,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
if (Offset >= -4096 && Offset <= 4095) {
// If the offset is small enough to fit in the immediate field, directly
// encode it.
- MI.getOperand(i).ChangeToRegister(SP::I6);
+ MI.getOperand(i).ChangeToRegister(SP::I6, false);
MI.getOperand(i+1).ChangeToImmediate(Offset);
} else {
// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
@@ -158,7 +158,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
SP::G1).addReg(SP::G1).addReg(SP::I6);
// Insert: G1+%lo(offset) into the user.
- MI.getOperand(i).ChangeToRegister(SP::G1);
+ MI.getOperand(i).ChangeToRegister(SP::G1, false);
MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
}
}
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 89cc8f2c94..e4c05c6db2 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -168,7 +168,7 @@ static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
assert(MO.isReg() && "Expected to fold into reg operand!");
MIB = addFrameReference(MIB, FrameIndex);
} else if (MO.isReg())
- MIB = MIB.addReg(MO.getReg(), MO.getUseType());
+ MIB = MIB.addReg(MO.getReg(), MO.isDef());
else if (MO.isImm())
MIB = MIB.addImm(MO.getImm());
else if (MO.isGlobalAddress())
@@ -795,7 +795,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
// This must be part of a four operand memory reference. Replace the
// FrameIndex with base register with EBP. Add add an offset to the offset.
- MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP);
+ MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP, false);
// Now add the frame object offset to the offset from EBP.
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-05-04 22:12:59 +0000